VISHAY SI4888DY

SPICE Device Model Si4888DY
Vishay Siliconix
N-Channel Reduced Qg, Fast Switching MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 71714
S-60245Rev. B, 20-Feb-06
www.vishay.com
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SPICE Device Model Si4888DY
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Simulated
Data
Measured
Data
VGS(th)
VDS = VGS, ID = 250 µA
1.1
ID(on)
VDS ≥ 5 V, VGS = 10 V
838
VGS = 10 V, ID = 16 A
0.0054
0.0058
VGS = 4.5 V, ID = 13 A
0.0080
0.0080
Unit
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistancea
rDS(on)
V
A
Ω
Forward Transconductancea
gfs
VDS = 15 V, ID = 16 A
49
38
S
Diode Forward Voltagea
VSD
IS = 3 A, VGS = 0 V
0.74
0.74
V
16
16.3
4
4
Dynamicb
Total Gate Charge
Gate-Source Charge
Qg
Qgs
VDS = 15 V, VGS = 5 V, ID = 16 A
Gate-Drain Charge
Qgd
5.9
5.9
Turn-On Delay Time
td(on)
12
14
10
10
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Source-Drain Reverse Recovery Time
trr
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω
IF = 3 A, di/dt = 100 A/µs
28
44
26
20
32
40
nC
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
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Document Number: 71714
S-60245Rev. B, 20-Feb-06
SPICE Device Model Si4888DY
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 71714
S-60245Rev. B, 20-Feb-06
www.vishay.com
3