16 M EDO DRAM (4-Mword × 4-bit) 4 k Refresh/2 k Refresh LP EO Description HM51W16405 Series HM51W17405 Series E0152H10 (Ver. 1.0) (Previous ADE-203-647D (Z)) Jul. 6, 2001 (K) The HM51W16405 Series, HM51W17405 Series are CMOS dynamic RAMs organized 4,194,304-word × 4-bit. They employ the most advanced CMOS technology for high performance and low power. The HM51W16405 Series, HM51W17405 Series offer Extended Data Out (EDO) Page Mode as a high speed access mode.They have package variations of standard 300-mil 26-pin plastic SOJ and 300-mil 26-pin plastic TSOP. ro Features ct du • Single 3.3 V (±0.3 V) • Access time: 50 ns/60 ns/70 ns (max) • Power dissipation Active mode : 324 mW /288 mW /252 mW (max) (HM51W16405 Series) : 360mW/324 mW/288 mW (max) (HM51W17405 Series) Standby mode : 7.2 mW (max) : 0.36 mW (max) (L-version) • EDO page mode capability • Long refresh period 4096 refresh cycles : 64 ms (HM51W16405 Series) : 128 ms (L-version) 2048 refresh cycles : 32 ms (HM51W17405 Series) : 128 ms (L-version) • 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. EO HM51W16405 Series, HM51W17405 Series • Battery backup operation (L-version) • Test function 16-bit parallel test mode Ordering Information Access time Package HM51W16405S-5 HM51W16405S-6 HM51W16405S-7 50 ns 60 ns 70 ns 300-mil 26-pin plastic SOJ (CP-26/24DB) HM51W16405LS-5 HM51W16405LS-6 HM51W16405LS-7 HM51W17405S-5 HM51W17405S-6 HM51W17405S-7 HM51W17405LS-5 HM51W17405LS-6 HM51W17405LS-7 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 300-mil 26-pin plastic TSOP II (TTP-26/24DA) HM51W16405LTS-5 HM51W16405LTS-6 HM51W16405LTS-7 50 ns 60 ns 70 ns HM51W17405TS-5 HM51W17405TS-6 HM51W17405TS-7 50 ns 60 ns 70 ns HM51W17405LTS-5 HM51W17405LTS-6 HM51W17405LTS-7 50 ns 60 ns 70 ns ct du ro HM51W16405TS-5 HM51W16405TS-6 HM51W16405TS-7 LP Type No. Data Sheet E0152H10 2 EO HM51W16405 Series, HM51W17405 Series Pin Arrangement HM51W16405S/LS Series HM51W16405TS/LTS Series 1 26 VSS VCC 1 26 VSS I/O1 2 25 I/O4 I/O1 2 25 I/O4 I/O2 3 24 I/O3 I/O2 3 24 I/O3 WE 4 23 CAS WE RAS A11 A10 A0 A1 A2 VCC 4 23 CAS 5 22 OE RAS 5 22 OE 6 21 A9 A11 6 21 A9 8 19 A8 A10 8 19 A8 9 18 A7 A0 9 18 A7 10 17 A6 A1 10 17 A6 11 16 A5 A2 11 16 A5 12 15 A4 A3 12 15 A4 13 14 VSS 13 14 VSS (Top view) Pin Description Function A0 to A11 Address input — Row/Refresh address A0 to A11 — Column address A0 to A9 I/O1 to I/O4 Data input/Data output RAS Row address strobe CAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground (Top view) ct Pin name VCC du ro A3 LP VCC Data Sheet E0152H10 3 EO HM51W16405 Series, HM51W17405 Series Pin Arrangement HM51W17405S/LS Series VCC HM51W17405TS/LTS Series 1 26 VSS I/O1 2 25 I/O4 I/O3 I/O2 3 24 I/O3 WE 4 23 CAS 1 26 VSS I/O1 2 25 I/O4 I/O2 3 24 RAS NC A10 A0 A1 A2 VCC 23 CAS 5 22 OE RAS 5 22 OE 6 21 A9 NC 6 21 A9 8 19 A8 A10 8 19 A8 9 18 A7 A0 9 18 A7 10 17 A6 A1 10 17 A6 11 16 A5 A2 11 16 A5 12 15 A4 A3 12 15 A4 13 14 VSS 13 14 VSS ro A3 4 LP WE VCC (Top view) Pin Description A0 to A10 Address input — Row/Refresh address A0 to A10 — Column address A0 to A10 I/O1 to I/O4 Data input/Data output RAS Row address strobe CAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground NC No connection ct Function Data Sheet E0152H10 4 (Top view) du Pin name VCC EO HM51W16405 Series, HM51W17405 Series Block Diagram(HM51W16405 Series) A1 • • • address Column decoder 4M array buffers Row buffers 4M array I/O buffers 4M array I/O1 to I/O4 ro address A11 OE Column • • • A9 A10 WE Timing and control Row decoder to CAS LP A0 RAS 4M array ct du Data Sheet E0152H10 5 EO HM51W16405 Series, HM51W17405 Series Block Diagram(HM51W17405 Series) A1 WE OE Timing and control Column decoder Column • • • A10 • • • address 4M array buffers Row buffers 4M array I/O buffers 4M array ro address Row decoder to CAS LP A0 RAS 4M array ct du Data Sheet E0152H10 6 I/O1 to I/O4 EO HM51W16405 Series, HM51W17405 Series Absolute Maximum Ratings Symbol Value Unit Voltage on any pin relative to V SS VT –0.5 to VCC + 0.5 (≤ +4.6 V (max)) V Supply voltage relative to VSS VCC –0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C –55 to +125 °C LP Parameter Storage temperature Tstg Recommended DC Operating Conditions (Ta = 0 to +70˚C) Parameter Supply voltage Input high voltage Input low voltage Note: Symbol Min Typ Max Unit Notes VCC 3.0 3.3 3.6 V 1, 2 VIH 2.0 — VCC + 0.3 V 1 VIL –0.3 — 0.8 V 1 1. All voltage referred to VSS . ct du ro Data Sheet E0152H10 7 EO HM51W16405 Series, HM51W17405 Series DC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W16405 Series) HM51W16405 -5 -7 Min Max Min Max Min Max Unit Test conditions I CC1 — 90 — 80 — 70 mA t RC = min Standby current I CC2 — 2 — 2 — 2 mA TTL interface RAS, CAS = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z Standby current (L-version) I CC2 — 100 — 100 — 100 µA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — 90 — 80 — 70 mA t RC = min I CC5 — 5 — 5 — 5 mA RAS = VIH CAS = VIL Dout = enable I CC6 — EDO page mode current*1, * 3 I CC7 — Battery backup current I CC10 — Self refresh mode current (L-version) I CC11 — Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 4.6 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 4.6 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0.4 0.4 V Low Iout = 2 mA Operating current* , * 1 2 RAS-only refresh current*2 1 Standby current* CAS-before-RAS refresh current ro Symbol LP Parameter -6 90 — 80 — 70 mA t RC = min 80 — 70 — 65 mA t HPC = min 300 — 300 µA CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 µs t RAS ≤ 0.3 µs 200 — 200 — 200 µA CMOS interface RAS, CAS ≤ 0.2 V Dout = High-Z 0 du 300 — 0 ct Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Data Sheet E0152H10 8 EO HM51W16405 Series, HM51W17405 Series DC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W17405 Series) Parameter HM51W17405 -5 -6 -7 Symbol Min Max Min Max Min Max Unit Test conditions Operating current* , * 2 I CC1 — 100 — 90 — 80 mA t RC = min Standby current I CC2 — 2 — 2 — 2 mA TTL interface RAS, CAS = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC2 — 100 — 100 — 100 µA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — 100 — 90 — 80 mA t RC = min I CC5 — 5 5 — 5 mA RAS = VIH CAS = VIL Dout = enable I CC6 — 100 — 90 — 80 mA t RC = min EDO page mode current*1, * 3 I CC7 — 90 80 — 75 mA t HPC = min Battery backup current I CC10 — Self refresh mode current (L-version) I CC11 — Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 4.6 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 4.6 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0.4 0.4 V Low Iout = 2 mA 1 RAS-only refresh current*2 1 Standby current* CAS-before-RAS refresh current — ro LP Standby current (L-version) — 300 — 300 µA CMOS interface Dout = High-Z, CBR refresh: tRC = 62.5 µs t RAS ≤ 0.3 µs 200 — 200 — 200 µA CMOS interface RAS, CAS ≤ 0.2 V Dout = High-Z 0 du 300 — 0 ct Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Data Sheet E0152H10 9 EO HM51W16405 Series, HM51W17405 Series Capacitance (Ta = 25˚C, VCC = 3.3 V ± 0.3 V) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 7 pF 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. ct du ro LP Data Sheet E0152H10 10 EO HM51W16405 Series, HM51W17405 Series AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *18 Test Conditions Input rise and fall time: 2 ns Input levels: VIL = 0 V, V IH = 3 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) LP • • • • • Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) Parameter HM51W16405/HM51W17405 -5 -6 -7 Min Max Min Max Min Max Unit Random read or write cycle time t RC 84 — 104 — 124 — ns RAS precharge time t RP 30 — 40 — 50 — ns CAS precharge time t CP 8 — 10 — 13 — ns RAS pulse width t RAS 50 10000 60 10000 70 10000 ns 8 10000 10 10000 13 10000 ns 0 — 0 — 0 — ns 8 — 10 — 10 — ns 0 — 0 — 0 — ns 8 — 10 — 13 — ns 12 37 14 45 14 52 ns 3 12 30 12 35 ns 4 13 — 13 — ns 40 — 45 — ns 5 — 5 — ns 15 — 18 — ns 5 0 — 0 — ns 6 0 — 0 — ns 6 2 50 2 t CAS Row address setup time t ASR Row address hold time t RAH Column address setup time t ASC Column address hold time t CAH RAS to CAS delay time t RCD RAS to column address delay time t RAD 10 25 RAS hold time t RSH 10 — CAS hold time t CSH 35 — CAS to RAS precharge time t CRP 5 — OE to Din delay time t OED 13 — OE delay time from Din t DZO 0 — CAS delay time from Din t DZC 0 — Transition time (rise and fall) tT 2 50 ct CAS pulse width du ro Symbol 50 ns Notes 7 Data Sheet E0152H10 11 EO HM51W16405 Series, HM51W17405 Series Read Cycle HM51W16405/HM51W17405 -5 -6 -7 Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC — 50 — 60 — 70 ns 8, 9, 20 Access time from CAS t CAC — 13 — 15 — 18 ns 9, 10, 17, 20 Access time from address t AA — 25 — 30 — 35 ns 9, 11, 17, 20 Access time from OE t OEA — 13 — 15 — 18 ns 9, 20 Read command setup time t RCS 0 — 0 — 0 — ns Read command hold time to CAS t RCH 0 — 0 — 0 — ns Read command hold time from RAS t RCHR 50 — 60 — 70 — ns Read command hold time to RAS t RRH 0 — 0 — 0 — ns Column address to RAS lead time t RAL 25 — 30 — 35 — ns Column address to CAS lead time t CAL 15 — 18 — 23 — ns CAS to output in low-Z t CLZ 0 — 0 — 0 — ns Output data hold time t OH 3 — 3 — 3 — ns Output data hold time from OE t OHO 3 — 3 — 3 — ns Output buffer turn-off time t OFF — 13 — 15 — 15 ns 13, 22 Output buffer turn-off to OE t OEZ — 13 — 15 — 15 ns 13 CAS to Din delay time t CDD 13 — 15 — 18 — ns 5 Output data hold time from RAS t OHR 3 — 3 — 3 — ns 22 Output buffer turn-off to RAS t OFR — 13 22 Output buffer turn-off to WE t WEZ — 13 WE to Din delay time t WED 13 — RAS to Din delay time t RDD 13 — RAS next CAS delay time t RNCD 50 — du ro LP Parameter — 15 — 15 ns — 15 — 15 ns 15 — 18 — ns 15 — 18 — ns 60 — 70 — ns ct Data Sheet E0152H10 12 12 12 22 EO HM51W16405 Series, HM51W17405 Series Write Cycle HM51W16405/HM51W17405 -5 -6 -7 Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns 14 Write command hold time t WCH 8 — 10 — 13 — ns Write command pulse width t WP 8 — 10 — 10 — ns Write command to RAS lead time t RWL 8 — 10 — 13 — ns Write command to CAS lead time t CWL 8 — 10 — 13 — ns Data-in setup time t DS 0 — 0 — 0 — ns 15 t DH 8 — 10 — 13 — ns 15 Notes Data-in hold time LP Parameter Read-Modify-Write Cycle -5 -6 -7 Symbol Min Max Min Max Min Max Unit Read-modify-write cycle time t RWC 111 — 135 — 161 — ns RAS to WE delay time t RWD 67 — 79 — 92 — ns 14 CAS to WE delay time t CWD 30 — 34 — 40 — ns 14 Column address to WE delay time t AWD 42 — 49 — 57 — ns 14 OE hold time from WE t OEH 13 — 15 — 18 — ns Refresh Cycle du ro Parameter HM51W16405/HM51W17405 HM51W16405/HM51W17405 -5 Parameter Symbol -6 -7 Max Min Max Min Max Unit CAS setup time (CBR refresh cycle) t CSR 5 — 5 — 5 — ns CAS hold time (CBR refresh cycle) t CHR 8 — 10 — 10 — ns WE setup time (CBR refresh cycle) t WRP 0 — 0 — 0 — ns WE hold time (CBR refresh cycle) t WRH 8 — 10 — 10 — ns RAS precharge to CAS hold time t RPC 5 — 5 — 5 — ns Notes ct Min Data Sheet E0152H10 13 EO HM51W16405 Series, HM51W17405 Series EDO Page Mode Cycle HM51W16405/HM51W17405 -5 -6 -7 Symbol Min Max Min Max Min Max Unit Notes EDO page mode cycle time t HPC 20 — 25 30 ns 21 EDO page mode RAS pulse width t RASP — 100000 — 100000 — 100000 ns 16 Access time from CAS precharge t CPA — 30 — 35 — 40 ns 9, 17, 20 RAS hold time from CAS precharge t CPRH 30 — 35 — 40 — ns Output data hold time from CAS low t DOH 3 — 3 — 3 — ns CAS hold time referred OE t COL 8 — 10 — 13 — ns CAS to OE setup time t COP 5 — 5 — 5 — ns Read command hold time from CAS precharge t RCHC 30 — 35 — 40 — ns LP Parameter — — 9, 17 EDO Page Mode Read-Modify-Write Cycle HM51W16405/HM51W17405 ro -5 Parameter Symbol EDO page mode read- modify-write t HPRWC cycle time WE delay time from CAS precharge t CPW -6 -7 Max Min Max Min 57 — 68 — 79 ns 45 — 54 — 62 ns 14 Notes Test Mode Cycle *19 du Min Max Unit Notes HM51W16405/HM51W17405 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Test mode WE setup time t WTS 0 — 0 — 0 — ns Test mode WE hold time t WTH 8 — 10 — 10 — ns Parameter Symbol Max Refresh period t REF 64 Refresh period (L-version) t REF 128 Data Sheet E0152H10 14 ct Refresh (HM51W16405 Series) Unit Notes ms 4096 cycles ms 4096 cycles EO HM51W16405 Series, HM51W17405 Series Refresh (HM51W17405 Series) Parameter Symbol Max Unit Notes Refresh period t REF 32 ms 2048 cycles Refresh period (L-version) t REF 128 ms 2048 cycles Self Refresh Mode (L-version) LP Parameter HM51W16405L/HM51W17405L -5 -6 -7 Symbol Min Max Min Max Min Max Unit RAS pulse width (self refresh) t RASS 100 — 100 — 100 — µs RAS precharge time (self refresh) t RPS 90 — 110 — 130 — ns CAS hold time (self refresh) t CHS –50 — –50 — –50 — ns Notes ct du ro Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. Data Sheet E0152H10 15 EO HM51W16405 Series, HM51W17405 Series ct du ro LP 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to device. 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M ×4 are don’t care during test mode. Test mode is set by performing a WE-and-CAS-before-RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular CASbefore-RAS refresh cycle or RAS-only refresh cycle. 20. In a test mode read cycle, the value of tRAC , t AA , t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding theabove value to the specified value in this data sheet. 21. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 22. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH , and between t OFR and t OFF. 23. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS > 100 µs, then RAS precharge time should use tRPS instead of tRP. 24. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. 25. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 2048 cycles (4096 cycles: HM51W16405 Series, 2048 cycles: HM51W17405 Series) of distributed CBR refresh with 15.6 µs interval should be executed within 64 or 32 ms (64 ms: HM51W16405 Series, 32 ms: HM51W17405 Series) immediately after exiting from and before entering into the self refresh mode. 26. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 27. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. Data Sheet E0152H10 16 EO HM51W16405 Series, HM51W17405 Series Timing Waveforms*27 Read Cycle t RC t RAS t RP RAS LP t CSH t CRP t RCD t RSH t CAS tT CAS t RAD t ASR Address t RAH t ASC t RAL t CAL t CAH Column Row ro t RRH t RCHR t RCS WE t DZC t DZO t OEA OE t RDD t OED t OEZ t OHO t OFF t AA ct t CAC t WED t CDD du High-Z Din t RCH t OH t OFR t OHR t RAC t CLZ t WEZ Dout Dout Data Sheet E0152H10 17 EO HM51W16405 Series, HM51W17405 Series Early Write Cycle tRC tRAS tRP RAS tCSH tCRP LP tRCD tRSH tCAS tT CAS tASR Address tRAH Row tASC tCAH Column ro tWCS WE tWCH Din Din High-Z* ct Dout tDH du tDS * t WCS Data Sheet E0152H10 18 t WCS (min) EO HM51W16405 Series, HM51W17405 Series Delayed Write Cycle*18 t RC t RAS t RP RAS t CSH t CRP LP t RCD t RSH t CAS tT CAS t ASR Address t RAH t ASC Row t CAH Column t CWL ro t RCS WE t DZC High-Z Din t DZO t OEH t OED t OEZ t CLZ ct OE t DH du Din t DS t RWL t WP High-Z Dout Invalid Dout Data Sheet E0152H10 19 EO HM51W16405 Series, HM51W17405 Series Read-Modify-Write Cycle *18 t RWC t RAS t RP RAS t RCD LP CAS tT tRAH t ASC Row t CAH Column t CWD ro t RCS WE t CRP t RAD t ASR Address t CAS tCWL t AWD t RWL t RWD t WP t DZC t DS du High-Z Din t DH Din t OED t DZO t OEH t OEA OE t OEZ t AA t RAC t OHO Dout Dout t CLZ Data Sheet E0152H10 20 ct t CAC High-Z EO HM51W16405 Series, HM51W17405 Series RAS-Only Refresh Cycle t RC t RAS t RP RAS t CRP LP CAS tT t ASR Address t RPC t CRP t RAH Row t OFR t OFF ct du ! High-Z ro Dout Data Sheet E0152H10 21 EO HM51W16405 Series, HM51W17405 Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP RAS t RPC t CSR t CHR t CRP LP , t RPC tT CAS t CP WE Address Dout t CP t WRH ro t OFR t OFF t WRP High-Z ct du Data Sheet E0152H10 22 EO HM51W16405 Series, HM51W17405 Series Hidden Refresh Cycle t RC t RAS t RC t RAS t RP t RC t RP t RAS t RP RAS tT LP t RSH t CHR t CRP t RCD CAS t RAD t ASR t RAH Address t RAL t ASC Row t CAH Column t WRH t WRP ro t RRH tWRH t RCS t WRP WE t DZC t RRH t RCH t DZO t OEA OE t CAC t AA t CLZ Dout Dout t CDD t RDD t OED t OFF t OH t OEZ t WEZ t OHO ct t RAC du High-Z Din t WED t OFR t OHR Data Sheet E0152H10 23 EO HM51W16405 Series, HM51W17405 Series EDO Page Mode Read Cycle t RP t RNCD RAS tT t CSH Address Row t HPC t CPRH t CP t tCAH Column 1 tCAS tCAS t RCHC t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CRP RSH t RCH t RCS LP tASR tRAH tASC t CP t CAS t RCHR t RCS WE t HPC t CP t CAS CAS t HPC t RASP t CAL t RRH t RCH t RAL t CAH tASC t WED Column 4 t CAL t CAL tRDD tCDD tDZC Din High-Z tCOL tCOP tOED ro tDZO OE tCPA tOEA tAA tCAC tCAC tAA tWEZ Dout Dout 1 tAA tOEZ tOEA Dout 2 tDOH du tRAC tOEZ tOHO tOFR tOHR tOEZ tCPA tCPA tAA tCAC Dout 2 tOHO Dout 3 tCAC tOHO tOFF tOH tOEA Dout 4 ct Data Sheet E0152H10 24 EO HM51W16405 Series, HM51W17405 Series EDO Page Mode Early Write Cycle tRP tRASP RAS tT tCSH LP CAS tASR Address tHPC tCAS tRCD Row tRAH tASC tCAH Column 1 tWCH WE Din Dout tDH Din 1 tASC tCAH Column 2 tWCH tWCS tDS tDH tCP tCAS tASC tCRP tCAH Column N tWCS tDS tWCH tDH du tDS tRSH tCAS ro tWCS tCP Din 2 Din N High-Z* ct * t WCS t WCS (min) Data Sheet E0152H10 25 EO HM51W16405 Series, HM51W17405 Series EDO Page Mode Delayed Write Cycle *18 t RASP t RP RAS tT t CP LP t CSH t RCD CAS t CRP t CP t HPC t CAS t CAS t RSH t CAS t RAD t ASR t ASC t RAH Address t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL WE t WP t DZC t DS t CWL t RCS t WP t WP t DZC t DS t DZC t DS t DH t DZO t DH Din 2 Din N t DZO # t DZO t DH du Din 1 Din t CWL t RWL t RCS ro t RCS Column N t OED t OEH t OEH OE t CLZ t CLZ t OEZ t OEH t CLZ t OEZ t OEZ ct High-Z Dout Invalid Dout Invalid Dout Data Sheet E0152H10 26 t OED t OED Invalid Dout EO HM51W16405 Series, HM51W17405 Series EDO Page Mode Read-Modify-Write Cycle *18 t RASP t RP RAS tT t HPRWC t RCD CAS t RSH t CP LP t CP t CAS t CAS t CRP t CAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 t RWD Column 2 t CWL t WP t t DZC DS t CWD t RCS t DZO t OED t DH Din N t OED t DZO t OEH t OEH *# t OEH t DH Din 2 t OED t DZO t RWL t WP t t DZC DS du Din 1 t CWL t CWD t WP t t DZC DS t DH Din t CPW t AWD ro t RCS t CWL t AWD t RCS WE Column N t CPW t AWD t CWD t ASC t CAH OE t OHO t OEA t CAC t OHO t OEA t CAC t AA t AA t CPA t RAC t AA t CPA t OEZ t CLZ t CLZ ct t OEZ t CLZ t OHO t OEA t CAC t OEZ High-Z Dout Dout 1 Dout 2 Dout N Data Sheet E0152H10 27 EO HM51W16405 Series, HM51W17405 Series EDO Page Mode Mix Cycle (1) t RP t RASP RAS tT t CAS CAS t CRP t CP t CP t CP t CAS tCAS tCAS LP t CSH tRSH t RCD t WCS WE t ASC tRAH tASR Address Row t WCH tCAH Column 1 t CAL t DS tCPW tAWD t ASC t CAH tASC t CAH Column 2 Column 3 t CAL tASC t RAL t CAH Column 4 t CAL t DH Din 1 tWP High-Z tRDD tCDD t CAL t DH t DS Din 3 ro tOED tWED Din t RRH t RCH t RCS t RCS OE tCPA tAA tOEA Dout tAA tAA t OEZ t DOH tCAC t OHO Dout 2 Dout 3 tOEZ tCAC du tCAC tOFR tWEZ tCPA tCPA tOHO tOEA tOFF tOH Dout 4 ct Data Sheet E0152H10 28 EO HM51W16405 Series, HM51W17405 Series EDO Page Mode Mix Cycle (2) t RNCD t RP t RASP RAS tT t CAS t RCD t ASC tRAH tASR Address Row tCAS tCAS t RCHR t RCS WE t CAS t CRP t CP t CP LP CAS t CSH t RCH tWCS t WCH tCAH Column 1 t ASC t CAH Column 2 Column 3 t DS t CAH tASC Column 4 t CAL t DS t DH tRDD tCDD t DH Din 2 tOED t RAL t CAL ro High-Z Din t CAL t RRH t RCH tWP tCPW t ASC t CAH t CAL tRSH t RCS t RCS Din 3 tOED tCOP tWED tCOL OE tAA tOEA tCAC tOEZ tCPA tAA Dout 1 tOEZ du t OHO tOFR tWEZ tCPA tCAC tRAC Dout t OEA t OHO Dout 3 tAA tCAC tOEZ tOEA tOFF tOH tOHO Dout 4 ct Data Sheet E0152H10 29 EO HM51W16405 Series, HM51W17405 Series Test Mode Cycle *19 Set Cycle** Test Mode Cycle *,** Reset Cycle Normal Mode RAS WE LP CAS * CBR or RAS-only refresh ** Address, Din, OE: H or L ct du ro Data Sheet E0152H10 30 EO HM51W16405 Series, HM51W17405 Series Test Mode Set Cycle t RC t RP t RAS t RP RAS Address t WTH t CP High-Z ct du t CRP ro t OFF t RPC ÃCÃ,ÂÀCB@,À@ t WTS t OFR Dout t CHR tT t CP WE t CSR LP CAS t RPC Data Sheet E0152H10 31 EO HM51W16405 Series, HM51W17405 Series Self Refresh Cycle (L-version)* 23, *24, * 25, * 26 t RASS t RP t RPS RAS tT t CP CAS t CSR t WRP WE t CRP LP , , t RPC t CHS t WRH $%&+, t OFR t OFF ro Dout High-Z ct du Data Sheet E0152H10 32 EO HM51W16405 Series, HM51W17405 Series Package Dimensions HM51W16405S/LS Series HM51W17405S/LS Series (CP-26/24DB) Unit: mm 1.30 Max ro 0.43 ± 0.10 0.41 ± 0.08 8.51 ± 0.13 7.62 ± 0.13 13 1.27 2.54 Dimension including the plating thickness Base material dimension 2.65 ± 0.12 6 8 0.74 0.80 +0.25 –0.17 1 14 3.50 ± 0.26 LP 26 16.90 17.27 Max 21 19 + 0.19 6.79 – 0.18 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) CP-26/24DB Conforms Conforms 0.8 g ct du Data Sheet E0152H10 33 EO HM51W16405 Series, HM51W17405 Series HM51W16405TS/LTS Series HM51W17405TS/LTS Series (TTP-26/24DA) Unit: mm 13 0.80 0.21 M 9.22 ± 0.20 0.10 Dimension including the plating thickness Base material dimension 0.145 ± 0.05 0.125 ± 0.04 2.54 0° – 5° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-26/24DA Conforms — 0.30 g ct du ro 1.20 Max 1.15 Max 0.68 0.42 ± 0.08 0.40 ± 0.06 6 8 1.27 0.13 ± 0.05 1 7.62 14 LP 26 17.14 17.54 Max 21 19 Data Sheet E0152H10 34 EO HM51W16405 Series, HM51W17405 Series Cautions ct du ro LP 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. Data Sheet E0152H10 36