UCC2818A-Q1 www.ti.com SLUSA21 – FEBRUARY 2010 BiCMOS POWER-FACTOR PREREGULATOR Check for Samples: UCC2818A-Q1 FEATURES 1 • • • • • • • • • • • • • • Qualified for Automotive Applications Controls Boost Preregulator to Near-Unity Power Factor Limits Line Distortion World-Wide Line Operation Overvoltage Protection Accurate Power Limiting Average Current Mode Control Improved Noise Immunity Improved Feed-Forward Line Regulation Leading Edge Modulation 150-mA Typical Start-Up Current Low-Power BiCMOS Operation 12-V to 17-V Operation Frequency Range of 6 kHz to 220 kHz D PACKAGE (TOP VIEW) GND 1 16 DRVOUT PKLMT 2 15 VCC CAOUT 3 14 CT CAI 4 13 SS MOUT 5 12 RT IAC 6 11 VSENSE VAOUT 7 10 OVP/EN VFF 8 9 VREF DESCRIPTION/ORDERING INFORMATION The UCC2818A provides all the functions necessary for active power factor corrected preregulators. The controller achieves near unity power factor by shaping the ac input line current waveform to correspond to that of the ac input line voltage. Average current mode control maintains stable, low distortion sinusoidal line current. Designed in Texas Instrument’s BiCMOS process, the UCC2818A offers new features such as lower start-up current, lower power dissipation, overvoltage protection, a shunt UVLO detect circuitry, a leading-edge modulation technique to reduce ripple current in the bulk capacitor and an improved, low-offset (±2 mV) current amplifier to reduce distortion at light load conditions. The UCC2818A PFC controller is directly pin-for-pin compatible with the UCC2818 devices. Only the output stage of UCC2818A has been modified to allow use of a smaller external gate drive resistor values. For some power supply designs where an adequately high enough gate drive resistor can not be used, the UCC2818A offers a more robust output stage at the cost of increasing the internal gate resistances. The gate drive of the UC2818A, however, remains strong at ±1.2 A of peak current capability. UCC2818A is intended for applications with a fixed supply (VCC). It is available in the 16-pin D package. ORDERING INFORMATION (1) PACKAGE (2) TJ = TA –40°C to 125°C (1) (2) SOIC – D Reel of 2500 ORDERABLE PART NUMBER UCC2818AQDRQ1 TOP-SIDE MARKING 2818AQ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated UCC2818A-Q1 SLUSA21 – FEBRUARY 2010 www.ti.com BLOCK DIAGRAM VCC 15 OVP/EN 10 7.5-V Reference 16 V (For UCC2817 Only) SS VSENSE 16 DRVOUT 1 GND 2 PKLMT UVLO ENABLE − + 7 11 − 7.5 V VFF VREF 13 1.9 V VAOUT 9 0.33 V Voltage Error Amplifier + VCC + X P Mult X Current Amplifier 8V OVP + − − − + PWM S + X2 8 16 V/10 V (UCC2817) 10.5 V/10 V (UCC2818) Zero Power − PWM Latch OSC R CLK Mirror 2:1 Q R CLK IAC Oscillator 6 − + MOUT 5 4 3 12 14 CAI CAOUT RT CT UDG-98182 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT VCC Supply voltage 18 V ICC Supply current 20 mA Gate drive current, continuous 0.2 A Gate drive current 1.2 A Input voltage Input current Maximum negative voltage CAI, MOUT, SS 8 PKLMT 5 VSENSE, OVP/EN 10 RT, IAC, PKLMT 10 VCC (no switching) 20 DRVOUT, PKLMT, MOUT Power dissipation V mA –0.5 V 1 W 73.1 °C/W qJA Package thermal impedance (2) TJ Junction temperature –40 to 150 °C Tstg Storage temperature range –65 to 150 °C (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. he package thermal impedance is calculated in accordance with JESD 51-5. ELECTROSTATIC DISCHARGE RATINGS (1) PARAMETER ESD (1) 2 TEST CONDITIONS Electrostatic discharge rating Human-body model (HBM) MAX UNIT 1000 V ESD testing performed in accordance with AEC-Q100. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 UCC2818A-Q1 www.ti.com SLUSA21 – FEBRUARY 2010 ELECTRICAL CHARACTERISTICS TJ = TA = –40°C to 125°C, VCC = 12 V, RT = 22 kΩ, CT = 270 pF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Current Supply current, off VCC = (VCC turn-on threshold – 0.3 V) Supply current, on VCC = 12 V, No load on DRVOUT 150 300 mA 2 4 6 mA VCC turn-on threshold 9.7 10.2 10.9 VCC turn-off threshold 9.4 9.7 V UVLO hysteresis 0.3 0.5 V 7.369 7.5 7.631 V 50 200 nA UVLO V Voltage Amplifier Input voltage VSENSE bias current VSENSE = VREF, VAOUT = 2.5 V Open-loop gain VAOUT = 2 V to 5 V 50 90 High-level output voltage IL = –150 mA 5.3 5.5 5.6 V Low-level output voltage IL = 150 mA 0 50 150 mV dB Overvoltage Protection and Enable VREF + 0.48 Overvoltage reference VREF VREF + 0.5 + 0.52 V Hysteresis 300 500 600 mV Enable threshold 1.7 1.9 2.1 V Enable hysteresis 0.1 0.2 0.3 V –3.5 0 3 Current Amplifier TA = 25°C Input offset voltage VCM = 0 V, VCAOUT = 3 V Input bias current VCM = 0 V, VCAOUT = 3 V Input offset current VCM = 0 V, VCAOUT = 3 V Open-loop gain VCM = 0 V, VCAOUT = 2 V to 5 V 90 Common-mode rejection ratio VCM = 0 V to 1.5 V, VCAOUT = 3 V 60 80 High-level output voltage IL = –120 mA 5.6 6.5 6.9 Low-level output voltage IL = 1 mA 0.1 0.2 0.5 TA = –40°C to 125°C –5 Gain bandwidth product (1) 5 mV –50 –100 nA 25 100 nA dB dB 2.5 V V MHz Voltage Reference 7.313 to 7.687 Input voltage 7.5 7.631 V Load regulation IREF = 1 mA to 2 mA 0 10 mV Line regulation VCC = 10.8 V to 15 V (2) 0 10 mV Short-circuit current VREF = 0 V –20 –25 –50 mA Initial accuracy TA = 25°C 85 100 115 kHz Voltage stability VCC = 10.8 V to 15 V –1 +1 % Total variation Over line and temperature 80 120 kHz Oscillator Ramp peak voltage 4.5 5 5.5 V Ramp amplitude voltage (peak to peak) 3.5 4 4.5 V 15 mV 350 550 ns Peak Current Limit (1) (2) PKLMT reference voltage –15 PKLMT propagation delay 150 Ensured by design, not production tested Reference variation for VCC < 10.8 V is shown in Figure 8. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 3 UCC2818A-Q1 SLUSA21 – FEBRUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = TA = –40°C to 125°C, VCC = 12 V, RT = 22 kΩ, CT = 270 pF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Multiplier IMOUT IMOUT High line, low power output current IAC = 500 mA, VFF = 4.7 V, VAOUT = 1.25 V 0 –6 –23 High-line, high-power output current IAC = 500 mA, VFF = 4.7 V, VAOUT = 5 V –70 –90 –105 Low-line, low-power output current IAC = 150 mA, VFF = 1.4 V, VAOUT = 1.25 V –10 –19 –50 Low-line, high-power output current IAC = 150 mA, VFF = 1.4 V, VAOUT = 5 V –268 –300 –345 IAC limited output current IAC = 150 mA, VFF = 1.3 V, VAOUT = 5 V –250 –300 –400 Gain constant (K) IAC = 200 mA, VFF = 3 V, VAOUT = 2.5 V 0.5 1 1.6 IAC = 150 mA, VFF = 1.4 V, VAOUT = 0.25 V 0 –2 IAC = 500 mA, VFF = 4.7 V, VAOUT = 0.25 V 0 –2 IAC = 500 mA, VFF = 4.7 V, VAOUT = 0.5 V 0 –3.5 Zero current Power limit (IMOUT × VFF) mA 1/V mA IAC = 150 mA, VFF = 1.4 V, VAOUT = 5 V –375 –420 –490 mW IAC = 300 mA –140 –150 –160 mA –6 –10 –17 mA 9 12 Ω Feed Forward VFF output current Soft Start Softstart charge current Gate Driver Pullup resistance IO = –100 mA to –200 mA Pulldown resistance IO = 100 mA 4 10 Ω Output rise time CL = 1 nF, RL = 10 Ω, VDRVOUT = 0.7 V to 9 V 25 50 ns Output fall time CL = 1 nF, RL = 10 Ω, VDRVOUT = 9 V to 0.7 V 10 50 ns 95 99 % 2 % 0.5 V Maximum duty cycle Minimum controlled duty cycle (3) 93 At 100 kHz Zero Power Zero-power comparator threshold (3) 4 Measured on VAOUT 0.2 0.33 Ensured by design, not production tested Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 UCC2818A-Q1 www.ti.com SLUSA21 – FEBRUARY 2010 PIN ASSIGNMENTS TERMINAL NAME CAI NO. I/O DESCRIPTION 4 I Current amplifier noninverting input CAOUT 3 O Current amplifier output CT 24 I Oscillator timing capacitor DRVOUT 26 O Gate drive GND 2 – Ground IAC 6 I Current proportional to input voltage MOUT 5 I/O OVP/EN 20 I Overvoltage/enable PKLMT 3 I PFC peak current limit RT 23 I Oscillator charging current SS 24 I Soft-start VAOUT 7 O Voltage amplifier output VCC 25 I Positive supply voltage VFF 8 I Feed-forward voltage VSENSE 11 I Voltage amplifier inverting input VREF 9 O Voltage reference output Multiplier output and current amplifier inverting input Pin Descriptions CAI: Current amplifier noninverting input. Place a resistor between this pin and the GND side of current sense resistor. This input and the inverting input (MOUT) remain functional down to and below GND. CAOUT: Current amplifier output. This is the output of a wide bandwidth operational amplifier that senses line current and commands the PFC pulse-width modulator (PWM) to force the correct duty cycle. Compensation components are placed between CAOUT and MOUT. CT: Oscillator timing capacitor. A capacitor from CT to GND sets the PWM oscillator frequency according to: f[ ǒRT0.6CTǓ The lead from the oscillator timing capacitor to GND should be as short and direct as possible. DRVOUT: Gate drive. The output drive for the boost switch is a totem-pole MOSFET gate driver on DRVOUT. Use a series gate resistor to prevent interaction between the gate impedance and the output driver that might cause the DRVOUT to overshoot excessively. See characteristic curve (Figure 13) to determine minimum required gate resister value. Some overshoot of the DRVOUT output is always expected when driving a capacitive load. GND: Ground. All voltages measured with respect to ground. VCC and REF should be bypassed directly to GND with a 0.1-mF or larger ceramic capacitor. IAC: Current proportional to input voltage. This input to the analog multiplier is a current proportional to instantaneous line voltage. The multiplier is tailored for very low distortion from this current input (IIAC) to multiplier output. The recommended maximum IIAC is 500 mA. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 5 UCC2818A-Q1 SLUSA21 – FEBRUARY 2010 www.ti.com MOUT: Multiplier output and current amplifier inverting input. The output of the analog multiplier and the inverting input of the current amplifier are connected together at MOUT. As the multiplier output is a current, this is a high-impedance input so the amplifier can be configured as a differential amplifier. This configuration improves noise immunity and allows for the leading-edge modulation operation. The multiplier output current is limited to (2 × IIAC). The multiplier output current is given by the equation: I MOUT I + IAC (V VAOUT 2 K V VFF * 1) Where: K = 1/V is the multiplier gain constant OVP/EN: Overvoltage/enable. A window comparator input that disables the output driver if the boost output voltage is a programmed level above the nominal, or disables both the PFC output driver and resets SS if pulled below 1.9 V (typ). PKLMT: PFC peak current limit. The threshold for peak limit is 0 V. Use a resistor divider from the negative side of the current sense resistor to VREF to level shift this signal to a voltage level defined by the value of the sense resistor and the peak current limit. Peak current limit is reached when PKLMT voltage falls below 0 V. RT: Oscillator charging current. A resistor from RT to GND is used to program oscillator charging current. A resistor between 10 kΩ and 100 kΩ is recommended. Nominal voltage on this pin is 3 V. SS: Soft-start. VSS is discharged for VVCC low conditions. When enabled, SS charges an external capacitor with a current source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty cycle to increase slowly. In the event of a VVCC dropout, the OVP/EN is forced below 1.9 V (typ), SS quickly discharges to disable the PWM. Note: In an open-loop test circuit, grounding the SS pin does not ensure 0% duty cycle. See the application section for details. VAOUT: Voltage amplifier output. This is the output of the operational amplifier that regulates output voltage. The voltage amplifier output is internally limited to approximately 5.5 V to prevent overshoot. VCC: Positive supply voltage. Connect to a stable source of at least 20 mA between 10 V and 17 V for normal operation. Bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To prevent inadequate gate drive signals, the output devices are inhibited unless VVCC exceeds the upper under-voltage lockout voltage threshold and remains above the lower threshold. VFF: Feed-forward voltage. The RMS voltage signal generated at this pin by mirroring 1/2 of the IIAC into a single pole external filter. At low line, the VFF voltage should be 1.4 V. VSENSE: Voltage amplifier inverting input. This is normally connected to a compensation network and to the boost converter output through a divider network. VREF: Voltage reference output. VREF is the output of an accurate 7.5-V voltage reference. This output is capable of delivering 20 mA to peripheral circuitry and is internally short-circuit current limited. VREF is disabled and remains at 0 V when VVCC is below the UVLO threshold. Bypass VREF to GND with a 0.1-mF or larger ceramic capacitor for best stability. See Figure 8 and Figure 9 for VREF line and load regulation characteristics. 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 UCC2818A-Q1 www.ti.com SLUSA21 – FEBRUARY 2010 APPLICATION INFORMATION The UCC2818A is a BiCMOS average current mode boost controller for high-power-factor high-efficiency preregulator power supplies. Figure 1 shows the UCC2818A in a 250-W PFC preregulator circuit. Off-line switching power converters normally have an input current that is not sinusoidal. The input current waveform has a high harmonic content because current is drawn in pulses at the peaks of the input voltage waveform. An active power-factor correction circuit programs the input current to follow the line voltage, forcing the converter to look like a resistive load to the line. A resistive load has 0° phase displacement between the current and voltage waveforms. Power factor (PF) can be defined in terms of the phase angle between two sinusoidal waveforms of the same frequency: PF = cos θ (1) Therefore, a purely resistive load would have a power factor of 1. In practice, power factors of 0.999 with total harmonic distortion (THD) of less than 3% are possible with a well-designed circuit. Following guidelines are provided to design PFC boost converters using the UCC2818A. NOTE: Schottky diodes, D5 and D6, are required to protect the PFC controller from electrical over stress during system power up. C10 1 µF R16 100Ω C11 1 µF VCC R21 383k R15 24k R13 383k D7 IAC R18 24k AC2 L1 1mH VO D1 8A, 600V F1 + C14 1.5µ F 400V VLINE 85270 V AC D8 D2 6A, 600V C13 0.47µ F 600V R14 0.25Ω 3W 6A 600V R17 20Ω UCC2817A R9 4.02k R12 2k VOUT C12 385VDC 220µ F 450V Q1 IRFP450 D3 AC1 R10 4.02k 1 GND VOUTDR 16 2 PKLIMIT 3 CAOUT 4 CAI 5 MOUT CT 14 6 IAC SS 13 RT 12 VSENSE 11 D4 VCC VCC D5 R11 10k VREF R8 12k C3 1µ F CER 15 C2 100µ F AI EI C1 560pF C9 1.2nF C4 0.01µ F C8 270pF R1 12k D6 C7 150nF R7 100k C15 2.2µ F 7 VAOUT 8 VFF R3 20k R19 499k VO R20 274k R4 249k R2 499k C6 2.2µ F OVP/EN 10 R6 30k C5 1µF VREF R5 10k 9 VREF Figure 1. Typical Application Circuit Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 7 UCC2818A-Q1 SLUSA21 – FEBRUARY 2010 www.ti.com Power Stage LBOOST: The boost inductor value is determined by Equation 2: L BOOST + ǒVIN(min) (DI Ǔ D fs) (2) Where: D = Duty cycle ΔI = Inductor ripple current fS = Switching frequency For the example circuit, a switching frequency of 100 kHz, a ripple current of 875 mA, a maximum duty cycle of 0.688, and a minimum input voltage of 85 VRMS produces a boost inductor value of about 1 mH. The values used in this equation are at the peak of low line, where the inductor current and its ripple are at a maximum. COUT: Two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor. The value of capacitance is determined by the holdup time required for supporting the load after input ac voltage is removed. Holdup is the amount of time that the output stays in regulation after the input has been removed. For this circuit, the desired holdup time is approximately 16 ms. Expressing the capacitor value in terms of output power, output voltage, and holdup time gives Equation 3: C OUT + ǒ2 P OUT Dt Ǔ ǒVOUT2 * VOUT(min)2Ǔ (3) In practice, the calculated minimum capacitor value may be inadequate because output ripple voltage specifications limit the amount of allowable output capacitor ESR. Attaining a sufficiently low value of ESR often necessitates the use of a much larger capacitor value than calculated. The amount of output capacitor ESR allowed can be determined by dividing the maximum specified output ripple voltage by the inductor ripple current. In this design holdup time was the dominant determining factor and a 220-mF, 450-V capacitor was chosen for the output voltage level of 385 VDC at 250 W. Power switch selection: As in any power-supply design, tradeoffs between performance, cost, and size have to be made. When selecting a power switch, it can be useful to calculate the total power dissipation in the switch for several different devices at the switching frequencies being considered for the converter. Total power dissipation in the switch is the sum of switching loss and conduction loss. Switching losses are the combination of the gate charge loss, COSS loss, and turnon and turnoff losses: PGATE = QGATE × VGATE × fs P +1 COSS 2 P 8 ON )P OFF C OSS +1 2 V V2 OFF OFF I L fs (4) ǒt ON ) tOFFǓ fs Submit Documentation Feedback (5) Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 UCC2818A-Q1 www.ti.com SLUSA21 – FEBRUARY 2010 Where: QGATE = Total gate charge VGATE = Gate drive voltage fS = Clock frequency COSS = Drain source capacitance of the MOSFET IL = Peak inductor current tON and tOFF = Switching times (estimated using device parameters RGATE, QGD and VTH) VOFF = Voltage across the switch during the off time (in this case VOFF = VOUT) Conduction loss is calculated as the product of the RDS(on) of the switch (at the worst-case junction temperature) and the square of RMS current: PCOND = RDS(on) × K × I2RMS (6) Where: K = temperature factor found in the manufacturer's RDS(on) vs junction temperature curves Calculating these losses and plotting against frequency gives a curve that enables the designer to determine which manufacturer's device has the best performance at the desired switching frequency, or which switching frequency has the least total loss for a particular power switch. For this design example, an IRFP450 HEXFET™ from International Rectifier was chosen because of its low RDS(on) and its VDSS rating. The IRFP450 RDS(on) of 0.4 Ω and the maximum VDSS of 500 V made it an ideal choice. A review of this procedure can be found in the Unitrode™ Power-Supply Design Seminar SEM1200, Topic 6, Design Review: 140 W (Multiple Output High Density DC/DC Converter). Soft Start The soft-start circuitry is used to prevent overshoot of the output voltage during start up. This is accomplished by slowly bringing up the voltage amplifier output (VVAOUT), which allows for the PWM duty cycle to slowly increase. Use Equation 7 to select a capacitor for the soft-start pin. In this example, tDELAY = 7.5 ms, which yields a CSS of 10 nF. 10 mA t DELAY C + SS 7.5 V (7) In an open-loop test circuit, shorting the soft-start pin to ground does not ensure 0% duty cycle. This is due to the current amplifiers input offset voltage, which could force the current amplifier output high or low depending on the polarity of the offset voltage. However, in the typical application, there is sufficient amount of inrush and bias current to overcome the current amplifier offset voltage. Multiplier The output of the multiplier of the UCC2818A is a signal representing the desired input line current. It is an input to the current amplifier, which programs the current loop to control the input current to give high power factor operation. As such, the proper functioning of the multiplier is key to the success of the design. The inputs to the multiplier are VAOUT, the voltage amplifier error signal, IIAC, a representation of the input rectified ac line voltage, and an input voltage feed-forward signal, VVFF. The output of the multiplier, IMOUT, can be expressed as: I MOUT +I ǒVVAOUT * 1Ǔ IAC K V 2 VFF (8) Where: K = Constant typically equal to 1/V Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 9 UCC2818A-Q1 SLUSA21 – FEBRUARY 2010 www.ti.com The Electrical Characteristics table covers all the required operating conditions for designing with the multiplier. Additionally, curves in Figure 10, Figure 11, and Figure 12 provide typical multiplier characteristics over its entire operating range. The IIAC signal is obtained through a high-value resistor connected between the rectified ac line and the IAC pin of the UCC2818A. This resistor RIAC is sized to give the maximum IIAC current at high line. For the UCC2818A, the maximum IIAC current is about 500 mA. A higher current than this can drive the multiplier out of its linear range. A smaller current level is functional, but noise can become an issue, especially at low input line. Assuming a universal line operation of 85 VRMS to 265 VRMS gives a RIAC value of 750 kΩ, because of voltage-rating constraints of a standard 1/4-W resistor, use a combination of lower-value resistors connected in series to give the required resistance and distribute the high voltage amongst the resistors. For this design example, two 383-kΩ resistors were used in series. The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage feed-forward signal proportional to line voltage. The VFF voltage is used to keep the power-stage gain constant, and to provide input power limiting.See the TI application report SLUA196 for detailed explanation on how the VFF pin provides power limiting. The following equation can be used to size the VFF resistor RVFF to provide power limiting where VIN(min) is the minimum RMS input voltage, and RIAC is the total resistance connected between the IAC pin and the rectified line voltage. 1.4 V R + [ 30 kW VFF V 0.9 IN(min) 2 R IAC (9) Because the VFF voltage is generated from line voltage, it needs to be adequately filtered to reduce THD caused by the 120-Hz rectified line voltage. Refer to Unitrode Power-Supply Design Seminar, SEM-700 Topic 7 (Optimizing the Design of a High Power Factor Preregulator). A single pole filter was adequate for this design. Assuming that an allocation of 1.5% total harmonic distortion from this input is allowed, and that the second harmonic ripple is 66% of the input ac line voltage, the amount of attenuation required by this filter is: 1.5 % + 0. 022 66 % (10) A ripple frequency (fR) of 120 Hz and an attenuation of 0.022 requires that the pole of the filter (fP) be placed at: fP = 120 Hz × 0.022 ≈ 2.6 Hz (11) The following equation can be used to select the filter capacitor CVFF required to produce the desired low-pass filter. 1 C + [ 2.2 mF VFF 2 p R f VFF P (12) The RMOUT resistor is sized to match the maximum current through the sense resistor to the maximum multiplier current. The maximum multiplier current, or IMOUT(max), can be determined by the equation: I I MOUT(max) + @V IAC IN(min) K ǒVVAOUT(max) * 1 VǓ V 2 VFF (min) (13) IMOUT(max) for this design is approximately 315 mA. The RMOUT resistor can then be determined by: V RSENSE R + MOUT I MOUT(max) (14) In this example, VRSENSE was selected to give a dynamic operating range of 1.25 V, which gives an RMOUT of roughly 3.91 kΩ. 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 UCC2818A-Q1 www.ti.com SLUSA21 – FEBRUARY 2010 Voltage Loop The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic of the line frequency. This ripple is fed back through the error amplifier and appears as a third harmonic ripple at the input to the multiplier. The voltage loop must be compensated not just for stability but also to attenuate the contribution of this ripple to the total harmonic distortion of the system (see Figure 2). Cf VOUT CZ Rf RIN − RD + VREF Figure 2. Voltage Amplifier Configuration The gain of the voltage amplifier, GVA, can be determined by first calculating the amount of ripple present on the output capacitor. The peak value of the second harmonic voltage is given by the equation: P IN V + OPK 2p f C V R OUT OUT (15) In this example, VOPK = 3.91 V. Assuming an allowable contribution of 0.75% (1.5% peak to peak) from the voltage loop to the THD budget, set the gain equal to: G VA + ǒDVVAOUTǓ 0.015 2 V OPK (16) Where: ΔVVAOUT = Effective output voltage range of the error amplifier (5 V for the UCC2818A). The network needed to realize this filter is comprised of an input resistor, RIN, and feedback components Cf, CZ, and Rf. The value of RIN is already determined because of its function as one-half of a resistor divider from VOUT feeding back to the voltage amplifier for output voltage regulation. In this case, the value was chosen to be 1 MΩ. This high value was chosen to reduce power dissipation in the resistor. In practice, the resistor value would be realized by the use of two 500-kΩ resistors in series because of the voltage rating constraints of most standard 1/4-W resistors. The value of Cf is determined by the equation: 1 C + f 2p f G R R VA IN (17) In this example, Cf = 150 nF. Resistor Rf sets the dc gain of the error amplifier and, thus, determines the frequency of the pole of the error amplifier. The location of the pole can be found by setting the gain of the loop equation to one and solving for the crossover frequency. The frequency, expressed in terms of input power, can be calculated by the equation: P 2 IN + f VI 2 (2 p) DV V R C C VAOUT OUT IN OUT f (18) fVI for this converter is 10 Hz. A derivation of this equation can be found in the Unitrode Power Supply Design Seminar SEM1000, Topic 1 (A 250-kHz, 500-W Power Factor Correction Circuit Employing Zero Voltage Transitions). Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 11 UCC2818A-Q1 SLUSA21 – FEBRUARY 2010 www.ti.com Solving for Rf becomes: 1 R + f 2p f C VI f (19) or Rf = 100 kΩ. Due to the low output impedance of the voltage amplifier, capacitor CZ was added in series with RF to reduce loading on the voltage divider. To ensure the voltage loop crossed over at fVI, CZ was selected to add a zero at 1/10th of fVI. For this design, a 2.2-mF capacitor was chosen for CZ. The following equation can be used to calculate CZ: 1 C + Z f VI R 2 p f 10 (20) Current Loop The gain of the power stage is: V R SENSE G (s) + OUT ID s L V BOOST P (21) RSENSE has been chosen to give the desired differential voltage for the current sense amplifier at the desired current limit point. In this example, a current limit of 4 A and a reasonable differential voltage to the current amplifier of 1 V gives a RSENSE value of 0.25 Ω. VP in this equation is the voltage swing of the oscillator ramp, 4 V for the UCC2818A. Setting the crossover frequency of the system to 1/10th of the switching frequency, or 10 kHz, requires a power-stage gain at that frequency of 0.383. In order for the system to have a gain of 1 at the crossover frequency, the current amplifier must have a gain of 1/GID at that frequency. GEA, the current amplifier gain is then: G + 1 + 1 + 2.611 EA 0.383 G ID (22) RI is the RMOUT resistor, previously calculated to be 3.9 kΩ (see Figure 3). The gain of the current amplifier is Rf/RI, so multiplying RI by GEA gives the value of Rf, in this case approximately 12 kΩ. Setting a zero at the crossover frequency and a pole at one-half the switching frequency completes the current loop compensation. 1 C + Z 2 p R f f C (23) 1 C + P fs 2 p R f 2 (24) C C Rf R P Z I − CAOUT + Figure 3. Current Loop Compensation The UCC2818A current amplifier has the input from the multiplier applied to the inverting input. This change in architecture from previous TI PFC controllers improves noise immunity in the current amplifier. It also adds a 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 UCC2818A-Q1 www.ti.com SLUSA21 – FEBRUARY 2010 phase inversion into the control loop. The UCC2818A takes advantage of this phase inversion to implement leading-edge duty cycle modulation. Synchronizing a boost PFC controller to a downstream dc-to-dc controller reduces the ripple current seen by the bulk capacitor between stages, reducing capacitor size and cost and reducing EMI. This is explained in greater detail in a following section. The UCC2818A current amplifier configuration is shown in Figure 4. L BOOST V OUT − R SENSE Q BOOST + Zf MULT CA PWM COMPARATOR − − + + Figure 4. Current Amplifier Configuration Start Up The UCC2818 version of the device is intended to have VCC connected to a 12-V supply voltage. The UCC2817A has an internal shunt regulator enabling the device to be powered from bootstrap circuitry, as shown in the typical application circuit of Figure 1. The current drawn by the UCC2818A during undervoltage lockout, or start-up current, is typically 150 mA. Once VCC is above the UVLO threshold, the device is enabled and draws 4 mA typically. A resistor connected between the rectified ac line voltage and the VCC pin provides current to the shunt regulator during power up. Once the circuit is operational, the bootstrap winding of the inductor provides the VCC voltage. Sizing of the start-up resistor is determined by the start-up time requirement of the system design. I + C DV C Dt (25) V 0.9 R + RMS I C (26) Where: IC = Charge current C = Total capacitance at the VCC pin ΔV = UVLO threshold Δt = Allowed start-up time Assuming a 1-s allowed start-up time, a 16-V UVLO threshold, and a total VCC capacitance of 100 mF, a resistor value of 51 kΩ is required at a low line input voltage of 85 VRMS. The IC start-up current is sufficiently small as to be ignored in sizing the start-up resistor. Capacitor Ripple Reduction For a power system where the PFC boost converter is followed by a dc-to-dc converter stage, there are benefits to synchronizing the two converters. In addition to the usual advantages, such as noise reduction and stability, proper synchronization can significantly reduce the ripple currents in the boost circuit output capacitor. Figure 5 shows the impact of proper synchronization by showing a PFC boost converter together with the simplified input stage of a forward converter. The capacitor current during a single switching cycle depends on the status of the Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 13 UCC2818A-Q1 SLUSA21 – FEBRUARY 2010 www.ti.com switches Q1 and Q2 and is shown in Figure 6. With a synchronization scheme that maintains conventional trailing-edge modulation on both converters, the capacitor current ripple is highest. The greatest ripple current cancellation is attained when the overlap of Q1 offtime and Q2 ontime is maximized. One method of achieving this is to synchronize the turnon of the boost diode (D1) with the turnon of Q2. This approach implies that the boost converter leading edge is pulse width modulated, while the forward converter is modulated with traditional trailing-edge PWM. The UCC2818A is designed as a leading edge modulator with easy synchronization to the downstream converter to facilitate this advantage. Table 1 compares the ICB(rms) for D1/Q2 synchronization as offered by UCC2818A, versus the ICB(rms) for the other extreme of synchronizing the turnon of Q1 and Q2 for a 200-W power system with a VBST of 385 V. iD1 LIN iQ2 D1 VBST Q2 IL iCB Q1 LOAD CBST UDG-97130-1 Figure 5. Simplified Representation of a Two-Stage PFC Power Supply UDG-97131 Figure 6. Timing Waveforms for Synchronization Scheme Table 1. Effects of Synchronization on Boost Capacitor Current VIN = 85 V 14 VIN = 120 V VIN = 240 V D(Q2) Q1/Q2 D1/Q2 Q1/Q2 D1/Q2 Q1/Q2 D1/Q2 0.35 1.491 A 0.835 A 1.341 A 0.663 A 1.024 A 0.731 A 0.45 1.432 A 0.93 A 1.276 A 0.664 A 0.897 A 0.614 A Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 UCC2818A-Q1 www.ti.com SLUSA21 – FEBRUARY 2010 Table 1 shows that the boost capacitor ripple current can be reduced by about 50% at nominal line and about 30% at high line with the synchronization scheme facilitated by the UCC2818A. Figure 7 shows the suggested technique for synchronizing the UCC2818A to the downstream converter. With this technique, maximum ripple reduction as shown in Figure 6 is achievable. The output capacitance value can be significantly reduced if its choice is dictated by ripple current or the capacitor life can be increased as a result. In cost-sensitive designs where holdup time is not critical, this is a significant advantage. An alternative method of synchronization to achieve the same ripple reduction is possible. In this method, the turnon of Q1 is synchronized to the turnoff of Q2. While this method yields almost identical ripple reduction and maintains trailing edge modulation on both converters, the synchronization is much more difficult to achieve and the circuit can become susceptible to noise as the synchronizing edge itself is being modulated. Gate Drive From Down Stream PWM C1 UCC3817A D2 CT CT D1 RT RT Figure 7. Synchronizing to a Downstream Converter REFERENCE VOLTAGE vs SUPPLY VOLTAGE REFERENCE VOLTAGE vs REFERENCE CURRENT 7.510 VREF − Reference Voltage − V VREF − Reference Voltage − V 7.60 7.55 7.50 7.45 7.505 7.500 7.495 7.490 7.40 9 10 11 12 13 14 0 VCC − Supply Voltage − V Figure 8. 5 10 15 20 25 IVREF − Reference Current − mA Figure 9. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 15 UCC2818A-Q1 SLUSA21 – FEBRUARY 2010 www.ti.com MULTIPLIER OUTPUT CURRENT vs VOLTAGE ERROR AMPLIFIER OUTPUT MULTIPLIER GAIN vs VOLTAGE ERROR AMPLIFIER OUTPUT 1.5 300 1.3 IAC = 150 µ A IAC = 150 µ A 250 Multiplier Gain − K IMOUT - Multiplier Output Current − µA 350 200 IAC = 300 µ A 150 100 1.1 0.9 IAC = 300 µ A IAC = 500 µ A 0.7 50 IAC = 500 µ A 0.5 0 0.0 1.0 2.0 3.0 4.0 1.0 5.0 2.0 VAOUT − Voltage Error Amplifier Output − V Figure 10. VAOUT = 5 V 300 VAOUT = 4 V 200 VAOUT = 3 V 100 VAOUT = 2 V 0 3.0 4.0 VFF − Feed-Forward Voltage − V 5.0 RGATE - Recommended Minimum Gate Resistance − Ω (VFF × IMOUT) − µW 400 2.0 5.0 RECOMMENDED MINIMUM GATE RESISTANCE vs SUPPLY VOLTAGE 500 1.0 4.0 Figure 11. MULTIPLIER CONSTANT POWER PERFORMANCE 0.0 3.0 VAOUT − Voltage Error Amplifier Output − V 17 16 15 14 13 12 11 10 9 8 10 12 14 16 18 20 VCC − Supply Voltage − V Figure 12. 16 Figure 13. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 UCC2818A-Q1 www.ti.com SLUSA21 – FEBRUARY 2010 References and Resources Application Note, Differences Between UCC3817A/18A/19A and UCC3817/18/19, Texas Instruments Literature Number SLUA294 Evaluation Module, UCC3817EVM, 385V, 250W PFC Boost Converter User’s Guide, UCC3817 BiCMOS Power Factor Preregulator Evaluation Board, Texas Instruments Literature Number SLUU077 Application Note, Synchronizing a PFC Controller from a Down Stream Controller Gate Drive, Texas Instruments Literature Number SLUA245 Seminar topic, High Power Factor Switching Preregulator Design Optimization, L.H. Dixon, SEM−700,1990. Seminar topic, High Power Factor Preregulator for Off−line Supplies, L.H. Dixon, SEM−600, 1988. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC2818A-Q1 17 PACKAGE OPTION ADDENDUM www.ti.com 28-Apr-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing UCC2818AQDRQ1 ACTIVE SOIC D Pins Package Eco Plan (2) Qty 16 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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