ESMT F25L32PA

ESMT
F25L32PA
Flash
„
3V Only 32 Mbit Serial Flash Memory with Dual
FEATURES
y
y
Single supply voltage 2.7~3.6V
Standard and Dual SPI
y
Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz / 86MHz / 100MHz
- Fast Read Dual max frequency: 50MHz / 86MHz / 100MHz
(100MHz / 172MHz / 200MHz equivalent Dual SPI)
y
Low power consumption
- Active current: 35 mA
- Standby current: 30 μ A
- Deep Power Down current: 5 μ A
y
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y
Program
- Byte programming time: 7 μ s (typical)
- Page programming time: 1.5 ms (typical)
„
Erase
- Chip erase time 25 sec (typical)
- Block erase time 1 sec (typical)
- Sector erase time 90 ms (typical)
y
Page Programming
- 256 byte per programmable page
y
Lockable 2K bytes OTP security sector
y
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
y
End of program or erase detection
y
Write Protect ( WP )
y
Hold Pin ( HOLD )
y
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
„
y
Speed
Package
Comments
F25L32PA –50PAG
50MHz
8 lead SOIC
200mil
Pb-free
F25L32PA –86PAG
86MHz
8 lead SOIC
200mil
Pb-free
F25L32PA –100PAG
100MHz
8 lead SOIC
200mil
Pb-free
F25L32PA –50PHG
50MHz
16 lead SOIC
300mil
Pb-free
F25L32PA –86PHG
86MHz
16 lead SOIC
300mil
Pb-free
F25L32PA –100PHG
100MHz
16 lead SOIC
300mil
Pb-free
GENERAL DESCRIPTION
The F25L32PA is a 32Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard and Dual
Serial Peripheral Interface (SPI). ESMT’s memory devices
reliably store memory data even after 100,000 programming and
erase cycles.
The memory array can be organized into 16,384 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
The device features sector erase architecture. The memory array
Elite Semiconductor Memory Technology Inc.
is divided into 1024 uniform sectors with 4K byte each; 64
uniform blocks with 64K byte each. Sectors can be erased
individually without affecting the data in other sectors. Blocks can
be erased individually without affecting the data in other blocks.
Whole chip erase capabilities provide the flexibility to revise the
data in the device. The device has Sector, Block or Chip Erase
but no page erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Publication Date: Mar. 2009
Revision: 1.0
1/36
ESMT
„
F25L32PA
PIN CONFIGURATIONS
8-PIN SOIC
CE
1
8
VDD
SO / SIO1
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI / SIO0
16-PIN SOIC
HOLD
1
16
SCK
VDD
2
15
SI / SIO0
NC
3
14
NC
NC
4
13
NC
NC
5
12
NC
NC
6
11
NC
CE
7
10
VSS
8
9
WP
SO / SIO1
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0
2/36
ESMT
„
„
F25L32PA
PIN DESCRIPTION
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing for serial input and output operations
To transfer commands, addresses or data serially into the device. Data is
latched on the rising edge of SCK (for Standard mode). / Bidirectional IO pin to
transfer commands, addresses or data serially into the device on the rising
edge of SCK and read data or status from the device on the falling edge of
SCK(for Dual mode).
To transfer data serially out of the device. Data is shifted out on the falling edge
of SCK (for Standard mode). / Bidirectional IO pin to transfer commands,
addresses or data serially into the device on the rising edge of SCK and read
data or status from the device on the falling edge of SCK (for Dual mode).
SI / SIO0
Serial Data Input /
Serial Data Input Output 0
SO / SIO1
Serial Data Output /
Serial Data Input Output 1
CE
Chip Enable
To activate the device when CE is low.
WP
Write Protect
The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status
register.
HOLD
Hold
VDD
Power Supply
VSS
Ground
To temporality stop serial communication with SPI flash memory without
resetting the device.
To provide power.
FUNCTIONAL BLOCK DIAGRAM
Page Address
Latch / Counter
Memory
Array
High Voltage
Generator
Page Buffer
Status
Register
Y-Decoder
Byte Address
Latch / Counter
Command and Conrol Logic
Serial Interface
CE
SCK
SI
(SIO0)
SO
(SIO1)
Elite Semiconductor Memory Technology Inc.
WP
HOLD
Publication Date: Mar. 2009
Revision: 1.0
3/36
ESMT
F25L32PA
SECTOR STRUCTURE
Table 1: F25L32PA Sector Address Table
Block
63
62
61
60
59
58
57
56
55
54
53
52
51
Sector
Sector Size
(Kbytes)
Address range
1023
4KB
3FF000H – 3FFFFFH
:
:
:
1008
4KB
3F0000H – 3F0FFFH
1007
4KB
3EF000H – 3EFFFFH
:
:
:
992
4KB
3E0000H – 3E0FFFH
991
4KB
3DF000H – 3DFFFFH
:
:
:
976
4KB
3D0000H – 3D0FFFH
975
4KB
3CF000H – 3CFFFFH
:
:
:
960
4KB
3C0000H – 3C0FFFH
959
4KB
3BF000H – 3BFFFFH
:
:
:
944
4KB
3B0000H – 3B0FFFH
943
4KB
3AF000H – 3AFFFFH
:
:
:
928
4KB
3A0000H – 3A0FFFH
927
4KB
39F000H – 39FFFFH
:
:
:
912
4KB
390000H – 390FFFH
911
4KB
38F000H – 38FFFFH
:
:
:
896
4KB
380000H – 380FFFH
895
4KB
37F000H – 37FFFFH
:
:
:
880
4KB
370000H – 370FFFH
879
4KB
36F000H – 36FFFFH
:
:
:
864
4KB
360000H – 360FFFH
863
4KB
35F000H – 35FFFFH
:
:
:
848
4KB
350000H – 350FFFH
847
4KB
34F000H – 34FFFFH
:
:
:
830
4KB
340000H – 340FFFH
831
4KB
33F000H – 33FFFFH
:
:
:
816
4KB
330000H – 330FFFH
Elite Semiconductor Memory Technology Inc.
Block Address
A21
A20
A19
A18
A17
A16
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
0
1
1
0
0
1
1
Publication Date: Mar. 2009
Revision: 1.0
4/36
ESMT
F25L32PA
Table 1: F25L32PA Sector Address Table – Continued I
Block
50
49
48
47
46
45
44
43
42
41
40
39
38
Sector
Sector Size
(Kbytes)
Address range
815
4KB
32F000H – 32FFFFH
:
:
:
800
4KB
320000H – 320FFFH
799
4KB
31F000H – 31FFFFH
:
:
:
784
4KB
310000H – 310FFFH
783
4KB
30F000H – 30FFFFH
:
:
:
768
4KB
300000H – 300FFFH
767
4KB
2FF000H – 2FFFFFH
:
:
:
752
4KB
2F0000H – 2F0FFFH
751
4KB
2EF000H – 2EFFFFH
:
:
:
736
4KB
2E0000H – 2E0FFFH
735
4KB
2DF000H – 2DFFFFH
:
:
:
720
4KB
2D0000H – 2D0FFFH
719
4KB
2CF000H – 2CFFFFH
:
:
:
704
4KB
2C0000H – 2C0FFFH
703
4KB
2BF000H – 2BFFFFH
:
:
:
688
4KB
2B0000H – 2B0FFFH
687
4KB
2AF000H – 2AFFFFH
:
:
:
672
4KB
2A0000H – 2A0FFFH
671
4KB
29F000H – 29FFFFH
:
:
:
656
4KB
290000H – 290FFFH
655
4KB
28F000H – 28FFFFH
:
:
:
640
4KB
280000H – 280FFFH
639
4KB
27F000H – 27FFFFH
:
:
:
624
4KB
270000H – 270FFFH
623
4KB
26F000H – 26FFFFH
:
:
:
608
4KB
260000H – 260FFFH
Elite Semiconductor Memory Technology Inc.
Block Address
A21
A20
A19
A18
A17
A16
1
1
0
0
1
0
1
1
0
0
0
1
1
1
0
0
0
0
1
0
1
1
1
1
1
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
0
1
0
0
1
1
1
1
0
0
1
1
0
Publication Date: Mar. 2009
Revision: 1.0
5/36
ESMT
F25L32PA
Table 1: F25L32PA Sector Address Table – Continued II
Block
37
36
35
34
33
32
31
30
29
28
27
26
25
Sector
Sector Size
(Kbytes)
Address range
607
4KB
25F000H – 25FFFFH
:
:
:
592
4KB
250000H – 250FFFH
591
4KB
24F000H – 24FFFFH
:
:
:
576
4KB
240000H – 240FFFH
575
4KB
23F000H – 23FFFFH
:
:
:
560
4KB
230000H – 230FFFH
559
4KB
22F000H – 22FFFFH
:
:
:
544
4KB
220000H – 220FFFH
543
4KB
21F000H – 21FFFFH
:
:
:
528
4KB
210000H – 210FFFH
527
4KB
20F000H – 20FFFFH
:
:
:
512
4KB
200000H – 200FFFH
511
4KB
1FF000H – 1FFFFFH
:
:
:
496
4KB
1F0000H – 1F0FFFH
495
4KB
1EF000H – 1EFFFFH
:
:
:
480
4KB
1E0000H – 1E0FFFH
479
4KB
1DF000H – 1DFFFFH
:
:
:
464
4KB
1D0000H – 1D0FFFH
463
4KB
1CF000H – 1CFFFFH
:
:
:
448
4KB
1C0000H – 1C0FFFH
447
4KB
1BF000H – 1BFFFFH
:
:
:
432
4KB
1B0000H – 1B0FFFH
431
4KB
1AF000H – 1AFFFFH
:
:
:
416
4KB
1A0000H – 1A0FFFH
415
4KB
19F000H – 19FFFFH
:
:
:
400
4KB
190000H – 190FFFH
Elite Semiconductor Memory Technology Inc.
Block Address
A21
A20
A19
A18
A17
A16
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
0
1
1
0
0
1
Publication Date: Mar. 2009
Revision: 1.0
6/36
ESMT
F25L32PA
Table 1: F25L32PA Sector Address Table – Continued III
Block
24
23
22
21
20
19
18
17
16
15
14
13
12
Sector
Sector Size
(Kbytes)
Address range
399
4KB
18F000H – 18FFFFH
:
:
:
384
4KB
180000H – 180FFFH
383
4KB
17F000H – 17FFFFH
:
:
:
368
4KB
170000H – 170FFFH
367
4KB
16F000H – 16FFFFH
:
:
:
352
4KB
160000H – 160FFFH
351
4KB
15F000H – 15FFFFH
:
:
:
336
4KB
150000H – 150FFFH
335
4KB
14F000H – 14FFFFH
:
:
:
320
4KB
140000H – 140FFFH
319
4KB
13F000H – 13FFFFH
:
:
:
304
4KB
130000H – 130FFFH
303
4KB
12F000H – 12FFFFH
:
:
:
288
4KB
120000H – 120FFFH
287
4KB
11F000H – 11FFFFH
:
:
:
272
4KB
110000H – 110FFFH
271
4KB
10F000H – 10FFFFH
:
:
256
4KB
100000H – 100FFFH
255
4KB
0FF000H – 0FFFFFH
:
:
240
4KB
0F0000H – 0F0FFFH
239
4KB
0EF000H – 0EFFFFH
:
:
224
4KB
0E0000H – 0E0FFFH
223
4KB
0DF000H – 0DFFFFH
:
:
208
4KB
0D0000H – 0D0FFFH
207
4KB
0CF000H – 0CFFFFH
:
:
192
4KB
Elite Semiconductor Memory Technology Inc.
:
:
:
:
:
Block Address
A21
A20
A19
A18
A17
A16
0
1
1
0
0
0
0
1
0
1
1
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
0C0000H – 0C0FFFH
Publication Date: Mar. 2009
Revision: 1.0
7/36
ESMT
F25L32PA
Table 1: F25L32PA Sector Address Table – Continued IV
Block
11
10
9
8
7
6
5
4
3
2
1
0
Sector
Sector Size
(Kbytes)
191
4KB
Address range
A20
A19
A18
A17
A16
0
0
1
0
1
1
0
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0BF000H – 0BFFFFH
:
:
176
4KB
0B0000H – 0B0FFFH
175
4KB
0AF000H – 0AFFFFH
:
:
:
:
160
4KB
0A0000H – 0A0FFFH
159
4KB
09F000H – 09FFFFH
:
:
:
144
4KB
090000H – 090FFFH
143
4KB
08F000H – 08FFFFH
:
:
:
128
4KB
080000H – 080FFFH
127
4KB
07F000H – 07FFFFH
:
:
:
112
4KB
070000H – 070FFFH
111
4KB
06F000H – 06FFFFH
:
:
:
96
4KB
060000H – 060FFFH
95
4KB
05F000H – 05FFFFH
:
:
:
80
4KB
050000H – 050FFFH
79
4KB
04F000H – 04FFFFH
:
:
:
64
4KB
040000H – 040FFFH
63
4KB
03F000H – 03FFFFH
:
:
:
48
4KB
030000H – 030FFFH
47
4KB
02F000H – 02FFFFH
:
:
:
32
4KB
020000H – 020FFFH
31
4KB
01F000H – 01FFFFH
:
:
:
16
4KB
010000H – 010FFFH
15
4KB
00F000H – 00FFFFH
:
:
:
0
4KB
000000H – 000FFFH
Elite Semiconductor Memory Technology Inc.
Block Address
A21
Publication Date: Mar. 2009
Revision: 1.0
8/36
ESMT
„
F25L32PA
STATUS REGISTER
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
Table 2: Software Status Register
Bit
Name
Function
Default at
Power-up
Read/Write
0
R
0
R
1
1
1
0
0
R/W
R/W
R/W
N/A
N/A
0
R/W
Status Register
0
BUSY
1
WEL
2
3
4
5
6
BP0
BP1
BP2
RESERVED
RESERVED
7
BPL
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Reserved for future use
Reserved for future use
1 = BP2,BP1,BP0 are read-only bits
0 = BP2,BP1,BP0 are read/writable
Note:
1. Only BP0, BP1, BP2 and BPL are writable.
2. All register bits are volatility
3. All area are protected at power-on (BP2=BP1=BP0=1)
WRITE ENABLE LATCH (WEL)
BUSY
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
The BUSY bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the BUSY bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
•
•
•
•
•
•
•
Power-up
Write Disable (WRDI) instruction completion
Page Program instruction completion
Sector Erase instruction completion
Block Erase instruction completion
Chip Erase instruction completion
Write Status Register instructions
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0
9/36
ESMT
F25L32PA
Table 3: F25L32PA Block Protection Table
TOP
Protection Level
Status Register Bit
Protected Memory Area
BP2
BP1
BP0
Block Range
Address Range
0
0
0
0
None
None
Upper 1/64
0
0
1
Block 63
3F0000H –3FFFFFH
Upper 1/32
0
1
0
Block 62~63
3E0000H –3FFFFFH
Upper 1/16
0
1
1
Block 60~63
3C0000H –3FFFFFH
Upper 1/8
1
0
0
Block 56~63
380000H –3FFFFFH
Upper 1/4
1
0
1
Block 48~63
300000H –3FFFFFH
Upper 1/2
1
1
0
Block 32~63
200000H –3FFFFFH
All Blocks
1
1
1
Block 0~63
000000H –3FFFFFH
Block Protection (BP2, BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
WP pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
BP2, BP1, BP0 bits as long as WP is high or the BlockProtection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0
are set to1.
Elite Semiconductor Memory Technology Inc.
WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Publication Date: Mar. 2009
Revision: 1.0
10/36
ESMT
„
F25L32PA
HOLD OPERATION
HOLD pin is used to pause a serial sequence underway with the
SPI flash memory without resetting the clocking sequence. To
activate the HOLD mode, CE must be in active low state. The
Once the device enters Hold mode, SO will be in high impedance
state while SI and SCK can be VIL or VIH.
HOLD mode begins when the SCK active low state coincides
If CE is driven active high during a Hold condition, it resets the
with the falling edge of the HOLD signal. The HOLD mode ends
internal logic of the device. As long as HOLD signal is low, the
memory remains in the Hold condition. To resume
when the HOLD signal’s rising edge coincides with the SCK
active low state.
If the falling edge of the HOLD signal does not coincide with the
SCK active low state, then the device enters Hold mode when the
SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD signal does not
coincide with the SCK active low state, then the device exits in
Hold mode when the SCK next reaches the active low state. See
Figure 1 for Hold Condition waveform.
communication with the device, HOLD must be driven active
high, and CE must be driven active low. See Figure 23 for Hold
timing.
The HOLD function is only available for Standard and Dual SPI
operation.
S CK
HO L D
A ctive
A ctive
Ho ld
Ho ld
A ctive
Figure 1: HOLD Condition Waveform
„
WRITE PROTECTION
The device provides software Write Protection.
The Write-Protect pin ( WP ) enables or disables the lock-down
function of the status register. The Block-Protection bits (BP2,
BP1, BP0, and BPL) in the status register provide Write
protection to the memory array and the status register. See Table
4 for Block-Protection description.
Write Protect Pin ( WP )
The Write-Protect ( WP ) pin enables the lock-down function of
Table 4: Conditions to Execute Write-Status- Register
(WRSR) Instruction
WP
BPL
Execute WRSR Instruction
L
1
Not Allowed
L
0
Allowed
H
X
Allowed
the BPL bit (bit 7) in the status register. When WP is driven low,
the execution of the Write Status Register (WRSR) instruction is
determined by the value of the BPL bit (see Table 4). When WP
is high, the lock-down function of the BPL bit is disabled.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0
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ESMT
F25L32PA
INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the device. The instruction bus cycles are 8 bits each
for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Write Status Register, Sector
Erase, Block Erase, or Chip Erase instructions, the Write Enable
(WREN) instruction must be executed first. The complete list of
the instructions is provided in Table 5. All instructions are
entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read ID, Read Status
Register, Read Electronic Signature instructions). Any low to high
synchronized off a high to low transition of CE . Inputs will be
accepted on the rising edge of SCK starting with the most
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
significant bit. CE must be driven low before an instruction is
Table 5: Device Operation Instruction
Operation
Read
Fast Read
Fast Read Dual Output12,13
Fast Read Dual I/O12, 14
Sector Erase4 (4K Byte)
Block Erase4, (64K Byte)
Chip Erase
Max.
Freq
1
SIN SOUT
33 MHz 03H Hi-Z
0BH Hi-Z
3BH
BBH
20H Hi-Z
D8H Hi-Z
60H /
Hi-Z
C7H
Page Program (PP)
50MHz
Mode Bit Reset 15
Deep Power Down (DP)
Read Status Register
(RDSR) 6
Enable Write Status
~
7
Register (EWSR)
Write Status Register
(WRSR) 7
Write Enable (WREN) 10
Write Disable (WRDI)/ Exit 100MHz
secured OTP mode
Enter secured OTP mode
(ENSO)
Release from Deep Power
Down (RDP)
Read Electronic Signature
8
(RES)
RES in secured OTP mode
& not lock down
RES in secured OTP mode
& lock down
02H
2
SIN
SOUT
A23-A16 Hi-Z
A23-A16 Hi-Z
A23-A16
A23-A8
A23-A16 Hi-Z
A23-A16 Hi-Z
-
Hi-Z A23-A16
FFH
B9h
Hi-Z
Hi-Z
FFH
-
05H
Hi-Z
X
50H
Hi-Z
-
01H
Hi-Z
Bus Cycle 1~3
3
4
SIN
SOUT SIN SOUT
A15-A8 Hi-Z A7-A0 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z
A15-A8
A7-A0
A7-A0, M7-M0
DOUT0~1
A15-A8 Hi-Z A7-A0 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z
-
-
Hi-Z
A15-A8
Hi-Z
DOUT
(S7-S0)
-
-
-
-
-
-
-
-
-
-
-
5
SIN
X
X
SOUT
DOUT0
X
X
cont.
-
6
SIN SOUT
X DOUT1
X DOUT0
DOUT0~1
-
N
SIN
X
X
SOUT
cont.
cont.
cont.
-
-
-
-
-
-
-
-
-
DIN0
Hi-Z
DIN1
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Hi-Z A7-A0 Hi-Z
Up to
256 Hi-Z
bytes
-
06H
DIN
(S7-S0)
Hi-Z
-
04H
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
B1H
Hi-Z
-
-
-
-
-.
-
-
-
-
-
-
-
ABH
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
ABH
Hi-Z
X
X
X
X
X
X
X
15H
-
-
-
-
ABH
Hi-Z
X
X
X
X
X
X
X
35H
-
-
-
-
ABH
Hi-Z
X
X
X
X
X
X
X
75H
-
-
-
-
Elite Semiconductor Memory Technology Inc.
Hi-Z
-
DIN
Hi-Z
(S15-S8)
-
Publication Date: Mar. 2009
Revision: 1.0
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ESMT
F25L32PA
Table 5: Device Operation Instruction - Continued
Max.
Freq
Operation
Jedec Read ID
9
(JEDEC-ID)
Read ID (RDID)
50MHz
1
2
SIN
SOUT
SIN
SOUT
SIN
9FH
Hi-Z
X
8CH
X
Bus Cycle 1~3
3
4
SOUT SIN SOUT
20H
~
11
90H
Hi-Z
00H
Hi-Z
00H
5
6
N
SIN
SOUT
SIN
SOUT
SIN
SOUT
X
16H
-
-
-
-
-
-
00H
Hi-Z
X
8CH
X
15H
-
-
01H
Hi-Z
X
15H
X
8CH
-
-
Hi-Z
100MHz
Notes:
1.
2.
3.
4.
5.
6.
7.
Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code
X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous
One bus cycle is eight clock periods.
Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH
Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH
To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be
programmed.
The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in
conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR
instruction to make both instructions effective.
8.
9.
The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
The JEDEC-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 16H as
memory capacity.
10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both
instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR
can reset WREN.
11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction.
12. Dual commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in.
13. Dual output data:
IO0 = (D6, D4, D2, D0), (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1), (D7, D5, D3, D1)
DOUT0
DOUT1
14. M7-M0: Mode bits. Dual input address:
IO0 = (A22, A20, A18, A16, A14, A12, A10, A8)
IO1 = (A23, A21, A19, A17, A15, A13, A11, A9)
(A6, A4, A2, A0, M6, M4, M2, M0)
(A7, A5, A3, A1, M7, M5, M3, M1)
Bus Cycle-2
Bus Cycle-3
15. This instruction is recommended when using the Dual Mode bit feature.
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Publication Date: Mar. 2009
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ESMT
F25L32PA
Read (33MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
the data from address location 3FFFFFH had been read, the next
output will be from address location 00000H.
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
(wrap-around) of the address space, i.e. for 32Mbit density, once
The Read instruction is initiated by executing an 8-bit command,
03H, followed by address bits [A23 -A0]. CE must remain active
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.
Figure 2: Read Sequence
Fast Read (50 MHz ~ 100 MHz)
The Fast Read instruction supporting up to 100 MHz is initiated
by executing an 8-bit command, 0BH, followed by address bits
all addresses until terminated by a low to high transition on CE .
The internal address pointer will automatically increment until the
highest memory address is reached. Once the highest memory
address is reached, the address pointer will automatically
increment to the beginning (wrap-around) of the address space,
i.e. for 32Mbit density, once the data from address location
3FFFFFH has been read, the next output will be from address
location 000000H.
[A23 -A0] and a dummy byte. CE must remain active low for the
duration of the Fast Read cycle. See Figure 3 for the Fast Read
sequence.
Following a dummy byte (8 clocks input dummy cycle), the Fast
Read instruction outputs the data starting from the specified
address location. The data output stream is continuous through
CE
MODE3
SCK MODE0
0 1 2 3 4 5 6 7 8
ADD.
0B
SI
MSB
SO
15 16
23 24
ADD.
31 32
ADD.
39 40
47 48
55 56
63 64
71 72
80
X
MSB
HIGH IMPENANCE
N
N+1
N+2
N+3
N+4
DOUT
DOUT
DOUT
DOUT
DOUT
MSB
Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)
Figure 3: Fast Read Sequence
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F25L32PA
Fast Read Dual Output (50 MHz~100 MHz)
The Fast Read Dual Output instruction is initiated by executing
an 8-bit command, 3BH, followed by address bits [A23 -A0] and a
The Fast Read Dual Output (3BH) instruction is similar to the
standard Fast Read (0BH) instruction except the data is output
on bidirectional I/O pins (SIO0 and SIO1). This allows data to be
transferred from the device at twice the rate of standard SPI
devices. This instruction is for quickly downloading code from
Flash to RAM upon power-up or for applications that cache codesegments to RAM for execution.
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 4 for the Fast Read
Dual Output sequence.
CE
MODE3
SCK MODE0
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
43 44
3B
MSB
SIO1
ADD.
MSB
HIGH IMPENANCE
ADD.
ADD.
55 56
51 52
IO0 switches from In put to Ouput
Dummy
SIO0
47 48
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4
D OUT
DOUT
D OU T
D OU T
D OUT
N
N+1
N+2
N+3
N+4
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5
Note: The input data durin g the dummy clocks is “don’t care”.
However , the IO0 pin should be high-impefance piror to th e falling edge of the first data clock.
Figure 4: Fast Read Dual Output Sequence
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F25L32PA
Fast Read Dual I/O (50 MHz~100 MHz)
The Fast Read Dual I/O (BBH) instruction is similar to the Fast
Read Dual Output (3BH) instruction, but with the capability to
input address bits [A23 -A0] two bits per clock.
If [M7 –M0] = “AxH”, the next Fast Read Dual I/O instruction (after
To set mode bits [M7 -M0] after the address bits [A23 -A0] can
further reduce instruction overhead (See Figure 5). The upper
mode bits [M7 –M4] controls the length of next Fast Read Dual I/O
instruction with/without the first byte command code (BBH). The
lower mode bits [M3 –M0] are “don’t care”.
clocks and allows to enter address immediately after CE is
asserted low. If [M7 –M0] are the value other than “AxH”, the next
instruction need the first byte command code, thus returning to
normal operation. A Mode Bit Reset (FFH) also can be used to
reset mode bits [M7 –M0] before issuing normal instructions.
CE is raised and the lowered) doesn’t need the command code
(See Figure 6). This way let the instruction sequence reduce 8
CE
MODE3
SCK MODE0
0 1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
27 28
31 32
35 36
39 40
IO0 switches from Input to Ouput
SIO0
22 20 18 16 14 12 10 8
BB
6
4
2
0
6
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4
4
MSB
HIG H IMPENANCE
SIO1
23 21 19 17 15 13 11 9
A23-16
7
5
A15-8
3
1
A7- 0
7
DOUT
D OU T
DOUT
DOUT
DOUT
N
N+1
N+2
N+3
N+4
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5
5
M7- 0
Note: The mode bits [M3 -M0] are “d on’t care”.
However , the IO pins sh ould be high-impefance piror to the falling edge of the first data clock.
Figure 5: Fast Read Dual I/O Sequence ([M7 -M0] = 0xH or NOT AxH)
CE
MODE3
SCK MODE0
IO0 switches from In put to Ouput
SIO0
SIO1
22 20 18 16 14 12 10 8
23 21 19 17 15 13 11
A23- 16
A15- 8
9
6
7
4
5
2
3
A7-0
0
1
6
7
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4
4
5
DOUT
DOUT
D OU T
D OUT
D OUT
N
N+1
N+2
N+3
N+4
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5
M 7-0
Note: The mode bits [M3 -M0] are “don’t care”.
However , the IO pins sh ould be high-impe fance piror to the fa ll ing edge of the fi rst data clock.
Figure 6: Fast Read Dual I/O Sequence ([M7 -M0] = AxH)
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F25L32PA
Page Program (PP)
The Page Program instruction allows many bytes to be
programmed in the memory. The bytes must be in the erased
state (FFH) when initiating a Program operation. A Page
Program instruction applied to a protected memory area will be
ignored.
latched data are discarded and the last 256 bytes Data are
guaranteed to be programmed correctly within the same page. If
less than 256 bytes Data are sent to device, they are correctly
programmed at the requested addresses without having any
effects on the other bytes of the same page.
Prior to any Write operation, the Write Enable (WREN) instruction
CE must be driven high before the instruction is executed. The
user may poll the BUSY bit in the software status register or wait
TPP for the completion of the internal self-timed Page Program
operation. While the Page Program cycle is in progress, the Read
Status Register instruction may still be accessed for checking the
status of the BUSY bit. It is recommended to wait for a duration of
TBP1 before reading the status register to check the BUSY bit.
The BUSY bit is a 1 during the Page Program cycle and becomes
a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Page Program cycle has
finished, the Write-Enable-Latch (WEL) bit in the Status Register
is cleared to 0. See Figure 10 for the Page Program sequence.
must be executed. CE must remain active low for the duration
of the Page Program instruction. The Page Program instruction is
initiated by executing an 8-bit command, 02H, followed by
address bits [A23-A0]. Following the address, at least one byte
Data is input (the maximum of input data can be up to 256 bytes).
If the 8 least significant address bits [A7-A0] are not all zero, all
transmitted data that goes beyond the end of the current page
are programmed from the start address of the same page (from
the address whose 8 least significant bits [A7-A0] are all zero).
If more than 256 bytes Data are sent to the device, previously
Figure 10: Page Program Sequence
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F25L32PA
Mode Bit Reset
Mode bits [M7 –M0] are issued to further reduce instruction
overhead for Fast Read Dual I/O operation. If [M7 –M0] = “AxH”,
the next Fast Read Dual I/O instruction doesn’t need the
command code.
However, the device doesn’t have a hardware reset pin, so if
[M7 –M0] = “AxH”, the device will not recognize any standard SPI
instruction. After a system reset, it is recommended to issue a
Mode Bit Reset instruction first to release the status of [M7 –M0] =
“AxH” and allow the device to recognize standard SPI instruction.
See Figure 16 for the Mode Bit Reset instruction.
If the system controller is reset during operation, it will send a
standard instruction (such as Read ID) to the Flash memory.
Mode bit Reset for Dual I/O
CE
MODE3
SCK MODE0
0
1
SIO0
2
3
4
FF
5
6
7
8
9
10
11
12
13
14
15
FF
SIO 1
Note: To reset mode bits during Dual I/O operation, sixteen clocks are needed to shift in command code “FFFFH”.
Figure 16: Mode Bit Reset Instruction
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F25L32PA
64K Byte Block Erase
The 64K-byte Block Erase instruction clears all bits in the
selected block to FFH. A Block Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write Enable (WREN) instruction must be
-A0]. Address bits [AMS -A16] (AMS = Most Significant address) are
used to determine the block address (BAX), remaining address
bits can be VIL or VIH. CE must be driven high before the
instruction is executed. The user may poll the BUSY bit in the
Software Status Register or wait TBE for the completion of the
internal self-timed Block Erase cycle. See Figure 17 for the Block
Erase sequence.
executed. CE must remain active low for the duration of the any
command sequence. The Block Erase instruction is initiated by
executing an 8-bit command, D8H, followed by address bits [A23
Figure 17: 64K-byte Block Erase Sequence
4K Byte Sector Erase
[AMS -A12] (AMS = Most Significant address) are used to determine
the sector address (SAX), remaining address bits can be VIL or
The Sector Erase instruction clears all bits in the selected sector
to FFH. A Sector Erase instruction applied to a protected memory
area will be ignored. Prior to any Write operation, the Write
VIH. CE must be driven high before the instruction is executed.
The user may poll the BUSY bit in the Software Status Register
or wait TSE for the completion of the internal self-timed Sector
Erase cycle. See Figure 18 for the Sector Erase sequence.
Enable (WREN) instruction must be executed. CE must remain
active low for the duration of the any command sequence. The
Sector Erase instruction is initiated by executing an 8-bit
command, 20H, followed by address bits [A23 -A0]. Address bits
CE
MODE3
15 16
0 1 2 3 4 5 6 7 8
31
23 24
SCK MODE0
20
SI
MSB
SO
ADD.
ADD.
ADD.
MSB
HIGH IMPENANCE
Figure 18: 4K-byte Sector Erase Sequence
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Chip Erase
The Chip Erase instruction clears all bits in the device to FFH. A
Chip Erase instruction will be ignored if any of the memory area is
protected. Prior to any Write operation, the Write Enable (WREN)
Erase instruction is initiated by executing an 8-bit command, 60H
or C7H. CE must be driven high before the instruction is
executed. The user may poll the BUSY bit in the Software Status
Register or wait TCE for the completion of the internal self-timed
Chip Erase cycle. See Figure 19 for the Chip Erase sequence.
instruction must be executed. CE must remain active low for
the duration of the Chip-Erase instruction sequence. The Chip
CE
MODE3
0 1 2 3 4 5 6 7
SCK MODE0
60 or C7
SI
MSB
HIGH IMPENANCE
SO
Figure 19: Chip Erase Sequence
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation. When a Write
operation is in progress, the BUSY bit may be checked before
sending any new commands to assure that the new commands
are properly received by the device.
CE must be driven low before the RDSR instruction is entered
and remain low until the status data is read. The RDSR-1
instruction code is “05H” for Status Register. Read Status
Register is continuous with ongoing clock cycles until it is
terminated by a low to high transition of the CE . See Figure 20
for the RDSR instruction sequence.
CE
MODE3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK MODE0
05
SI
MSB
SO
HIGH IMPEDANCE
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB
Status Register Data Out
Figure 20: Read Status Register (RDSR) Sequence
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Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write-EnableLatch bit in the Software Status Register to 1 allowing Write
operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
CE
0 1 2 3 4 5 6 7
MODE3
SCK MODE0
06
SI
MSB
HIGH IMPENANCE
SO
Figure 21: Write Enable (WREN) Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write-EnableLatch bit to 0 disabling any new Write operations from occurring.
CE must be driven high before the WRDI instruction is
executed.
CE
MODE3
0 1 2 3 4 5 6 7
SCK MODE0
04
SI
MSB
SO
HIGH IMPENANCE
Figure 22: Write Disable (WRDI) Sequence
Enable Write Status Register (EWSR)
The Enable Write Status Register (EWSR) instruction arms the
Write Status Register (WRSR) instruction and opens the status
register for alteration. The Enable Write Status Register
instruction does not have any effect and will be wasted, if it is not
followed immediately by the Write Status Register (WRSR)
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instruction. CE must be driven low before the EWSR instruction
is entered and must be driven high before the EWSR instruction
is executed.
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F25L32PA
Write-Status-Register (WRSR)
The Write Status Register instruction writes new values to the
BP2, BP1, BP0, BPL (Status Register) bits of the status register.
CE must be driven low before the command sequence of the
WRSR instruction is entered and driven high before the WRSR
instruction is executed. CE must be driven high after the eighth
bit of data that is clocked in. If it is not done, the WRSR
instruction will not be issued. See Figure 23 for EWSR or WREN
and WRSR instruction sequences.
Executing the Write Status Register instruction will be ignored
when WP is low and BPL bit is set to “1”. When the WP is
low, the BPL bit can only be set from “0” to “1” to lock down the
status register, but cannot be reset from “1” to “0”.
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, BP1,and BP2 bits in the status
register can all be changed. As long as BPL bit is set to 0 or WP
pin is driven high (VIH) prior to the low-to-high transition of the
CE pin at the end of the WRSR instruction, the bits in the status
register can all be altered by the WRSR instruction. In this case,
a single WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0; BP1 and BP2 bits
at the same time. See Table 4 for a summary description of WP
and BPL functions.
CE
MODE3
SCK MODE0
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Stauts Register
Data In
50 or 06
SI
01
MSB
SO
7 6 5 4 3 2 1 0
MSB
HIGH IMPENANCE
Figure 23: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR)
Enter OTP Mode (ENSO)
The ENSO (B1H) instruction is for entering the additional 2K
bytes secured OTP mode. The additional 2K bytes secured OTP
sector is independent from main array, which may use to store
unique serial number for system identifier. User must unprotect
whole array (BP0=BP1=BP2=0), prior to any Write (Program/
Erase) operation in OTP sector. After entering the secured OTP
mode, only the secured OTP sector can be accessed and user
can follow the standard Read or Write procedure except for Block
Erase and Chip Erase. The secured OTP data cannot be
updated again once it is lock down. In secured OTP mode,
WRSR command will ignore the input data and lock down the
secured OTP sector (OTP_lock bit =1). To exit secured OTP
mode, user must execute WRDI command. RES can be used to
verify the secured OTP status as shown in Table 6.
Figure 24: Enter OTP Mode (ENSO) Sequence
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Deep Power Down (DP)
The Deep Power Down instruction is for minimizing power
consumption (the standby current is reduced from ISB1 to ISB2.).
Once the device is in deep power down status, all instructions will
be ignored except the Release from Deep Power Down
instruction (RDP) and Read Electronic Signature instruction
(RES). The device always power-up in the normal operation with
the standby current (ISB1). See Figure 25 for the Deep Power
Down instruction.
This instruction is initiated by executing an 8-bit command, B9H,
and then CE must be driven high. After CE is driven high, the
device will enter to deep power down within the duration of TDP.
CE
MODE3
0
1
2
3
4
5
6
SCK MODE0
7
T DP
B9
SI
MSB
Standard Current
Deep Power Down Current
(ISB2)
Figure 25: Deep Power Down Instruction
Release from Deep Power Down (RDP) and Read Electronic-Signature (RES)
The Release form Deep Power Down and Read
Electronic-Signature instruction is a multi-purpose instruction.
The instruction can be used to release the device from the deep
power down status. This instruction is initiated by driving CE
low and executing an 8-bit command, ABH, and then drive CE
high. See Figure 26 for RDP instruction. Release from the deep
power down will take the duration of TRES1 before the device will
resume normal operation and other instructions are accepted.
CE must remain high during TRES1.
The instruction also can be used to read the 8-bit ElectronicSignature of the device on the SO pin. It is initiated by driving
Elite Semiconductor Memory Technology Inc.
CE low and executing an 8-bit command, ABH, followed by 3
dummy bytes. The Electronic-Signature byte is then output from
the device. The Electronic-Signature can be read continuously
until CE go high. See Figure 27 for RES sequence. After
driving CE high, it must remain high during for the duration of
TRES2, and then the device will resume normal operation and
other instructions are accepted.
The instruction is executed while an Erase, Program or WRSR
cycle is in progress is ignored and has no effect on the cycle in
progress. In OTP mode, user also can execute RES to confirm
the status of OTP.
Publication Date: Mar. 2009
Revision: 1.0
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ESMT
F25L32PA
CE
MODE3
0
1
2
3
4
5
6
7
T RES1
SCK MODE0
AB
SI
MSB
HIGH IMPEDANCE
SO
Standby Current
Deep Power Down Current
(ISB2)
Figure 26: Release from Deep Power Down (RDP) Instruction
CE
MODE3
SCK MODE0
0
1
2
3
4
5
6
7
8
30
9
31
32
33
34
35
36
37
38
TRES2
SS
3 Dummy Bytes
SS
AB
SI
MSB
SO
HIGH IMPEDANCE
SS
Electronic-Signature Data Out
MSB
Deep Power Down Current
(ISB2)
Standby
Current
Figure 27: Read Electronic -Signature (RES) Sequence
Table 6: Electronic Signature Data
Command
RES
Mode
Electronic Signature Data
Normal
15H
In secured OTP mode &
non lock down (OTP_lock =0)
35H
In secured OTP mode &
lock down (OTP_lock =1)
75H
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Publication Date: Mar. 2009
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ESMT
F25L32PA
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as
F25L32PA and the manufacturer as ESMT. The device
information can be read from executing the 8-bit command, 9FH.
Following the JEDEC Read-ID instruction, the 8-bit
manufacturer’s ID, 8CH, is output from the device. After that, a
16-bit device ID is shifted out on the SO pin. Byte1, 8CH,
identifies the manufacturer as ESMT. Byte2, 20H, identifies the
memory type as SPI Flash. Byte3, 16H, identifies the device as
F25L32PA. The instruction sequence is shown in Figure 28.
The JEDEC Read ID instruction is terminated by a low to high
transition on CE at any time during data output. If no other
command is issued after executing the JEDEC Read-ID
instruction, issue a 00H (NOP) command before going into
Standby Mode ( CE =VIH).
CE
MODE3
SCK MODE0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 1617 1819 2021 22 23 24 25 2627 2829 3031
9F
SI
MSB
SO
HIGH IMPENANCE
20
8C
MSB
16
MSB
MSB
Figure 28: JEDEC Read-ID Sequence
Table 7: JEDEC Read-ID Data
Manufacturer’s ID
(Byte 1)
8CH
Elite Semiconductor Memory Technology Inc.
Device ID
Memory Type
(Byte 2)
Memory Capacity
(Byte 3)
20H
16H
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Revision: 1.0
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ESMT
F25L32PA
Read-ID (RDID)
The Read-ID instruction (RDID) identifies the devices as
F25L32PA and manufacturer as ESMT. This command is
backward compatible to all ESMT SPI devices and should be
used as default device identification when multiple versions of
ESMT SPI devices are used in one design. The device
information can be read from executing an 8-bit command, 90H,
followed by address bits [A23 -A0]. Following the Read-ID
instruction, the manufacturer’s ID is located in address 00000H
and the device ID is located in address 00001H.
Once the device is in Read-ID mode, the manufacturer’s and
device ID output data toggles between address 00000H and
00001H until terminated by a low to high transition on CE .
CE
MODE3
SCK MODE0
15 16
0 1 2 3 4 5 6 7 8
SI
90
00
39 40
47 4 8
55 56
63
1
00
ADD
MSB
MSB
SO
31 32
23 24
HIGH IMPENANCE
8C
15
8C
15
HIGH
IMPENA NCE
MSB
Note: The Manufacture’s an d Device ID o utput stream i s continu ous until terminated by a low to high transition on CE.
1. 00H will output the Manufacture’s ID first a nd 01H will output Device ID first b efore toggling between the two. .
Figure 29: Read ID Sequence
Table 8: Product ID Data
Address
00000H
00001H
Elite Semiconductor Memory Technology Inc.
Byte1
Byte2
8CH
15H
Manufacturer’s ID
Device ID
ESMT F25L32PA
15H
8CH
Device ID
ESMT F25L32PA
Manufacturer’s ID
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ESMT
„
F25L32PA
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings
(Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device
reliability.)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
( Note 1: Output shorted for no more than one second. No more than one output shorted at a time. )
TABLE 9: AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for ≧75MHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for ≦50MHz
See Figures 34 and 35
TABLE 10: OPERATING RANGE
Parameter
Symbol
Operating Supply Voltage
Ambient Operating Temperature
Value
Unit
VDD
2.7 ~ 3.6
V
VDD (FCLK > 50MHz)
3.0 ~ 3.6
V
0 ~ 70
℃
TA
TABLE 11: DC OPERATING CHARACTERISTICS
Symbol
Parameter
Min
Limits
Max
15
18
IDDR1
Read Current @ 33MHz
Standard
Dual
IDDR2
Read Current @ 50MHz
Standard
Dual
20
23
IDDR3
Read Current @ 86MHz
IDDR4
Read Current @ 100MHz
Standard
Dual
Standard
Dual
23
25
25
28
IDDW
Program and Erase Current
ISB1
Standby Current
ISB2
Deep Power Down Current
ILI
ILO
VIL
VIH
VOL
VOH
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Elite Semiconductor Memory Technology Inc.
mA
CE =0.1 VDD/0.9 VDD, SO=open
mA
CE =0.1 VDD/0.9 VDD, SO=open
mA
CE =0.1 VDD/0.9 VDD, SO=open
mA
CE =0.1 VDD/0.9 VDD, SO=open
35
mA
CE =VDD
30
µA
CE =VDD, VIN =VDD or VSS
5
µA
1
1
0.8
µA
µA
V
V
V
V
CE =VDD, VIN =VDD or VSS
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VDD=VDD Max
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
0.7 x VDD
0.2
VDD-0.2
Test Condition
Unit
Publication Date: Mar. 2009
Revision: 1.0
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ESMT
F25L32PA
TABLE 12: LATCH UP CHARACTERISTIC
Symbol
Parameter
1
ILTH
Latch Up
Minimum
Unit
Test Method
100 + IDD
mA
JEDEC Standard 78
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
TPU-READ1
TPU-WRITE
1
Parameter
Minimum
Unit
VDD Min to Read Operation
10
µs
VDD Min to Write Operation
10
µs
Test Condition
Maximum
VOUT = 0V
12 pF
VIN = 0V
6 pF
TABLE 14: CAPACITANCE (TA = 25°C, f=1 MHz, other pins open)
Parameter
Description
COUT1
Output Pin Capacitance
CIN1
Input Capacitance
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 15: AC OPERATING CHARACTERISTICS
Normal 33 MHz
Symbol
Fast 50 MHz
Fast 86 MHz
Fast 100 MHz
Min
Min
Min
Parameter
Unit
Min
Max
TSCKH
Serial Clock High Time
13
9
7
5
ns
TSCKL
Serial Clock Low Time
13
9
7
5
ns
CE Active Setup Time
5
5
5
5
ns
TCEH1
CE Active Hold Time
5
5
5
5
ns
TCHS1
CE Not Active Setup Time
5
5
5
5
ns
TCHH
CE Not Active Hold Time
5
5
5
5
ns
TCPH
CE High Time
100
100
100
100
ns
TCHZ
CE High to High-Z Output
TCLZ
SCK Low to Low-Z Output
0
0
0
0
ns
TDS
Data In Setup Time
3
3
3
3
ns
TDH
Data In Hold Time
3
3
3
3
ns
THLS
HOLD Low Setup Time
5
5
5
5
ns
THHS
HOLD High Setup Time
5
5
5
5
ns
THLH
HOLD Low Hold Time
5
5
5
5
ns
THHH
HOLD High Hold Time
5
5
5
5
ns
THZ
HOLD Low to High-Z Output
1
Elite Semiconductor Memory Technology Inc.
9
9
86
Max
Serial Clock Frequency
TCES
50
Max
FCLK
1
33
Max
9
9
100
9
9
9
9
MHz
ns
ns
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ESMT
F25L32PA
TABLE 15: AC OPERATING CHARACTERISTICS - Continued
Normal 33MHz
Symbol
Fast 50 MHz
Fast 86 MHz
Fast 100 MHz
Min
Min
Min
Parameter
Unit
Min
Max
9
Max
Max
9
9
Max
9
ns
TLZ
HOLD High to Low-Z Output
TOH
Output Hold from SCK Change
TV
Output Valid from SCK
12
8
8
8
ns
TDP
CE High to Deep Power Down Mode
3
3
3
3
us
TRES1
CE High to Standby Mode ( for DP)
3
3
3
3
us
TRES2
CE High to Standby Mode (for RES)
1.8
1.8
1.8
1.8
us
0
0
0
0
ns
Note 1: Relative to SCK.
TABLE 16: ERASE AND PROGRAMMING PERFORMANCE
Limit
Parameter
Symbol
Typ
2
Max3
Unit
Sector Erase Time
TSE
90
300
ms
Block Erase Time
TBE
1
2
s
Chip Erase Time
TCE
25
50
s
Byte Programming Time
TBP
7
30
us
Page Programming Time
TPP
1.5
5
ms
Chip Programming Time
50
100
s
Erase/Program Cycles1
100,000
-
Cycles
20
-
Years
Data Retention
Notes:
1.
2.
3.
Not 100% Tested, Excludes external system level over head.
Typical values measured at 25°C, 3V.
Maximum values measured at 85°C, 2.7V.
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ESMT
F25L32PA
Figure 30: Serial Input Timing Diagram
Figure 31: Serial Output Timing Diagram
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ESMT
F25L32PA
CE
SCK
SO
SI
HOLD
Figure 32: HOLD Timing Diagram
VCC
VCC (max)
Program, Erase and Write command is ignored
CE must track VCC
VCC (min)
TVSL
Reset
State
Read command
is allowed
Device is fully
accessible
VWI
TPUW
Time
Figure 33: Power-Up Timing Diagram
Table 17: Power-Up Timing and VWI Threshold
Parameter
Symbol
Min.
VCC(min) to CE low
TVSL
200
Time Delay before Write instruction
TPUW
Write Inhibit Threshold Voltage
VWI
1
Max.
Unit
us
10
ms
2
V
Note: These parameters are characterized only.
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ESMT
F25L32PA
Input timing reference level
Output timing reference level
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AC
Measurement
Level
0.5VCC
Note : Input pulse rise and fall time are <5ns
Figure 34: AC Input/Output Reference Waveforms
Figure 35: A Test Load Example
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ESMT
F25L32PA
PACKING DIMENSIONS
8-LEAD SOIC 200 mil ( official name – 209 mil )
5
1
4
E1
8
E
θ
b
e
A
A2
D
L
A1
L1
SEATING PLANE
Dimension in mm
Dimension in inch
DETAIL "X"
Dimension in mm
Symbol
Dimension in inch
Symbol
Min
Norm
Max
Min
Norm
Max
Min
Norm
Max
Min
Norm
Max
A
---
---
2.16
---
---
0.085
E
7.70
7.90
8.10
0.303
0.311
0.319
A1
0.05
0.15
0.25
0.002
0.006
0.010
E1
5.18
5.28
5.38
0.204
0.208
0.212
A2
1.70
1.80
1.91
0.067
0.071
0.075
L
0.50
0.65
0.80
0.020
0.026
0.032
b
0.36
0.41
0.51
0.014
0.016
0.020
e
c
0.19
0.20
0.25
0.007
0.008
0.010
L1
1.27
1.37
1.47
0.050
0.054
0.058
D
5.13
5.23
5.33
0.202
0.206
0.210
θ
0°
---
8°
0°
---
8°
1.27 BSC
0.050 BSC
Controlling dimension : millimenter
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ESMT
F25L32PA
PACKING
DIMENSIONS
16-LEAD
SOIC ( 300 mil )
9
GAUGE PLANE
0
0.25
E
E1
A
16
L
DETAIL "X"
1
8
e
b
A2
A
C
D
Dimension in mm
"X"
A1
SEATING PLANE
Dimension in inch
Dimension in mm
Symbol
Dimension in inch
Symbol
Min
Norm
Max
Min
Norm
Max
Min
A
---
---
2.65
---
---
0.104
E
10.30 BSC
0.406 BSC
A1
0.1
---
0.3
0.004
---
0.012
E1
7.50 BSC
0.295 BSC
A2
2.05
---
---
0.081
---
---
L
b
0.31
---
0.51
0.012
---
0.020
e
c
0.20
---
0.33
0.008
---
0.013
θ
D
10.10
10.30
10.50
0.400
0.406
0.413
0.40
Norm
---
Max
1.27
Min
0.016
1.27 BSC
0°
---
Norm
---
Max
0.050
0.050 BSC
8°
0°
---
8°
Controlling dimension : millimenter
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0
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ESMT
F25L32PA
Revision History
Revision
Date
0.1
2008.11.21
0.2
2009.01.09
1.0
2009.03.16
Elite Semiconductor Memory Technology Inc.
Description
Original
1. Modify the specification of TCE
2. Modify headline
1. Add Dual SPI instructions
2. Modify the memory type of JEDEC Read-ID data from
40H to 20H
3. Delete the rating of Temperature Under Bias
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ESMT
F25L32PA
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or
by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of failure.
To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.
ESMT's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
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Publication Date: Mar. 2009
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