ESMT M24L816512SA

ESMT
M24L816512SA
PSRAM
8-Mbit (512K x 16)
Pseudo Static RAM
Features
‧Advanced low-power architecture
• High speed: 55 ns, 70 ns
• Wide voltage range: 2.7V to 3.6V
• Typical active current: 2 mA @ f = 1 MHz
• Typical active current: 11 mA @ f = fMAX
• Low standby power
• Automatic power-down when deselected
Byte Low Enable are disabled ( BHE , BLE HIGH), or during
a write operation ( CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip
Enable( CE LOW) and Write Enable ( WE ) input LOW. If
Byte Low Enable ( BLE ) is LOW, then data from I/O pins (I/O0
through I/O7) is written into the location specified on the
Functional Description
The M24L816512SA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 512K words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
address pins(A0 through A18). If Byte High Enable ( BHE ) is
LOW, then data from I/O pins (I/O8 through I/O15) is written
into the location specified on the address pins (A0 through
A18).
Reading from the device is accomplished by taking Chip
Enable ( CE LOW) and Output Enable ( OE ) LOW while
forcing the Write Enable ( WE ) HIGH. If Byte Low Enable
deselected ( CE HIGH or both BHE and BLE are HIGH).
The input/output pins (I/O0through I/O15) are placed in a
( BLE ) is LOW, then data from the memory location specified
by the address pins will appear on I/O0 to I/O7. If Byte High
high-impedance state when : deselected ( CE
Enable( BHE ) is LOW, then data from memory will appear on
I/O8 toI/O15. Refer to the truth table for a complete description
of read and write modes.
HIGH),
outputs are disabled ( OE HIGH), both Byte High Enable
and
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
1/14
ESMT
M24L816512SA
Pin Configuration[2, 3, 4]
48-ball VFBGA
Top View
44-Pin TSOPII(Note*)
Top View
(Default)
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
V CC
V SS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(TypeA)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BL E
I/O 1 5
I/O 1 4
I/O 1 3
I/O 1 2
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
V SS
V CC
VCC
V SS
I/ O1 1
I/ O1 0
I/ O9
I/ O8
A1 8
A8
A9
A1 0
A11
A1 7
I/O4
I/O5
I/O6
I/O7
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O 15
I/O 14
I/O 13
I/O 12
V SS
V CC
I/O 11
I/O 10
I/O 9
I/O 8
A8
A9
A1 0
A11
A1 2
A1 3
Note* :
The default pin arrangement of TSOPII package of the device is as ”Default” figure.
User also can control pin 18~28 to turn into pin arrangement of “Type A” with software.
(The difference in pin arrangement between ”Default” and “Type A” is pin 18~28)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
2/14
ESMT
M24L816512SA
Product Portfolio Product
Power Dissipation
VCC Range (V)
Product
M24L816512SA
Speed(ns)
Min.
Typ.
Max.
2.7
3.0
3.6
55
70
Operating ICC(mA)
f = 1MHz
Standby, ISB2(µA)
f = fMAX
Typ.[5]
Max.
Typ.[5]
2
5
11
Max.
22
17
Typ. [5]
55
Max.
100
110(for Vcc > 3.3V)
Notes:
2.DNU pins are to be left floating or tied to VSS.
3.Ball G2, H6 are the address expansion pins for the 16-Mbit and 32-Mbit densities respectively.
4.NC “no connect”—not connected internally to the die.
5.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ)
and TA = 25°C.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
3/14
ESMT
M24L816512SA
Maximum Ratings
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................–55°C to +125°C
Supply Voltage to Ground Potential ................−0.4V to 4.6V
DC Voltage Applied to Outputs
in High-Z State[6, 7, 8] .......................................−0.4V to 3.7V
DC Input Voltage[6, 7, 8] ....................................−0.4V to 3.7V
Output Current into Outputs (LOW) ............................20 mA
Operating Range
Ambient
Temperature (TA)
−25°C to +85°C
−40°C to +85°C
Range
Extended
Industrial
VCC
2.7V to 3.6V
2.7V to 3.6V
DC Electrical Characteristics (Over the Operating Range) [5, 6, 7, 8]
-55
Parameter
Description
Test Conditions
Min.
VCC
VOH
VOL
VIH
VIL
IIX
IOZ
Supply Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
ICC
VCC Operating
Supply Current
ISB1
Automatic CE
Power-Down
Current
—CMOS Inputs
ISB2
Automatic CE
Power-Down
Current
—CMOS Inputs
2.7
VCC0.4
IOH = −0.1 mA
Typ
.[5]
3.0
IOL = 0.1 mA
-70
Max.
Min.
3.6
2.7
VCC0.4
Typ.
[5]
3.0
Unit
Max.
3.6
V
0.4
0.4
CIN
COUT
V
f=0
0.8*
VCC
-0.4
VCC+
0.4V
0.4
0.8*
VCC
-0.4
VCC+0
.4V
0.4
GND ≤ VIN < VCC
-1
+1
-1
+1
µA
GND ≤ VOUT ≤ VCC, Output Disabled
-1
+1
-1
+1
µA
f = fMAX = 1/tRC
VCC = 3.6V
IOUT = 0mA
CMOS level
f = 1 MHz
CE ≥ VCC − 0.2V, VIN ≥ VCC − 0.2V, VIN
≤ 0.2V, f = fMAX (Address and Data
Only), f = 0
( OE , WE , BHE and
11
22
11
17
2
5
2
5
100
400
100
400
V
V
mA
µA
BLE )
CE ≥ VCC−0.2V,
VIN ≥ VCC − 0.2V or
VIN ≤ 0.2V,
f=0
VCC = 3.3V
55
VCC = 3.6V
100
55
110
100
110
Capacitance[9]
Parameter
V
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz
VCC = VCC(typ)
Max.
Unit
8
8
pF
pF
Thermal Resistance[9]
Parameter
ΘJA
Description
Thermal Resistance(Junction to Ambient)
ΘJC
Thermal Resistance (Junction to Case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/ JESD51.
BGA
55
Unit
°C/W
17
°C/W
Notes:
6.VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns.
7.VIL(MIN) = –0.5V for pulse durations less than 20 ns.
8.Overshoot and undershoot specifications are characterized and are not 100% tested.
9.Tested initially and after design or process changes that may affect these parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
4/14
µA
ESMT
M24L816512SA
AC Test Loads and Waveforms
Parameters
R1
R2
RTH
VTH
3.0V VCC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics Over the Operating Range[10, 11, 12, 13, 14]
Parameter
Description
-55
Min.
-70
Max.
Min.
Max.
Unit
Read Cycle
tRC
tAA
tOHA
tACE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
55
70
ns
ns
ns
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to LOW Z[11, 12]
tHZOE
OE HIGH to High Z[11, 12]
tLZCE
CE LOW to Low Z[11, 12]
tHZCE
CE HIGH to High Z[11, 12]
25
25
ns
tDBE
BLE / BHE LOW to Data Valid
55
70
ns
tLZBE
BLE / BHE LOW to Low Z[11, 12]
tHZBE
BLE / BHE HIGH to High Z[11, 12]
Address Skew
tSK[14]
55[14]
70
55
5
70
5
5
ns
5
25
5
25
ns
5
5
ns
ns
5
10
25
ns
0
10
ns
Notes:
10. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V CC(typ)/2, input pulse levels of 0V
to V CC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance
11. tHZOE, tHZCE, tHZBE, and tHZWEtransitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. The internal write time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals
must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up
and hold timing should be referenced to the edge of the signal that terminates write.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK
is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be
stable within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
5/14
ESMT
M24L816512SA
Switching Characteristics (Over the Operating Range) (continued)[10, 11, 12, 13, 14]
Parameter
Write Cycle[13]
tWC
tSCE
tAW
tHA
tSA
Description
Write Cycle Time
-55
Min.
-70
Max.
Min.
Max.
Unit
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
55
45
45
0
0
70
55
55
0
0
ns
ns
ns
ns
ns
tPWE
WE Pulse Width
40
55
ns
tBW
BLE / BHE LOW to Write End
50
55
ns
tSD
Data Set-up to Write End
42
42
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
WE LOW to High-Z[11, 12]
tLZWE
WE HIGH to Low-Z[11, 12]
25
5
25
5
ns
ns
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[14, 15, 16]
Read Cycle 2 ( OE Controlled)[14, 15]
Notes:
15. WE is HIGH for Read Cycle.
16. Device is continuously selected. OE , CE = VIL
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
6/14
ESMT
M24L816512SA
Switching Waveforms (continued)
Write Cycle 1 ( WE Controlled) [12, 13, 17, 18, 19]
Write Cycle 2 ( CE Controlled) [12, 13, 17, 18, 19]
Notes:
17.Data I/O is high impedance if OE ≥ VIH.
18.If Chip Enable goes INACTIVE simultaneously with WE = HIGH, the output remains in a high-impedance state.
19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
7/14
ESMT
M24L816512SA
Switching Waveforms (continued)
Write Cycle 3 ( WE Controlled, OE LOW)[18, 19]
Write Cycle 4 ( BHE / BLE Controlled, OE LOW)[18, 19]
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
8/14
ESMT
M24L816512SA
Avoid Timing
ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal
shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during
15μs shown as in Avoidable timing 1 or toggle CE to high (≧tRC) one time at least shown as in Avoidable Timing 2.
Abnormal Timing
≧15μ s
CE
WE
＜ tRC
Address
Avoidable Timing 1
≧15μ s
CE
WE
≧ tRC
Address
Avoidable Timing 2
≧15μ s
CE
≧ tRC
WE
＜ tRC
Address
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
9/14
ESMT
M24L816512SA
Truth Table[20]
CE
H
X
WE
X
X
OE
X
X
BHE
X
H
L
H
L
L
L
L
H
L
H
L
L
H
L
L
H
L
H
H
L
L
L
H
H
H
L
H
H
L
L
L
L
Inputs/Outputs
High Z
High Z
Mode
Deselect/Power-Down
Deselect/Power-Down
Power
Standby (ISB)
Standby (ISB)
Data Out (I/O0–I/O15)
Read (Upper Byte and Lower Byte)
Active (ICC)
Read (Lower Byte only)
Active (ICC)
Read (Upper Byte only)
Active (ICC)
High Z
Output Disabled
Active (ICC)
L
High Z
Output Disabled
Active (ICC)
L
H
High Z
Output Disabled
Active (ICC)
X
L
L
Data In (I/O0–I/O15)
Write (Upper Byte and Lower Byte)
Active (ICC)
L
X
H
L
Write (Lower Byte Only)
Active (ICC)
L
X
L
H
Write (Upper Byte Only)
Active (ICC)
BLE
X
H
Data Out (I/O0–I/O7);
(I/O8–I/O15) in High Z
Data Out (I/O8–I/O15);
(I/O0–I/O7) in High Z
Data In (I/O0–I/O7);
(I/O8–I/O15) in High Z
Data Out (I/O8–I/O15);
(I/O0–I/O7) in High Z
Ordering Information
Speed (ns)
55
70
55
70
55
70
55
70
Ordering Code
M24L816512SA-55BEG
M24L816512SA -70BEG
M24L816512SA-55TEG
M24L816512SA-70TEG
M24L816512SA-55BIG
M24L816512SA-70BIG
M24L816512SA-55TIG
M24L816512SA-70TIG
Package Type
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free)
44-pin TSOPII (Pb-Free)
44-pin TSOPII (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free)
44-pin TSOPII (Pb-Free)
44-pin TSOPII (Pb-Free)
Operating Range
Extended
Extended
Extended
Extended
Industrial
Industrial
Industrial
Industrial
Note:
20.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
10/14
ESMT
M24L816512SA
Package Diagrams
48-Ball (6 mm x 8mm x 1.2 mm) FBGA
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
11/14
ESMT
44-LEAD
M24L816512SA
TSOP(II)
Symbol
PSRAM(400mil)
Dimension in mm
Min
Norm
A
Dimension in inch
Max
Min
Norm
1.20
A1
0.05
A2
0.95
B
0.30
B1
0.30
C
Max
0.047
0.15
0.002
1.05
0.037
0.45
0.012
0.40
0.012
0.12
0.21
0.005
0.008
C1
0.10
0.16
0.004
0.006
D
18.28
18.54
0.720
ZD
1.00
0.35
18.41
0.805
REF
0.006
0.039
0.042
0.018
0.014
0.725
0.016
0.730
0.0317 REF
E
11.56
11.76
11.96
0.455
0.463
0.471
E1
10.03
10.16
10.29
0.395
0.400
0.4
L
0.40
0.59
0.69
0.016
0.023
0.027
L1
0.80 REF
e
0.80 BSC
θ
0°
0.031
REF
0.0315 BSC
8°
Elite Semiconductor Memory Technology Inc.
0°
8°
Publication Date : Jun. 2009
Revision : 1.5
12/14
ESMT
M24L816512SA
Revision History
Revision
Date
1.0
1.1
2008.02.27
2008.03.24
1.2
2008.06.23
1.3
2008.07.04
1.4
2009.02.20
1.5
2009.06.22
Elite Semiconductor Memory Technology Inc.
Description
Original
Add I-grade for TSOPII package
1. Move Revision History to the last
2. Modify voltage range from 2.7V~3.3V to 2.7V~3.6V
Add Industrial grade for BGA package
1.Correct Logic Block Diagram
2.Correct the ball name of H1 in BGA configuration
Correct the ball name of D3 in BGA configuration
Publication Date : Jun. 2009
Revision : 1.5
13/14
ESMT
M24L816512SA
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by
any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples for
the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual
property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should
be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
14/14