www.ti.com Typical Size 6,6 mm X 9,8 mm TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 SLVS400C − AUGUST 2001 − REVISED APRIL 2005 3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT™) FEATURES D 30-mΩ, 12-A Peak MOSFET Switches for High D D D D D D Efficiency at 6-A Continuous Output Source and Sink 0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V Fixed Output Voltage Devices With 1.0% Initial Accuracy Internally Compensated for Easy Use and Minimal Component Count Fast Transient Response Wide PWM Frequency − Fixed 350 kHz, 550 kHz or Adjustable 280 kHz to 700 kHz Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Total Cost APPLICATIONS D Low-Voltage, High-Density Systems With DESCRIPTION The SWIFT™ family of dc/dc regulators, the TPS54611, TPS54612, TPS54613, TPS54614, TPS54615 and TPS54616 low-input voltage high-output current synchronous-buck PWM converters integrate all required active components. Included on the substrate are true, high-performance, voltage error amplifiers that provide high performance under transient conditions; an under-voltage-lockout circuit to prevent start-up until the input voltage reaches 3 V; an internally and externally set slow-start circuit to limit in-rush currents; and a power good output useful for processor/logic reset, fault signaling, and supply sequencing. The TPS54611−6 devices are available in a thermally enhanced 28-pin TSSOP (PWP) PowerPAD™ package, which eliminates bulky heatsinks. TI provides evaluation modules and the SWIFT™ designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles. Power Distributed at 5 V or 3.3 V D Point of Load Regulation for High D D Performance DSPs, FPGAs, ASICs and Microprocessors Broadband, Networking and Optical Communications Infrastructure Portable Computing/Notebook PCs EFFICIENCY AT 350 kHz 100 SIMPLIFIED SCHEMATIC VIN PH TPS54614 BOOT PGND VSENSE VBIAS AGND 95 Output 90 85 Efficiency − % Input 80 75 70 65 60 55 50 0 1 2 3 4 5 6 Load Current − A Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and SWIFT are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001−2005, Texas Instruments Incorporated TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 www.ti.com SLVS400C − AUGUST 2001 − REVISED APRIL 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PWP PACKAGE (TOP VIEW) AGND VSENSE NC PWRGD BOOT PH PH PH PH PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 THERMAL 22 PAD 21 20 19 18 17 16 15 RT FSEL SS/ENA VBIAS VIN VIN VIN VIN VIN PGND PGND PGND PGND PGND AVAILABLE OPTIONS OUTPUT VOLTAGE TA −40°C 40 C to 85 85°C C PACKAGED DEVICES PLASTIC HTSSOP (PWP)(1)(2) 0.9 V TPS54611PWP 1.2 V TPS54612PWP 1.5 V TPS54613PWP TA −40°C 40 C to 85 85°C C OUTPUT VOLTAGE PACKAGED DEVICES PLASTIC HTSSOP (PWP)(1)(2) 1.8 V TPS54614PWP 2.5 V TPS54615PWP 3.3 V TPS54616PWP (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54616PWPR). See the application section of this data sheet for PowerPAD drawing and layout information. Terminal Functions TERMINAL NAME DESCRIPTION NO. AGND 1 Analog ground. Return for slow-start capacitor, VBIAS capacitor, RT resistor FSEL. Make PowerPAD connection to AGND. BOOT 5 Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-set FET driver. NC 3 No connection PGND 15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. PH 6−14 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. PWRGD 4 Power good open drain output. High-Z when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or internal shutdown signal active. RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. SS/ENA 26 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time. FSEL 27 Frequency select input. Provides logic input to select between two internally set switching frequencies. VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low-ESR 0.1-µF to 1-µF ceramic capacitor. 20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high quality, low-ESR 1-µF to 10-µF ceramic capacitor. VIN VSENSE 2 2 Error amplifier inverting input. Connect directly to output voltage sense point. TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 www.ti.com SLVS400C − AUGUST 2001 − REVISED APRIL 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) Input voltage range, range VI Output voltage range, range VO Source current, current IO VIN, SS/ENA, FSEL −0.3 V to 7 V RT −0.3 V to 6 V VSENSE −0.3 V to 4 V BOOT −0.3 V to 17 V VBIAS, PWRGD −0.3 V to 7 V PH −0.6 V to 10 V PH Internally Limited VBIAS 6 mA PH Sink current, current IS Voltage differential 12 A SS/ENA, PWRGD 10 mA AGND to PGND ±0.3 V Continuous power dissipation See Power Dissipation Rating Table Operating virtual junction temperature range, TJ −40°C to 125°C Storage temperature, Tstg −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) 300°C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS(1)(2) PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT TA = 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 28 Pin PWP with solder 18.2 °C/W 5.49 W(3) 3.02 W 2.20 W 28 Pin PWP without solder 40.5 °C/W 2.48 W 1.36 W 0.99 W (1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002. (2) Test board conditions: 1. 3” x 3”, 4 layers, thickness: 0.062” 2. 1.5 oz. copper traces located on the top of the PCB 3. 1.5 oz. copper ground plane on the bottom of the PCB 4. 0.5 oz. copper ground planes on the 2 internal layers 5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet) (3) Maximum power dissipation may be limited by over current protection. ADDITIONAL 6A SWIFT™ DEVICES DEVICE OUTPUT VOLTAGE TPS54610 0.9 V to 3.3 V TPS54672 DDR memory adjustable TPS54680 Sequencing adjustable TPS54673 Prebias adjustable RELATED DC/DC PRODUCTS D TPS40000—Low-input, voltage-mode synchronous buck controller D TPS759xx—7.5-A low dropout regulator D PT6440 series—6 A plugin modules 3 TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 www.ti.com SLVS400C − AUGUST 2001 − REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE, VIN Input voltage range, VIN I(Q) 3.0 Quiescent current 6.0 fs = 350 kHz, FSEL ≤ 0.8 V, RT open, phase pin open 6.2 9.6 fs = 550 kHz, FSEL ≤ 2.5 V, RT open, phase pin open 8.4 12.8 1 1.4 2.95 3.0 Shutdown, SS/ENA = 0 V V mA UNDER VOLTAGE LOCK OUT Start threshold voltage, UVLO V Stop threshold voltage, UVLO 2.70 2.80 V Hysteresis voltage, UVLO 0.14 0.16 V 2.5 µs Rising and falling edge deglitch, UVLO(1) BIAS VOLTAGE Output voltage, VBIAS Output current, I(VBIAS) = 0 2.70 2.80 VBIAS(2) 2.90 V 100 µA OUTPUT VOLTAGE TPS54611 TPS54612 TPS54613 VO O t t voltage Output lta TPS54614 TPS54615 TPS54616 TJ = 25°C, VIN = 5 V 0.9 3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, −40° ≤ TJ ≤ 125°C −2.0% TJ = 25°C, VIN = 5 V V 2.0% 1.2 3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, −40° ≤ TJ ≤ 125°C −2.0% TJ = 25°C, VIN = 5 V V 2.0% 1.5 3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, −40° ≤ TJ ≤ 125°C −2.0% TJ = 25°C, VIN = 5 V V 2.0% 1.8 3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, −40° ≤ TJ ≤ 125°C −3.0% TJ = 25°C, VIN = 5 V V 3.0% 2.5 3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, −40° ≤ TJ ≤ 125°C −3.0% TJ = 25°C, VIN = 5 V V 3.0% 3.3 4 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, −40° ≤ TJ ≤ 125°C −3.0% V 3.0% REGULATION Line regulation(1) (3) Load IL = 3 A, 350 ≤ fs ≤ 550 kHz, TJ = 85°C regulation(1) (3) IL = 0 A to 6 A, 350 ≤ fs ≤ 550 kHz, TJ = 85°C 0.088 %/V 0.0917 %/A OSCILLATOR Internally set—free set free running frequency Externally E t ll set—free t f running i frequency range High level threshold, FSEL FSEL ≤ 0.8 V, RT open 280 350 420 FSEL ≥ 2.5 V, RT open 440 550 660 RT = 180 kΩ (1% resistor to AGND)(1) 252 280 308 RT = 100 kΩ (1% resistor to AGND) 460 500 540 663 700 762 RT = 68 kΩ (1% resistor to AGND)(1) 2.5 0.8 Ramp amplitude (peak-to-peak)(1) Minimum controllable on Maximum duty cycle(1) (1)Specified by design resistive loads only (3)Tested using circuit in Figure 10. (2)Static 4 time(1) V 0.75 V 1 V 200 90% kHz V Low level threshold, FSEL Ramp valley(1) kHz ns TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 www.ti.com SLVS400C − AUGUST 2001 − REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS (CONTINUED) TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER Error amplifier open loop voltage gain(1) Error amplifier unity gain bandwidth(1) 3 Error amplifier common mode input voltage range Powered by internal LDO(1) 26 dB 5 MHz 0 VBIAS V 70 85 ns 1.20 1.40 V PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin (excluding deadtime) 10-mV overdrive(1) SLOW-START/ENABLE Enable threshold voltage, SS/ENA 0.82 Enable hysteresis voltage, SS/ENA(1) Falling edge deglitch, 0.03 SS/ENA(1) Internal slow-start slow start time(1) V 2.5 µs TPS54611 2.6 3.3 4.1 TPS54612 3.5 4.5 5.4 TPS54613 4.4 5.6 6.7 TPS54614 2.6 3.3 4.1 TPS54615 3.6 4.7 5.6 4.7 6.1 7.6 3 5 8 µA 1.5 2.3 4.0 mA TPS54616 Charge current, SS/ENA SS/ENA = 0V Discharge current, SS/ENA SS/ENA = 0.2 V, VI = 2.7 V ms POWER GOOD Power good threshold voltage VSENSE falling 90 %VO Power good hysteresis voltage Power good falling edge deglitch See Note 1 3 %VO See Note 1 35 µs Output saturation voltage, PWRGD I(sink) = 2.5 mA Leakage current, PWRGD VI = 5.5 V 0.18 0.3 V 1 µA CURRENT LIMIT Current limit VI = 3 V(1) 7.2 10 VI = 6 V(1) 10 12 A Current limit leading edge blanking time (see Note 1) 100 ns Current limit total response time (see Note 1) 200 ns THERMAL SHUTDOWN Thermal shutdown trip point(1) 135 Thermal shutdown hysteresis(1) 150 165 10 _C OUTPUT POWER MOSFETS rDS(on) (1) (2) Power MOSFET switches IO = 3 A, VI = 6 V(2) 26 47 IO = 3 A, VI = 3 V(2) 36 65 mΩ Specified by design Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design. 5 TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 www.ti.com SLVS400C − AUGUST 2001 − REVISED APRIL 2005 INTERNAL BLOCK DIAGRAM AGND VBIAS VIN Enable 5 µA Comparator SS/ENA 1.8 V Hysteresis: 0.03 V Falling Edge Deglitch VIN UVLO Comparator VIN 2.94 V Hysteresis: 0.16 V VIN ILIM Comparator Thermal Shutdown 145°C 2.5 µs REG VBIAS SHUTDOWN Falling and Rising Edge Deglitch 100 ns BOOT Sensefet 30 mΩ 2.5 µs SS_DIS SHUTDOWN Internal/External Slow-Start (Internal Slow-Start Time = 3.3 ms to 6.6 ms) VI VI Feed-Forward Compensation PH + − S 40 kΩ Error Amplifier PWM Comparator LOUT CO Adaptive Dead-Time and Control Logic R Q 2 kΩ 25 ns Adaptive Deadtime VIN 30 mΩ OSC PGND Power good Comparator Reference/ DAC Falling Edge Deglitch VSENSE 0.90 Vref TPS5461x Hysteresis: 0.03 Vref VSENSE 6 VIN Leading Edge Blanking RT FSEL SHUTDOWN 35 µs PWRGD VO TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 www.ti.com SLVS400C − AUGUST 2001 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS 100 Drain-Source On-State Resistance − Ω Drain-Source On-State Resistance − Ω 120 VI = 3.3 V 100 IO = 3 A 80 60 40 20 0 −40 0 25 85 DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE VI = 5 V IO = 3 A 80 60 40 20 0 −40 125 0 25 Figure 1 450 250 −40 125 600 RT = 100 k 500 400 RT = 180 k 300 0.891 0.889 0.887 0 0 Gain 20 −140 −160 0 −180 −20 −200 10 k 100 k 1 M 10 M 10 100 1k f − Frequency − Hz Figure 7 125 3 4 5 VI − Input Voltage − V 3.65 3.50 3.35 3.20 3.05 2.90 2.75 −40 6 Figure 6 DEVICE POWER LOSSES vs LOAD CURRENT 5 TJ = 125°C FS = 700 kHz 4.5 Phase − Degrees −80 −120 40 85 3.80 −40 −100 60 25 −20 −60 Phase 80 f = 350 kHz 0.8870 INTERNAL SLOW-START TIME vs JUNCTION TEMPERATURE Internal Slow-Start Time − ms 100 0.8890 Figure 5 ERROR AMPLIFIER OPEN LOOP RESPONSE 120 0.8910 TJ − Junction Temperature − °C Figure 4 RL= 10 kΩ, CL = 160 pF, TA = 25°C TA = 85°C 0.8930 0.8850 0.885 −40 125 125 0.8950 Device Power Losses − W 85 85 OUTPUT VOLTAGE REGULATION vs INPUT VOLTAGE 0.893 TJ − Junction Temperature − °C 140 25 Figure 3 VO − Output Voltage Regulation − V 700 25 0 TJ − Junction Temperature − °C RT = 68 k 0 FSEL ≤ 0.8 V 350 0.895 800 200 −40 FSEL ≥ 2.5 V 550 VOLTAGE REFERENCE vs JUNCTION TEMPERATURE Vref − Voltage Reference − V f − Externally Set Oscillator Frequency − kHz 650 Figure 2 EXTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE Gain − dB 85 INTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE TJ − Junction Temperature − °C TJ − Junction Temperature − °C 0 750 f − Internally Set Oscillator Frequency −kHz DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 4 VI = 3.3 V 3.5 3 2.5 2 1.5 VI = 5.0 V 1 0.5 0 0 25 85 TJ − Junction Temperature − °C Figure 8 125 0 1 2 3 4 5 6 7 8 IL − Load Current − A Figure 9 7 TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 www.ti.com SLVS400C − AUGUST 2001 − REVISED APRIL 2005 APPLICATION INFORMATION Figure 10 shows the schematic diagram for a typical TPS54614 application. The TPS54614 (U1) can provide greater than 6 A of output current at a nominal output VI 3V−6V 20 220 µF 10 µF 21 22 23 24 voltage of 1.8 V. For proper operation, the exposed thermal PowerPAD underneath the integrated circuit package needs to be soldered to the printed-circuit board. VIN BOOT VIN PH 28 PwrGood 26 25 4 Enable 0.1 µF 3 2 CSS 1 6 NC 7 PH 8 PH 9 PH 10 PH 11 PH 12 PH 13 PH 14 PH 15 PGND PGND 16 VSENSE PGND VIN VIN VIN 10 kΩ 27 5 FSEL RT SS/ENA VBIAS PWRGD PGND AGND PGND 0.047 µF 7.2 µH VO 1.8 V 680 µF 17 18 19 PwrPad Figure 10. Application Circuit COMPONENT SELECTION OPERATING FREQUENCY The values for the components used in this design example were selected using the SWIFT designer software tool. SWIFT designer provides a complete design environment for developing dc-dc converters using the TPS54614, or other devices in the SWIFT product family. Additional design information is available at www.ti.com. In the application circuit, 350 kHz operation is selected by leaving FSEL open. Different operating frequencies can be selected by connecting a resistor between RT pin and AGND. Choose the value of R using Equation 1 for the desired operating frequency: INPUT FILTER The input to the circuit is a nominal 3.3 VDC or 5 VDC. The input filter is a 220-µF POSCAP capacitor, with a maximum allowable ripple current of 3 A. A 10-µF ceramic capacitor for the TPS54614 is required, and must be located as close as possible to the device. FEEDBACK CIRCUIT The output voltage of the converter is fed directly into the VSENSE pin of the TPS54614. The TPS54614 is internally compensated to provide stability of the output under varying line and load conditions. 8 R+ 500 kHz SwitchingFrequency 100 kW (1) Alternately, a preset operating frequency of 550 kHz can be selected by leaving RT open and connecting the FSEL pin to VI. OUTPUT FILTER The output filter is composed of a 5.2-µH inductor and a 470-µF capacitor. The inductor is low dc resistance (16-mΩ) type, Sumida CDRH104R−5R2. The capacitor used is a 4-V POSCAP with a maximum ESR of 40 mΩ. The output filter components work with the internal compensation network to provide a stable closed loop response for the converter. www.ti.com TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 SLVS400C − AUGUST 2001 − REVISED APRIL 2005 PCB LAYOUT Figure 11 shows a generalized PCB layout guide for the TPS54311−16 The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the TPS54311−16 ground pins. The minimum recommended bypass capacitance is 10-µF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the PGND pins. The TPS54311−16 has two internal grounds (analog and power). Inside the TPS54311−16, the analog ground ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. Noise injected between the two grounds can degrade the performance of the TPS54311−16, particularly at higher output currents. Ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For these reasons, separate analog and power ground traces are recommended. There should be an area of ground one the top layer directly under the IC, with an exposed area for connection to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the ground side of the input and output filter capacitors as well. The AGND and PGND pins should be tied to the PCB ground by connecting them to the ground area under the device as shown. The only components that should tie directly to the power ground plane are the input capacitors, the output capacitors, the input voltage decoupling capacitor, and the PGND pins of the TPS54311−16. Use a separate wide trace for the analog ground signal path. This analog ground should be used for the timing resistor RT, slow start capacitor and bias capacitor grounds. Connect this trace directly to AGND (pin 1). The PH pins should be tied together and routed to the output inductor. Since the PH connection is the switching node, inductor should be located very close to the PH pins and the area of the PCB conductor minimized to prevent excessive capacitive coupling. Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. Connect the output filter capacitor(s) as shown between the VOUT trace and PGND. It is important to keep the loop formed by the PH pins, Lout, Cout and PGND as small as practical. Connect the output of the circuit directly to the VSENSE pin. Do not place this trace too close to the PH trace. Do to the size of the IC package and the device pinout, they will have to be routed somewhat close, but maintain as much separation as possible while still keeping the layout compact. Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If a slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating frequency, connect them to this trace as well. 9 TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 www.ti.com SLVS400C − AUGUST 2001 − REVISED APRIL 2005 ANALOG GROUND TRACE FREQUENCY SET RESISTOR AGND RT FSEL VSENSE NC SLOW START CAPACITOR SS/ENA BIAS CAPACITOR PWRGD BOOT CAPACITOR BOOT PH VOUT PH VBIAS VIN EXPOSED POWERPAD AREA VIN PH VIN PH VIN PH VIN PH PGND OUTPUT INDUCTOR OUTPUT FILTER CAPACITOR VIN PGND PGND PGND PGND INPUT BYPASS CAPACITOR INPUT BULK FILTER TOPSIDE GROUND AREA VIA to Ground Plane Figure 11. TPS54611 − 16 PCB Layout 10 TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 www.ti.com SLVS400C − AUGUST 2001 − REVISED APRIL 2005 LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and 8 PL Ø 0.0130 4 PL Ø 0.0180 Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance any area available should be used when 3 A or greater operation is desired. Connection from the exposes area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Eight vias should be in the PowerPAD area with four additional vias located under the device package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance thermal performance should be included in areas not under the device package. Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside Powerpad Area 4 x 0.018 Diameter Under Device as Shown. Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground Area Is Extended. 0.06 0.0150 0.0339 0.0650 0.0500 0.3820 0.3478 0.0500 0.0500 0.2090 0.0256 0.0650 0.0339 0.1700 Minimum Recommended Top Side Analog Ground Area 0.1340 Minimum Recommended Exposed Copper Area for Powerpad. 5mm Stencils May Require 10 Percent Larger Area 0.0630 0.0400 Figure 12. Recommended Land Pattern for 28-Pin PWP PowerPAD 11 TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 www.ti.com SLVS400C − AUGUST 2001 − REVISED APRIL 2005 PERFORMANCE GRAPHS EFFICIENCY vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 50 80 VI = 3.3V 70 60 40 1.01 Gain − dB VO − Output Voltage − V Efficiency − % VI = 5 V VI = 5 V 1 VI = 3.3V 1 2 3 4 5 6 7 8 9 0 1 2 3 Gain 45 4 5 7 6 8 9 −20 10 10 100 IL − Load Current − A Figure 13 14 7 70 300 12 6 250 10 200 8 150 6 100 4 50 2 1 0 0 40 60 80 100 120 140 160 180 200 0 VO − Output Voltage − mV 350 VI − Input Voltage − V 80 I O − Output Current − A 8 VO − Output Voltage − mV 5 4 3 2 60 50 40 30 20 10 0 6 4 2 8 10 12 14 16 18 20 Figure 16 Figure 17 125 TJ = 125°C FS = 700 kHz 115 105 VI = 5 V 95 85 75 VI = 3.3 V 55 45 Safe Operating Area 35 25 0 1 2 3 0 20 40 60 80 100 120 140 160 180 200 Figure 18 AMBIENT TEMPERATURE vs LOAD CURRENT 65 0 t − Time − µs t − Time − µs T A − Ambient Temperature − ° C 0 100 k OUTPUT RIPPLE VOLTAGE START-UP WAVEFORMS 16 20 10 k Figure 15 400 0 1k f − Frequency − Hz Figure 14 t − Time − µs 4 5 6 IL − Load Current − A Figure 19 12 90 20 −10 IL − Load Current − A TRANSIENT RESPONSE 30 0 0.97 10 135 Phase 10 0.99 0.98 0 180 60 1.02 90 50 LOOP RESPONSE 1.03 Phase − Degrees 100 7 8 TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 www.ti.com SLVS400C − AUGUST 2001 − REVISED APRIL 2005 DETAILED DESCRIPTION t Under Voltage Lock Out (UVLO) The TPS5461x incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs rising and falling edge deglitch circuit, reduces the likelihood of shutting the device down due to noise on VIN. Slow-Start/Enable (SS/ENA) The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA exceeds the enable threshold, device start up begins. The reference voltage fed to the error amplifier is linearly ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of triggering the enable due to noise. Refer to the following table for start up times for each device DEVICE OUTPUT VOLTAGE SLOW-START TPS54611 0.9 V 3.3 ms TPS54612 1.2 V 4.5 ms TPS54613 1.5 V 5.6 ms TPS54614 1.8 V 3.3 ms TPS54615 2.5 V 4.7 ms TPS54616 3.3 V 6.1 ms The second function of the SS/ENA pin provides an external means for extending the slow-start time with a ceramic capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the SS/ENA pin and start-up of the output. The delay is proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The start-up delay is approximately: t +C d (SS) 1.2 V 5 mA (2) Second, as the output becomes active, a brief ramp up at the internal slow-start rate may be observed before the externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor. The slow-start time set by the capacitor is approximately: (SS) +C (SS) 0.7 V 5 mA (3) The actual slow-start time is likely to be less than the above approximation due to the brief ramp up at the internal rate. VBIAS Regulator The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V, and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. Voltage Reference The voltage reference system produces a precise, temperature-stable voltage from a bandgap circuit. A scaling amplifier and DAC are then used to produce the reference voltages for each of the fixed output devices. Oscillator and PWM Ramp The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the FSEL pin as a static digital input. If a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 kHz to 700 kHz by connecting a resistor from the RT pin to AGND and floating the FSEL pin. The switching frequency is approximated by the following equation, where R is the resistance from RT to AGND: Switching Frequency + 100 kW R 500 [kHz] (4) The following table summarizes the frequency selection configurations: SWITCHING FREQUENCY SYNC PIN RT PIN 350 kHz, internally set Float or AGND Float 550 kHz, internally set ≥2.5 V Float Externally set 280 kHz to 700 kHz Float R = 180 k to 68 k Error Amplifier The high performance, wide bandwidth, voltage error amplifier is gain-limited to provide internal compensation of the control loop. The user is given limited flexibility in choosing output L and C filter components. Inductance values of 4.7 µH to 10 µH are typical and available from several vendors. The resulting designs exhibit good noise 13 TPS54611, TPS54612 TPS54613, TPS54614 TPS54615, TPS54616 www.ti.com SLVS400C − AUGUST 2001 − REVISED APRIL 2005 and ripple characteristics, but with exceptional transient response. Transient recovery times are typically in the range of 10 µs to 20 µs. PWM Control Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch, and portions of the adaptive dead-time and control logic block. During steady-state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately set and reset the PWM latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset, and the high-side FET remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting VSENSE to approximately the same voltage as Vref. If the error amplifier output is low, the PWM latch is continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states. The TPS54611 − TPS54616 devices are capable of sinking current continuously until the output reaches the regulation set-point. If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the error amplifier output. The high-side FET turns off and the low-side FET turns on to decrease the energy in the output inductor and consequently decrease the output current. This process is repeated each cycle in which the current limit comparator is tripped. Dead-Time Control and MOSFET Drivers Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the switching transitions by actively controlling the 14 turnon times of the MOSFET drivers. The high-side driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. The high-side and low-side drivers are designed with 300 mA source and sink capability to quickly drive the power MOSFETs gates. The low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and internal 2.5-Ω bootstrap switch connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and reduces external component count. Overcurrent Protection Cycle-by-cycle current limiting is achieved by sensing the current flow through the high-side MOSFET and a differential amplifier with preset overcurrent threshold. The high-side MOSFET is turned off within 200 ns of reaching the current limit threshold. A 100 ns leading edge blanking circuit prevents false tripping of current limit. Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter. Load protection during current sink operation is provided by thermal shutdown. Thermal Shutdown The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction temperature exceeds 150°C. The device is released from shutdown when the junction temperature decreases to 10°C below the thermal shutdown trip point, and starts up under control of the slow-start circuit.Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent fault condition, the device cycles continuously: starting up by control of the slow-start circuit, heating up due to the fault, and then shutting down upon reaching the thermal shutdown trip point. Power Good (PWRGD) The power good circuit monitors for under voltage conditions on VSENSE. If the voltage on VSENSE falls 10% below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is less than the UVLO threshold, or SS/ENA is low, or thermal shutdown is asserted. When VIN = UVLO threshold, SS/ENA = enable threshold, and VSENSE > 90% of Vref, the open drain output of the PWRGD pin is high. A hysteresis voltage equal to 3% of Vref and a 35-µs falling edge deglitch circuit prevent tripping of the power good comparator due to high-frequency noise. PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS54611PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54611 TPS54611PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54611 TPS54611PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54611 TPS54611PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54611 TPS54612PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54612 TPS54612PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54612 TPS54612PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54612 TPS54612PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54612 TPS54613PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54613 TPS54613PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54613 TPS54613PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54613 TPS54613PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54613 TPS54614PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54614 TPS54614PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54614 TPS54614PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54614 TPS54614PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54614 TPS54615PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54615 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS54615PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54615 TPS54615PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54615 TPS54615PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54615 TPS54616PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54616 TPS54616PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54616 TPS54616PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54616 TPS54616PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54616 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS54611, TPS54612, TPS54613, TPS54614, TPS54615, TPS54616 : • Automotive: TPS54612-Q1, TPS54613-Q1, TPS54614-Q1, TPS54615-Q1, TPS54616-Q1 • Enhanced Product: TPS54611-EP, TPS54612-EP, TPS54613-EP, TPS54614-EP, TPS54615-EP, TPS54616-EP NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54611PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 TPS54612PWPR HTSSOP PWP 28 2000 330.0 TPS54613PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 16.4 6.9 10.2 1.8 12.0 16.0 TPS54614PWPR HTSSOP PWP 28 2000 Q1 330.0 16.4 6.9 10.2 1.8 12.0 16.0 TPS54614PWPR HTSSOP PWP 28 Q1 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 TPS54615PWPR HTSSOP PWP TPS54616PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54611PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0 TPS54612PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0 TPS54613PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0 TPS54614PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0 TPS54614PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0 TPS54615PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0 TPS54616PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated