TI TMS470R1VF334A

TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
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High-Performance Static CMOS Technology
TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
– 24-MHz System Clock (48-MHz Pipeline
Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
– Utilizes Big-Endian Format
Integrated Memory
– 64K-Byte Program Flash
– One Bank With Five Contiguous Sectors
– Internal State Machine for Programming
and Erase
– 4K-Byte Static RAM (SRAM)
Operating Features
– Core Supply Voltage (VCC): 1.70 V - 2.06 V
– I/O Supply Voltage (VCCIO): 3.0 V - 3.6 V
– Low-Power Modes: STANDBY and HALT
– Industrial and Automotive Temperature
Ranges
– Class II Serial Interface (C2SIa)
– Two Selectable Data Rates
– Normal Mode 10.4 Kbps and 4X Mode
41.6 Kbps
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High-End Timer (HET)
– 13 Programmable I/O Channels:
– 12 High-Resolution Pins
– 1 Standard-Resolution Pin
– High-Resolution Share Feature (XOR)
– HET RAM (64-Instruction Capacity)
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10-Bit Multi-Buffered ADC (MibADC)
8-Channel
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 μs Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
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Six External Interrupts
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Flexible Interrupt Handling
5 Dedicated General-Purpose I/O (GIO) Pins,
1 Input-Only GIO Pin, and 34 Additional
Peripheral I/Os
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470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory and
Peripherals
– Analog Watchdog (AWD) Timer
– Real-Time Interrupt (RTI)
– System Integrity and Failure Detection
Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
Six Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
– Two Serial Communication Interfaces (SCIs)
– 224 Selectable Baud Rates
– Asynchronous/Isosynchronous Modes
– Standard CAN Controller (SCC)
– 16-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
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External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
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On-Chip Scan-Base Emulation Logic,
IEEE Standard 1149.1† (JTAG) Test-Access Port
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80-Pin Plastic Low-Profile Quad Flatpack
(PN Suffix)
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Development System Support Tools Available
– Code Composer Studio™ Integrated Development Environment (IDE)
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
– Flash Programming
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines (ARM) Limited.
All trademarks are the property of their respective owners.
† The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture
specification. Boundary scan is not supported on this device.
Copyright © 2006, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication
date. Products conform to specifications per the Texas
Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
POST OFFICE BOX 1443
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1
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
TDI
PLLDIS
CLKOUT
41
CANSRX
48
TDO
CANSTX
49
42
SCI1CLK
51
50
TCK
SCI1TX
52
43
SCI1RX
53
HET[8]
VSS
54
44
VCC
55
45
ADEVT
56
VCCIO
ADIN[6]
57
VSSIO
ADIN[4]
58
46
ADIN[2]
59
47
ADIN[0]
60
TMS470R1VF334 80-PIN PIN PACKAGE (TOP VIEW)
VSS
VSS
71
30
C2SIaRX
HET[0]
72
29
C2SIaTX
VSS
73
28
C2SIaLPN
VCC
74
27
HET[24]
FLTP2
75
26
SCI2TX
VCCP
76
25
SCI2RX
HET[2]
77
24
GIOA[1]/ECLK/INT1
HET[4]
78
23
HET[6]
79
22
GIOA[0]/INT0†
TEST
HET[7]
80
21
TRST
VSSIO
RST
VCC
OSCOUT
OSCIN
SPI1SOMI
SPI1CLK
VSS
SPI1SIMO
SPI1ENA
SPI1SCS
20
31
GIOA[4]/INT4
70
19
TMS2
18
69
GIOA[6]/INT6
GIOA[5]/INT5
SPI2CLK
TMS
33
32
17
68
16
SPI2SIMO
VSSAD
PORRST
34
GIOA[7]/INT7
67
15
SPI2SOMI
VCCAD
HET[12]
35
14
66
HET[14]
SPI2ENA
ADREFLO
13
36
12
65
VCCIO
HET[16]
HET[22]
ADREFHI
10
11
37
9
64
8
HET[20]
ADIN[8]
7
38
6
63
5
HET[18]
ADIN[12]
4
AWD
39
3
40
62
2
61
ADIN[10]
1
ADIN[14]
† GIOA[0]/INT0 (pin 23) is an input-only GIO pin.
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VCC
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
description
The TMS470R1VF334† device is a member of the Texas Instruments TMS470R1x family of general-purpose16/
32-bit reduced instruction set computer (RISC) microcontrollers. The VF334 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high
instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views
memory as a linear collection of bytes numbered upwards from zero. The TMS470R1VF334 utilizes the bigendian format, where the most significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining
low costs. The VF334 RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The VF334 device contains the following:
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ARM7TDMI 16/32-Bit RISC CPU
TMS470R1x system module (SYS) with 470+ enhancements
64K-byte flash
4K-byte SRAM
Zero-pin phase-locked loop (ZPLL) clock module
Analog watchdog (AWD) timer
Real-time interrupt (RTI) module
Two serial peripheral interface (SPI) modules
Two serial communication interface (SCI) modules
Standard CAN controller (SCC)
Class II serial interface (C2SIa)
10-bit multi-buffered analog-to-digital converter (MibADC), 8-input channels
High-end timer (HET) controlling 13 I/Os
External Clock Prescale (ECP)
Up to 39 I/O pins and 1 input-only pin
The functions performed by the 470+ system module (SYS) include: address decoding; memory protection;
memory and peripherals bus supervision; reset and abort exception management; prioritization for all internal
interrupt sources; device clock control; and parallel signature analysis (PSA). This data sheet includes devicespecific information such as memory and peripheral select assignment, interrupt priority, and a device memory
map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module
Reference Guide (literature number SPNU189).
The VF334 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
† Throughout the remainder of this document, the TMS470R1VF334 device name shall be referred to as either their full device name or VF334.
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3
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
description (continued)
The flash memory on the VF334 device is a nonvolatile, electrically erasable and programmable memory
implemented with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to
24 MHz. In pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. For more detailed
information on the flash, see the F05 flash section of this data sheet and the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).
The VF334 device has six communication interfaces: two SPIs, two SCIs, an SCC, and a C2SIa. The SPI
provides a convenient method of serial interaction for high-speed communications between similar shift-register
type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between
the CPU and other peripherals using the standard Non-Return-to-Zero (NRZ) format. The SCC uses a serial,
multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy
and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or
multiplexed wiring. The C2SIa allows the VF334 to transmit and receive messages on a class II network following
an SAE J1850† standard. For more detailed functional information on the SPI, SCI, and SCC peripherals, see
the specific TMS470R1x Peripheral Reference Guides (literature numbers SPNU195, SPNU196, and
SPNU197, respectively). For more detailed functional information on the C2SIa peripheral, see the TMS470R1x
Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and
an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well
suited for applications requiring multiple sensor information and drive actuators with complex and accurate
time pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199). The VF334 HET peripheral contains the XOR-share feature.
This feature allows two adjacent HET high-resolution channels to be XORed together, making it possible to
output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see
the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).
The VF334 device has a 10-bit-resolution sample-and-hold MibADC. The MibADC channels can be converted
individually or can be grouped by software for sequential conversion sequences. There are three separate
groupings, two of which are triggerable by an external event. Each sequence can be converted once when
triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK‡ to the system
(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other VF334 device modules. For
more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL)
Clock Module Reference Guide (literature number SPNU212).
The VF334 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
† SAE Standard J1850 Class B Data Communication Network Interface
‡ ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal
reference.
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
device characteristics
The TMS470R1VF334 device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1
identifies all the characteristics of the TMS470R1VF334 device except the SYSTEM and CPU, which are
generic. The COMMENTS column aids the user in software-programming and references device-specific information.
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
TMS470R1VF334
COMMENTS FOR VF334
MEMORY
For the number of memory selects on this device, see the Memory Selection Assignment table (Table 2).
Flash is pipeline-capable.
INTERNAL
MEMORY
64K-Byte flash
4K-Byte SRAM
The VF334 RAM is implemented in one 4K array selected by two memoryselect signals (see the Memory Selection Assignment table, Table 2).
PERIPHERALS
For the device-specific interrupt priority configurations, see the Interrupt Priority table (Table 5). And for the 1K peripheral address ranges and
their peripheral selects, see the VF334 Peripherals, System Module, and Flash Base Addresses table (Table 4).
CLOCK
ZPLL
GENERAL-PURPOSE
I/Os
5 I/O
1 Input only
ECP
YES
C2SIa
1
SCI
1 (3-pin)
1 (2-pin)
CAN
(HECC and/or SCC)
1 SCC
SPI
(5-pin, 4-pin or 3-pin)
1 (5-pin)
1 (4-pin)
Zero-pin PLL has no external loop filter pins.
Port A has six (6) external pins – GIOA[2]/INT2 and GIOA[3]/INT3 are not
available.
SCI2 has no external clock pin, only transmit/receive pins (SCI2TX and
SCI2RX)
Standard CAN controller
SPI2 has no chip select pin.
The VF334 device has both the logic and registers for a full 32-I/O HET
implemented, even though not all 32 pins are available externally.
HET with
XOR Share
13 I/O
HET RAM
64-Instruction Capacity
MibADC
10-bit, 8-channel
64-word FIFO
CORE VOLTAGE
1.70 - 2.06 V
I/O VOLTAGE
3.0 - 3.6 V
PINS
80
PACKAGE
PN
POST OFFICE BOX 1443
The high-resolution (HR) SHARE feature allows even HR pins to share the
next higher odd HR pin structures. This HR sharing is independent of
whether or not the odd pin is available externally. If an odd pin is available
externally and shared, then the odd pin can only be used as a generalpurpose I/O. For more information on HR SHARE, see the TMS470R1x
High-End Timer (HET) Reference Guide (literature number SPNU199).
8-channel MibADC. Both the logic and registers for a full 16-channel
MibADC are present.
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5
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
functional block diagram
External Pins
FLTP2
OSCIN
FLASH
64K Bytes
(5 Sectors)
RAM
(4K Bytes)
ZPLL
PLLDIS
ADIN[14, 12, 10, 8,
6, 4, 2, 0]
CPU Address/Data Bus
MibADC
with
64-Word
FIFO
TRST
TMS470R1x
CPU
TCK
OSCOUT
ADEVT
ADREFHI
ADREFLO
VCCAD
VSSAD
TDI
TMS
TMS470R1x 470+ SYSTEM MODULE
TMS2
RST
AWD
TEST
PORRST
Expansion Address/Data Bus
TDO
CLKOUT
HET with
XOR Share
(64-Word)
SCC
HET[22, 24, 20, 18,
16, 14, 12, 8, 7, 6,
4, 2, 0]
CANSTX
CANSRX
SCI1CLK
SCI1
SCI1TX
SCI1RX
SCI2
SCI2TX
SCI2RX
C2SIaTX
C2SIa
C2SIaRX
SPI2
SPI1
SPI1SCS
SPI1ENA
SPI1SIMO
SPI1SOMI
SPI1CLK
GIOA[7:4]/
INT[7:4]
GIO
GIOA[0]/
INT[0]†
ECP
SPI2ENA
SPI2SIMO
SPI2SOMI
SPI2CLK
C2SIaLPN
GIOA[1]/INT[1]/
ECLK
† GIOA[0]/INT[0] is an input-only GIO pin.
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Crystal
VCCP
External Pins
• HOUSTON, TEXAS 77251-1443
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
Terminal Functions
TERMINAL
NAME
VF334
TYPE†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
HIGH-END TIMER (HET)
HET[0]
72
HET[2]
77
The VF334 device has both the logic and registers for a full 32-I/O HET
implemented, even though not all 32 pins are available externally
HET[4]
78
HET[6]
79
HET[7]
80
HET[8]
45
HET[12]
15
HET[14]
14
HET[16]
13
HET[18]
39
HET[20]
38
HET[22]
37
HET[24]
27
CANSRX
49
3.3-V I/O
CANSTX
50
3.3-V I/O
C2SIaLPN
28
3.3-V I/O
C2SIaRX
30
3.3-V I/O
C2SIaTX
29
3.3-V I/O
GIOA[0]/INT0
23
3.3-V I
GIOA[1]/INT1/
ECLK
24
GIOA[4]/INT4
20
GIOA[5]/INT5
19
GIOA[6]/INT6
18
GIOA[7]/INT7
17
ADEVT
56
ADIN[0]
60
ADIN[2]
59
ADIN[4]
58
ADIN[6]
57
ADIN[8]
64
ADIN[10]
62
ADIN[12]
63
ADIN[14]
61
ADREFHI
65
3.3-V REF I
MibADC module high-voltage reference input
ADREFLO
66
GND REF I
MibADC module low-voltage reference input
VCCAD
67
3.3-V
PWR
MibADC analog supply voltage
VSSAD
68
GND
MibADC analog ground reference
Timer input capture or output compare. The HET[31:0] applicable pins can be
programmed as general-purpose input/output (GIO) pins.
3.3-V I/O
IPD
HET pins [22, 20, 18, 16, 14, 12, 8, 7, 6, 4, 2, and 0]are high-resolution pins for
VF334.
HET[24] is a standard-resolution pin.
The high-resolution (HR) SHARE feature allows even HR pins to share the next
higher odd HR pin structures. This HR sharing is independent of whether or not
the odd pin is available externally. If an odd pin is available externally and shared,
then the odd pin can only be used as a general-purpose I/O. For more information
on HR SHARE, see the TMS470R1x High-End Timer Reference Guide (literature
number SPNU199).
STANDARD CAN CONTROLLER (SCC)
SCC receive pin or GIO pin
IPU
SCC transmit pin or GIO pin
CLASS II SERIAL INTERFACE (C2SIA)
IPD
C2SIa module loopback enable pin or GIO pin
IPD
C2SIa module transmit data output pin or GIO pin
C2SIa module receive data input pin or GIO pin
GENERAL-PURPOSE I/O (GIO)
3.3-V I/O
General-purpose input/output pins. GIOA[0]/INT[0] is an input-only pin.
GIOA[7:0]/INT[7:0] are interrupt-capable pins.
IPD
GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out function of the
external clock prescale (ECP) module.
GIOA[2]/INT[2] and GIOA[3]/INT[3]] pins are not applicable on the VF334 device.
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
3.3-V I/O
MibADC event input. ADEVT can be programmed as a GIO pin.
MibADC analog input pins
3.3-V I
IPD
The VF334 device has only 8 input channels but all S/W registers are capable.
ADIN[15,13, 11, 9, 7, 5, 3, and 1] pins are not applicable to the VF334 device.
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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7
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
Terminal Functions (Continued)
TERMINAL
NAME
VF334
TYPE†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1CLK
5
SPI1 clock. SPI1CLK can be programmed as a GIO pin.
SPI1ENA
1
SPI1 chip enable. SPI1ENA can be programmed as a GIO pin.
SPI1SCS
2
SPI1SIMO
3
SPI1SOMI
4
3.3-V I/O
IPD
SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin.
SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed as a GIO pin.
SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed as a GIO pin.
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2CLK
33
SPI2ENA
36
SPI2 clock. SPI2CLK can be programmed as a GIO pin.
SPI2SIMO
34
SPI2SOMI
35
OSCIN
8
1.8-V I
Crystal connection pin or external clock input
OSCOUT
7
1.8-V O
External crystal connection pin
PLLDIS
41
3.3-V I
SCI1CLK
51
3.3-V I/O
IPD
SCI1 clock. SCI1CLK can be programmed as a GIO pin.
SCI1RX
53
3.3-V I/O
IPU
SCI1 data receive. SCI1RX can be programmed as a GIO pin.
SCI1TX
52
3.3-V I/O
IPU
SCI1 data transmit. SCI1TX can be programmed as a GIO pin.
SCI2RX
25
3.3-V I/O
IPU
SCI2 data receive. SCI2RX can be programmed as a GIO pin.
SCI2TX
26
3.3-V I/O
IPU
SCI2 data transmit. SCI2TX can be programmed as a GIO pin.
3.3-V I/O
IPD
SPI2 chip enable. SPI2ENA can be programmed as a GIO pin.
SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed as a GIO pin.
SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed as a GIO pin.
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
IPD
Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator becomes
the system clock. If not in bypass mode, TI recommends that this pin be connected
to ground or pulled down to ground by an external resistor.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
SYSTEM MODULE (SYS)
CLKOUT
48
3.3-V I/O
IPD
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of
SYSCLK, ICLK, or MCLK.
PORRST
16
3.3-V I
IPD
Input master chip power-up reset. External VCC monitor circuitry must assert a
power-on reset.
IPU
Bidirectional reset. The internal circuitry can assert a reset, and an external system
reset can assert a device reset.
On this pin, the output buffer is implemented as an open drain (drives low only).
To ensure an external reset is not arbitrarily generated, TI recommends that an
external pullup resistor be connected to this pin.
RST
10
3.3-V I/O
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
8
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
Terminal Functions (Continued)
TERMINAL
NAME
VF334
TYPE†‡
AWD
40
3.3-V I/O
TCK
44
3.3-V I
TDI
42
3.3-V I
TDO
43
3.3-V O
TEST
22
3.3-V I
TMS
69
3.3-V I
TMS2
70
3.3-V I
TRST
21
3.3-V I
FLTP2
75
NC
VCCP
76
3.3-V PWR
INTERNAL
PULLUP/
DESCRIPTION
PULLDOWN§
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
Analog watchdog reset. The AWD pin provides a system reset if the WD KEY is
not written in time by the system, providing an external RC network circuit is
connected. If the user is not using AWD, TI recommends that this pin be connected
to ground or pulled down to ground by an external resistor.
IPD
For more details on the external RC network circuit, see the TMS470R1x System
Module Reference Guide (literature number SPNU189) and the application note
Analog Watchdog Resistor, Capacitor and Discharge Interval Selection
Constraints (literature number SPNA005).
TEST/DEBUG (T/D)
IPD
Test clock. TCK controls the test hardware (JTAG)
Test data in. TDI inputs serial data to the test instruction register, test data register,
IPU
and programmable test address (JTAG).
Test data out. TDO outputs serial data from the test instruction register, test data
IPD
register, identification register, and programmable test address (JTAG).
Test enable. Reserved for internal use only. TI recommends that this pin be
IPD
connected to ground or pulled down to ground by an external resistor.
Serial input for controlling the state of the CPU test access port (TAP) controller
IPU
(JTAG)
Serial input for controlling the second TAP. TI recommends that this pin be
IPU
connected to VCCIO or pulled up to VCCIO by an external resistor.
IPD
Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG) BoundaryScan Logic. TI recommends that this pin be pulled down to ground by an external
resistor.
FLASH
Flash test pad 2. For proper operation, this pin must not be connected [no
connect (NC)].
Flash external pump voltage (3.3 V)
SUPPLY VOLTAGE CORE (1.8 V)
VCC
9
32
55
74
1.8-V
PWR
VCCIO
12
47
3.3-V
PWR
VSS
6
31
54
71
73
VSSIO
11
46
Core logic supply voltage
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
Digital I/O supply voltage
SUPPLY GROUND CORE
GND
Core supply ground reference
SUPPLY GROUND DIGITAL I/O
GND
Digital I/O supply ground reference
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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9
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
VF334 DEVICE-SPECIFIC INFORMATION
memory
Figure 1 shows the memory map of the VF334 device.
0xFFFF_FFFF
Memory (4G Bytes)
SYSTEM
0xFFFF_FFFF
0xFFFF_FD00
System Module Control Registers
(512K Bytes)
Reserved
0xFFF8_0000
0xFFF7_FFFF
0xFFF0_0000
0xFFEF_FFFF
0xFFE8_C000
0xFFE8_BFFF
0xFFE8_8000
0xFFE8_7FFF
0xFFE8_4024
0xFFE8_4023
0xFFE8_4000
0xFFE8_3FFF
HET
Peripheral Control Registers
(512K Bytes)
SPI1
SCI2
Reserved
SCI1
Flash Control Registers
MibADC
Reserved
GIO/ECP
MPU Control Registers
Reserved
SCC
Reserved
SCC RAM
0xFFE0_0000
Reserved
SPI2
RAM
(4K Bytes)
Reserved
C2SIa
Reserved
Program
and
Data Area
FLASH
(64K Bytes)
5 Sectors
FIQ
IRQ
Reserved
Data Abort
Prefetch Abort
0x0000_0020
0x0000_001F
0x0000_0000
Software Interrupt
Undefined Instruction
Exception, Interrupt, and
Reset Vectors
Reset
0xFFF8_0000
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F500
0xFFF7_F400
0xFFF7_F000
0xFFF7_EC00
0xFFF7_E400
0xFFF7_E000
0xFFF7_DC00
0xFFF7_D800
0xFFF7_D400
0xFFF7_CC00
0xFFF7_C800
0xFFF0_0000
0x0000_001F
0x0000_001C
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
0x0000_0004
0x0000_0000
NOTES: A. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
B. The CPU registers are not a part of the memory map.
Figure 1. Memory Map
10
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
memory selects
Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array’s starting (base) address, size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple
of the decoded block size. The decoded block size for the flash is 0x00100000. For more information on how
to control and configure these memory select registers, see the bus structure and memory sections of the
TMS470R1x System Module Reference Guide (literature number SPNU189).
For the memory selection assignments and the memory selected, see Table 2.
Table 2. Memory Selection Assignment
MEMORY
SELECT
MEMORY SELECTED
(ALL INTERNAL)
0 (fine)
FLASH
1 (fine)
FLASH
2 (fine)
RAM
3 (fine)
RAM
4 (fine)
HET RAM
MEMORY
SIZE
64K
4K†
1K
MPU
MEMORY BASE ADDRESS REGISTER
NO
MFBAHR0 and MFBALR0
NO
MFBAHR1 and MFBALR1
YES
MFBAHR2 and MFBALR2
YES
MFBAHR3 and MFBALR3
MFBAHR4 and MFBALR4
STATIC MEM
CTL REGISTER
SMCR1
† The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block size in the
memory-base address register.
RAM
The VF334 device contains 4K bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This VF334 RAM is implemented in one 4K array selected
by two memory-select signals. This VF334 configuration imposes an additional constraint on the memory map
for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the multiples
of the size of the physical RAM (i.e., 4K for the VF334 device). The VF334 RAM is addressed through memory
selects 2 and 3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion
of the SYS module and memory protection, see the memory section of the TMS470R1x System Module
Reference Guide (literature number SPNU189).
F05 flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions. See the flash read and flash program and erase sections below.
flash protection keys
The VF334 devices provide flash protection keys. These four 32-bit protection keys prevent program/erase/
compaction operations from occurring until after the four protection keys have been matched by the CPU loading
the correct user keys into the FMPKEY control register. The protection keys on the VF334 are located in the
last 4 words of the first 8K sector. For more detailed information on the flash protection keys and the FMPKEY
control register, see the Optional Quadruple Protection Keys and Programming the Protection Keys portions
of the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
FLASH read
The VF334 flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000
to 0xFFE0_0000. The flash is addressed through memory selects 0 and 1.
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
Note: The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
flash pipeline mode
When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz (versus a system
clock in normal mode of up to 24 MHz). Flash in pipeline mode is capable of accessing 64-bit words and provides
two 32-bit pipelined words to the CPU. Also in pipeline mode, the flash can be read with no wait states when
memory addresses are contiguous (after the initial 1-or 2-wait-state reads).
Note: After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a "0"). In other words,
the VF334 device powers up and comes out of reset in non-pipeline mode. Furthermore, setting the flash
configuration mode bit (GLBCTRL.4) will override pipeline mode.
flash program and erase
The VF334 device flash has one 64K-byte bank that consists of five sectors. These five sectors are shown in
Table 3.
Table 3. Flash Sectors
SECTOR
NO.
SEGMENT
LOW ADDRESS
HIGH ADDRESS
0
8K Bytes
0x0000_0000
0x0000_1FFF
1
8K Bytes
0x0000_2000
0x0000_3FFF
2
16K Bytes
0x0000_4000
0x0000_7FFF
3
16K Bytes
0x0000_8000
0x0000_BFFF
4
16K Bytes
0x0000_C000
0x0000_FFFF
The minimum size for an erase operation is one sector. The maximum size for a program operation is one
16-bit word.
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
Execution can occur from one bank while programming/erasing any or all sectors of another bank. However,
execution can not occur from any sector within a bank that is being programmed or erased.
NOTE
When the OTP sector is enabled, the rest of the flash memory is disabled. The OTP memory can only
be read or programmed from code executed out of RAM.
For more detailed information on Flash program and erase operations, see the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
HET RAM
The VF334 device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
peripheral selects and base addresses
The VF334 device uses ten of the sixteen peripheral selects to decode the base addresses of the peripherals.
These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used
by the SYS module.
Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 4.
Table 4. VF334 Peripherals, System Module, and Flash Base Addresses
CONNECTING MODULE
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
PERIPHERAL SELECTS
SYSTEM
0XFFFF_FD00
0XFFFF_FFFF
RESERVED
0XFFF8_0000
0XFFFF_FCFF
N/A
HET
0XFFF7_FC00
0XFFF7_FFFF
PS[0]
PS[1]
SPI1
0XFFF7_F800
0XFFF7_FBFF
SCI2
0XFFF7_F500
0XFFF7_F7FF
SCI1
0XFFF7_F400
0XFFF7_F4FF
N/A
PS[2]
ADC
0XFFF7_F000
0XFFF7_F3FF
GIO/ECP
0XFFF7_EC00
0XFFF7_EFFF
PS[3]
PS[4]
RESERVED
0XFFF7_E400
0XFFF7_EBFF
PS[5] - PS[6]
SCC
0XFFF7_E000
0XFFF7_E3FF
PS[7]
SCC RAM
0XFFF7_DC00
0XFFF7_DFFF
PS[8]
RESERVED
0XFFF7_D800
0XFFF7_DBFF
PS[9]
SPI2
0XFFF7_D400
0XFFF7_D7FF
PS[10]
RESERVED
0XFFF7_CC00
0XFFF7_D3FF
PS[11] - PS[12]
C2SIA
0XFFF7_C800
0XFFF7_CBFF
PS[13]
RESERVED
0XFFF7_C000
0XFFF7_C7FF
PS[14] - PS[15]
RESERVED
0XFFF0_0000
0XFFF7_BFFF
N/A
FLASH CONTROL REGISTERS
0XFFE8_8000
0XFFE8_BFFF
N/A
MPU CONTROL REGISTERS
0XFFE8_4000
0XFFE8_4023
N/A
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13
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
interrupt priority
The central interrupt manager (CIM) portion of the SYS module manages the interrupt requests from the device
modules (i.e., SPI1 or SPI2, SCI1 or SCI2, and RTI, etc.).
Although the CIM can accept up to 32 interrupt request signals, the VF334 device only uses 21 of those interrupt
request signals. The request channels are maskable so that individual channels can be selectively disabled.
All interrupt requests can be programmed in the CIM to be of either type:
z
Fast interrupt request (FIQ)
z
Normal interrupt request (IRQ)
The precedences of request channels decrease with ascending channel order in the CIM (0 [highest] and
31 [lowest] priority). For these channel priorities and the associated modules, see Table 5.
Table 5. Interrupt Priority
MODULES
INTERRUPT SOURCES
SPI1 end-transfer/overrun
0
RTI
COMP2 interrupt
1
RTI
COMP1 interrupt
2
RTI
TAP interrupt
3
SPI2
SPI2 end-transfer/overrun
4
GIO
Interrupt A
5
RESERVED
HET
6
Interrupt A
7
RESERVED
SCI1/SCI2
8
SCI1/SCI2 error interrupt
9
SCI1
SCI1 receive interrupt
10
C2SIa
C2SIa interrupt
11
RESERVED
12
RESERVED
SCC
13
Interrupt A
14
MibADC
End event conversion
16
SCI2
SCI2 receive interrupt
17
RESERVED
15
RESERVED
18
RESERVED
SCI1
System
19
SCI1 transmit interrupt
20
SW interrupt (SSI)
21
RESERVED
HET
22
Interrupt B
23
RESERVED
24
SCC
Interrupt B
SCI2
SCI2 transmit interrupt
26
End Group 1 conversion
27
MibADC
25
RESERVED
GIO
MibADC
28
Interrupt B
29
End Group 2 conversion
30
RESERVED
14
INTERRUPT LEVEL/CHANNEL
SPI1
31
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.
The VF334 MibADC module can function in two modes: compatibility mode, where its programmer’s model is
compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in
buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by interrupts
or by the DMA.
MibADC event trigger enhancements
The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.
z
Both group1 and the event group can be configured for event-triggered operation, providing up to two eventtriggered groups.
z
The trigger source and polarity can be selected individually for both group 1 and the event group from the
three options identified in Table 6.
Table 6. MibADC Event Hookup Configuration
SOURCE SELECT BITS FOR G1 OR EVENT
(G1SRC[1:0] or EVSRC[1:0])
SIGNAL PIN NAME
EVENT1
00
ADEVT
EVENT2
01
HET18
EVENT3
10
HET19
EVENT4
11
RESERVED
EVENT #
For group 1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0])
in the AD event source register (ADEVTSRC.[5:4]). For the event group, these event-triggered selections are
configured via the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC.[1:0]).
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).
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15
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
development system support
Texas Instruments provides extensive hardware and software development support tools for the TMS470R1x
family. These support tools include:
z
Code Composer Studio™ Integrated Development Environment (IDE)
–
–
–
z
Optimizing C compiler
–
–
–
–
–
–
–
z
Provides extensive macro capability
Allows high-speed operation
Allows extensive control of the assembly process using assembler directives
Automatically resolves memory references as C and assembly modules are combined
TMS470R1x CPU Simulator
–
–
–
z
Supports high-level language programming
Full implementation of the standard ANSI C language
Powerful optimizer that improves code-execution speed and reduces code size
Extensive run-time support library included
TMS470R1x control registers easily accessible from the C program
Interfaces C functions and assembly functions easily
Establishes comprehensive, easy-to-use tool set for the development of high-performance
microcontroller applications in C/C++
Assembly language tools (assembler and linker)
–
–
–
–
z
Fully integrated suite of software development tools
Includes Compiler/Assembler/Linker, Debugger, and Simulator
Supports Real-Time analysis, data visualization, and open API
Provides capability to simulate CPU operation without emulation hardware
Allows inspection and modifications of memory locations
Allows debugging programs in C or assembly language
XDS emulation communication kits
–
Allow high-speed JTAG communication to the TMS470R1x emulator or target board
For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
16
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
documentation support
Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types
of documentation available include: data sheets with design specifications; complete user’s guides for all
devices and development support tools; and hardware and software applications. Useful reference documentation includes:
z
z
User’s Guides
–
TMS470R1x 32-Bit RISC Microcontroller Family User’s Guide (literature number SPNU134)
–
TMS470R1x C/C++ Compiler User’s Guide (literature number SPNU151)
–
TMS470R1x Code Generation Tools Getting Started Guide (literature number SPNU117)
–
TMS470R1x C Source Debugger User’s Guide (literature number SPNU124)
–
TMS470R1x Assembly Language Tools User’s Guide (literature number SPNU118)
–
TMS470R1x System Module Reference Guide (literature number SPNU189)
–
TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)
–
TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
–
TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
–
TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199)
–
TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
–
TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide
(literature number SPNU206)
–
TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide
(literature number SPNU212)
–
TMS470R1x F05 Flash Reference Guide (literature number SPNU213)
–
TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218)
Application Reports:
–
Analog Watchdog Resistor, Capacitor and Discharge Interval Selection Constraints
(literature number SPNA005)
–
F05/C05 Power Up Reset and Power Sequencing Requirements (literature number SPNA009)
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
device numbering conventions
Figure 2 illustrates the numbering and symbol nomenclature for the TMS470R1x family.
TMS 470 R1 V F 33 4 E PN Q
Prefix: TMS = Standard Prefix for Fully Qualified Devices
Family:
470 = TMS470 RISC-Embedded Microcontroller Family
V = 1.8-V Core Voltage
Program Memory Types:
CPU Type:
Device Type:
Program Memory Size
C
F
L
B
R
=
=
=
=
=
Masked ROM
Flash
ROM-less
System Emulator for Development Tools
RAM
R1 = ARM7TDMI CPU
33 = 33 Devices Contain the Following Modules:
– ZPLL Clock
– 4K-Byte Static RAM
– 1K-Byte HET RAM (64 Instructions)
– Analog Watchdog (AWD)
– Real-Time Interrupt (RTI)
– 10-Bit, 8-Input Multi-buffered Analog-to-Digital
Converter (MibADC)
– Two Serial Peripheral Interface (SPI) Modules
– Two Serial Communications Interface (SCI) Modules
– Class II Serial Interface (C2SIa)
– Standard Controller Area Network (CAN) [SCC]
– High-End Timer (HET)
– External Clock Prescaler (ECP)
6 = 0
– No on-chip program memory
1–5 – 1 to < 128K Bytes
6–B – 128K Bytes to < 1M Bytes
C–F – > 1M Bytes
Operating Free-Air
Temperature Ranges:
A =
T =
–40°C to 85°C
–40°C to 105°C
Q =
–40°C to 125°C
Silicon Version: Blank = Original silicon
A,B... = Subsequent silicon revisions
Package:
PN = 80-Pin Plastic Low-Profile Quad Flatpack (LQFP)
Figure 2. TMS470R1x Family Nomenclature
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
device identification code register
The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash
device, and an assigned device-specific part number (see Table 7). The VF334 device identification code
register value is 0xn83F.
Table 7. TMS470 Device ID Bit Allocation Register
BIT 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BIT 16
6
5
4
3
2
1
BIT 0
Reserved
FFFF_FFF0
BIT 15
LEGEND:
For bits 3–15:
For bits 0–2:
14
13
12
11
10
9
8
7
VERSION
TF
R/F
PART NUMBER
1
1
1
R-K
R-K
R-K
R-K
R-1
R-1
R-1
R = Read only, -K = Value constant after RESET
R = Read only, -1 = Value after RESET
Bits 31:16
Reserved. Reads are undefined and writes have no effect.
Bits 15:12
VERSION. Silicon version (revision) bits
These bits identify the silicon version of the device.
Bit 11
TF. Technology Family (TF) bit
This bit distinguishes the technology family core power supply:
0 = 3.3 V for F10/C10 devices
1 = 1.8 V for F05/C05 devices
Bit 10
R/F. ROM/flash bit
This bit distinguishes between ROM and flash devices:
0 = Flash device
1 = ROM device
Bits 9:3
PART NUMBER. Device-specific part number bits
These bits identify the assigned device-specific part number.
The assigned device-specific part number for the VF334 device is: 0000111.
Bits 2:0
"1" Mandatory High. Bits 2,1, and 0 are tied high by default.
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19
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
device part numbers
Table 8 lists all the available TMS470R1VF334 devices.
Table 8. Device Part Number†
DEVICE PART
NUMBER
PROGRAM MEMORY
PACKAGE TYPE
TEMPERATURE RANGES
FLASH
EEPROM
80-PIN
LQFP
−40°C TO 85°C
TMS470R1VF334EPNA
X
X
X
TMS470R1VF334EPNT
X
X
TMS470R1VF334EPNQ
X
X
ROM
−40°C TO 105°C
−40°C TO 125°C
X
X
† The various part numbers listed in this table differ due to differences in either electrical specifications or functional errata. Electrical differences
will be noted in this datasheet. For functional errata, see the errata document for the specific part number you are using.
20
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS
absolute maximum ratings over operating free-air temperature range, Q version
(unless otherwise noted)†
Supply voltage ranges: VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
Supply voltage ranges: VCCIO , VCCAD , VCCP (flash pump) (see Note 1) . . . . . . . . . . . . . . . . . . −0.5 V to 4.1 V
Input voltage range: All input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.1 V
Input clamp current: IIK (VI < 0 or VI > VCCIO)
All pins except ADIN[0:11], PORRST, TRST, TEST and TCK . . . . . . . . . . . . . . . ±20 mA
IIK (VI < 0 or VI > VCCAD)
ADIN[0:11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Operating free-air temperature ranges, TA: A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 85°C
T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 105°C
Q version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 125°C
Operating junction temperature range, TJ A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 115°C
T version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 130°C
Q version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to their associated grounds.
device recommended operating conditions‡
MIN
NOM
MAX
UNIT
2.06
V
VCC
Digital logic and flash supply voltage (Core)
VCCIO
Digital logic supply voltage (I/O)
3
3.3
3.6
V
VCCAD
ADC supply voltage
3
3.3
3.6
V
VCCP
Flash pump supply voltage
3
3.3
3.6
V
VSS
Digital logic supply ground
VSSAD
ADC supply ground
1.70
0
− 0.1
0.1
− 40
85
T version
− 40
105
Q version
− 40
125
A version
− 40
115
°C
T version
− 40
130
°C
Q version
− 40
150
°C
A version
TA
TJ
Operating free-air temperature
Operating junction temperature
V
V
°C
‡ All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.
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21
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
electrical characteristics over recommended operating free-air temperature range, Q version
(unless otherwise noted)†
PARAMETER
Vhys
TEST CONDITIONS
All inputs‡
except OSCIN
VIL
Low-level input voltage
VIH
High-level input voltage
Vth
Input threshold voltage
AWD only
RDSON
Drain to source on
resistance
AWD only§
VOL
Low-level output voltage¶
VOH
High-level output voltage¶
IIC
Input clamp current (I/O pins)#
II
IOL
Input current (I/O pins)
Low-level output
current
OSCIN only
All inputs except OSCIN
0.8
V
V
VCCIO + 0.3
V
0.65 VCC
VCC + 0.3
V
1.35
1.8
V
45
Ω
0.2 VCCIO
IOL = 50 μA
IOH = 50 μA
V
0.35 VCC
VOL = 0.35V @ IOL = 8mA
IOH = IOH MIN
0.2
0.8 VCCIO
−2
IIL Pulldown
VI = VSS
−1
1
IIH Pulldown
VI = VCCIO
5
40
2
IIL Pullup
VI = VSS
–40
–5
IIH Pullup
VI = VCCIO
−1
1
−1
1
All other pins
No pullup or pulldown
CLKOUT, AWD, TDO
VOL = VOL MAX
8
RST, SPI1CLK,
SPI1SOMI, SPI1SIMO,
SPI2CLK, SPI2SOMI,
SPI2SIMO
VOL = VOL MAX
4
VOL = VOL MAX
2
CLKOUT, TDO
VOH = VOH MIN
−8
SPI1CLK, SPI1SOMI,
SPI1SIMO, SPI2CLK,
SPI2SOMI, SPI2SIMO
VOH = VOH MIN
−4
VOH = VOH MIN
−2
except RST||
V
V
VCCIO − 0.2
VI < VSSIO − 0.3 or VI > VCCIO + 0.3
All other output pins
UNIT
− 0.3
IOL = IOL MAX
output pins||
High-level output
current
MAX
− 0.3
2
OSCIN only
All other
IOH
MIN
0.15
Input hysteresis
mA
μA
mA
mA
† Source currents (out of the device) are negative while sink currents (into the device) are positive.
‡ This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 29.
§ These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
¶ VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
# Parameter does not apply to input-only or output-only pins.
||
The 2 mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a low level
and the other is outputting a high level, the resulting value will always be low.
,For flash banks/pumps in sleep mode.
†I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
22
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
electrical characteristics over recommended operating free-air temperature range, Q version
(unless otherwise noted) (continued)†
PARAMETER
ICC
ICCIO
ICCAD
ICCP
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC Digital supply current (operating mode)
SYSCLK = 48 MHz,
ICLK = 24 MHz, VCC = 2.06 V
70
mA
VCC Digital supply current (standby mode)I
OSCIN = 6 MHz, VCC = 2.06 V
3.0
mA
VCC Digital supply current (halt mode)I
VCC = 2.06 V
1.0
mA
VCCIO Digital supply current (operating mode)
No DC load, VCCIO = 3.6 Vo
10
mA
VCCIO Digital supply current (standby mode)
No DC load, VCCIO = 3.6 Vo
300
μA
o
300
μA
VCCIO Digital supply current (halt mode)
No DC load, VCCIO = 3.6 V
VCCAD supply current (operating mode)
All frequencies, VCCAD = 3.6 V
15
mA
VCCAD supply current (standby mode)
All frequencies, VCCAD = 3.6 V
20
μA
VCCAD supply current (halt mode)
VCCAD = 3.6 V
20
μA
VCCP = 3.6 V read operation
50
mA
VCCP = 3.6 V program and erase
70
mA
20
μA
20
μA
VCCP pump supply current
VCCP = 3.6 V standby mode
operationI
VCCP = 3.6 V halt mode operationI
CI
Input capacitance
2
pF
CO
Output capacitance
3
pF
† Source currents (out of the device) are negative while sink currents (into the device) are positive.
‡ This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 29.
§ These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
¶ VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
# Parameter does not apply to input-only or output-only pins.
||
The 2 mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a low level
and the other is outputting a high level, the resulting value will always be low.
,For flash banks/pumps in sleep mode.
†I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
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23
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
VLOAD
Output
Under
Test
CL
IOH
Where: IOL
= IOL MAX for the respective pin (see Note A)
= IOH MIN for the respective pin (see Note A)
IOH
VLOAD = 1.5 V
= 150-pF typical load-circuit capacitance (see Note B)
CL
NOTES: A. For these values, see the electrical characteristics over recommended operating free-air temperature range table.
B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 3. Test Load Circuit
24
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten
the symbols, some of the pin names and other related terminology have been abbreviated as follows:
CM
CO
ER
ICLK
M
OSC, OSCI
OSCO
P
R
R0
R1
Compaction, CMPCT
CLKOUT
Erase
Interface clock
Master mode
OSCIN
OSCOUT
Program, PROG
Ready
Read margin 0, RDMRGN0
Read margin 1, RDMRGN1
RD
RST
RX
S
SCC
SIMO
SOMI
SPC
SYS
TX
Read
Reset, RST
SCInRX
Slave mode
SCInCLK
SPInSIMO
SPInSOMI
SPInCLK
System clock
SCInTX
r
su
t
v
w
rise time
setup time
transition time
valid time
pulse duration (width)
Lowercase subscripts and their meanings are:
a
c
d
f
h
access time
cycle time (period)
delay time
fall time
hold time
The following additional letters are used with these meanings:
H
High
X
L
V
Low
Valid
Z
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Unknown, changing, or don’t care
level
High impedance
• HOUSTON, TEXAS 77251-1443
25
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
external reference resonator/crystal oscillator clock option
The oscillator is enabled by connecting the appropriate fundamental 4–20 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 4a. The oscillator is a singlestage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.
An external oscillator source can be used by connecting a 1.8 V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 4b.
OSCIN
C1
(see Note A)
OSCOUT
Crystal
OSCIN
C2
(see Note A)
External
Clock Signal
(toggling 0–1.8 V)
(a)
(b)
NOTE A: The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 4. Crystal/Clock Connection
26
OSCOUT
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
ZPLL and clock specifications
timing requirements for ZPLL circuits enabled or disabled
MIN
TYP
MAX
UNIT
20
MHz
f(OSC)
Input clock frequency
tc(OSC)
Cycle time, OSCIN
50
ns
tw(OSCIL)
Pulse duration, OSCIN low
15
ns
tw(OSCIH)
Pulse duration, OSCIN high
15
ns
f(OSCRST)
OSC FAIL
4
frequency†
53
kHz
† Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1) bits equal
to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (literature number
SPNU189).
switching characteristics over recommended operating conditions for clocks‡§
PARAMETER
f(SYS)
System clock frequency#
f(CONFIG)
System clock frequency - flash config mode
f(ICLK)
Interface clock frequency
f(ECLK)
External clock output frequency for ECP Module
tc(SYS)
Cycle time, system clock
tc(CONFIG)
Cycle time, system clock - flash config mode
tc(ICLK)
Cycle time, interface clock
tc(ECLK)
Cycle time, ECP module external clock output
TEST CONDITIONS¶
MIN
MAX
Pipeline mode enabled
48
Pipeline mode disabled
24
24
Pipeline mode enabled
25
Pipeline mode disabled
24
Pipeline mode enabled
25
Pipeline mode disabled
24
Pipeline mode enabled
20.8
Pipeline mode disabled
41.6
41.6
Pipeline mode enabled
40
Pipeline mode disabled
41.6
Pipeline mode enabled
40
Pipeline mode disabled
41.6
UNIT
MHz
MHz
MHz
MHz
ns
ns
ns
ns
‡ f(SYS) = M × f(OSC) / R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the CLKDIVPRE
[2:0] bits in the global control register (GLBCTRL.[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the GLBCTRL register
(GLBCTRL.3).
f(SYS) = f(OSC) / R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f(ICLK) = f(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits
in the SYS module.
§ f(ECLK) = f(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
¶ Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
# Flash Vread must be set to 5V to achieve maximum System Clock Frequency.
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
ZPLL and clock specifications (continued)
switching characteristics over recommended operating conditions for external clocks
(see Figure 5 and Figure 6)†‡§
NO.
PARAMETER
TEST CONDITIONS
SYSCLK or MCLK
1
tw(COL)
MIN
ICLK, X is odd and not
1#
tw(COH)
Pulse duration, CLKOUT high ICLK, X is even or
0.5tc(SYS) – tr
0.5tc(ICLK) – tr
1#
ICLK, X is odd and not 1
3
4
tw(EOL)
tw(EOH)
Pulse duration, ECLK low
Pulse duration, ECLK high
#
0.5tc(ECLK) – tf
N is odd and X is even
0.5tc(ECLK) – tf
N is odd and X is odd and not 1
0.5tc(ECLK) + 0.5tc(SYS) – tf
N is even and X is even or odd
0.5tc(ECLK) – tr
0.5tc(ECLK) – tr
N is odd and X is even
0.5tc(ECLK) – 0.5tc(SYS) – tr
† X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module.
‡ N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
§ CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
¶ Clock source bits selected as either SYSCLK (CLKCNTL.[6:5] = 11 binary) or MCLK (CLKCNTL.[6:5] = 10 binary).
# Clock source bits selected as ICLK (CLKCNTL.[6:5] = 01 binary).
2
CLKOUT
1
Figure 5. CLKOUT Timing Diagram
4
ECLK
3
Figure 6. ECLK Timing Diagram
POST OFFICE BOX 1443
ns
0.5tc(ICLK) – 0.5tc(SYS) – tr
N is even and X is even or odd
N is odd and X is odd and not 1
28
ns
0.5tc(ICLK) + 0.5tc(SYS) – tf
SYSCLK or MCLK¶
2
UNIT
0.5tc(ICLK) – tf
ICLK, X is even or 1#
Pulse duration, CLKOUT low
MAX
0.5tc(SYS) – tf
¶
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ns
ns
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
RST and PORRST timings
timing requirements for PORRST (see Figure 7)
MIN
NO.
MAX UNIT
VCCPORL
VCC low supply level when PORRST must be active during power up
VCCPORH
VCC high supply level when PORRST must remain active during power up and
become active during power down
VCCIOPORL
VCCIO low supply level when PORRST must be active during power up
VCCIOPORH
VCCIO high supply level when PORRST must remain active during power up and
become active during power down
VIL
Low-level input voltage after VCCIO > VCCIOPORH
VIL(PORRST)
Low-level input voltage of PORRST before VCCIO > VCCIOPORL
3
tsu(PORRST)r
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
0
ms
5
tsu(VCCIO)r
Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL
0
ms
6
th(PORRST)r
Hold time, PORRST active after VCC > VCCPORH
1
ms
0.6
1.5
V
V
1.1
2.75
V
V
0.2 VCCIO
V
0.5
V
7
tsu(PORRST)f
Setup time, PORRST active before VCC ≤ VCCPORH during power down
8
μs
8
th(PORRST)rio
Hold time, PORRST active after VCC > VCCIOPORH
1
ms
9
th(PORRST)d
Hold time, PORRST active after VCC < VCCPORL
0
ms
10
tsu(PORRST)fio
Setup time, PORRST active before VCC ≤ VCCIOPORH during power down
0
ns
11
tsu(VCCIO)f
Setup time, VCC < VCCPORL before VCCIO < VCCIOPORL
0
ns
VCCP/ VCCIO
VCCIOPORH
VCC
VCCPORH
6
VCCIOPORL
VCC
VCCP/VCCIO
PORRST
VCCIOPORH
VCCIO
8
11
VCC
7
6
VCCPORL
VCCPORH
10
7
VCCPORL
VCCIOPORL
5
3
9
VIL(PORRST)
VIL
VIL
VIL
VIL
VIL(PORRST)
Figure 7. PORRST Timing Diagram
switching characteristics over recommended operating conditions for RST‡
PARAMETER
tv(RST)
tfsu
MIN
4112tc(OSC)
Valid time, RST active after PORRST inactive
8tc(SYS)
Valid time, RST active (all others)
Flash start up time, from RST inactive to fetch of first instruction from flash
(flash pump stabilization time)
336tc(OSC)
MAX
UNIT
ns
ns
‡ Specified values do NOT include rise/fall times. For rise and fall timings, see the switching characteristics for output timings versus load
capacitance table.
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29
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
JTAG scan interface timing (JTAG clock specification 10-MHz and 50-pF load on TDO output)
MIN
NO.
UNIT
1
Cycle time, JTAG low and high period
50
ns
2
tsu(TDI/TMS - TCKr)
Setup time, TDI, TMS before TCK rise (TCKr)
15
ns
3
th(TCKr -TDI/TMS)
Hold time, TDI, TMS after TCKr
15
ns
4
th(TCKf -TDO)
Hold time, TDO after TCKf
10
ns
5
td(TCKf -TDO)
Delay time, TDO valid after TCK fall (TCKf)
45
TCK
1
1
TMS
TDI
2
3
TDO
4
5
Figure 8. JTAG Scan Timing
30
MAX
tc(JTAG)
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ns
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
output timings
switching characteristics for output timings versus load capacitance (CL) (see Figure 9)
MIN
PARAMETER
tr
tf
tf
tf
tr
tf
Rise time, CLKOUT, AWD, TDO
Fall time, CLKOUT, AWD, TDO
Rise time, SPI1CLK, SPI1SOMI, SPI1SIMO, SPI2CLK,
SPI2SOMI, SPI2SIMO
Fall time, RST, SPI1CLK, SPI1SOMI, SPI1SIMO, SPI2CLK,
SPI2SOMI, SPI2SIMO
Rise time, all other output pins
Fall time, all other output pins
0.5
2.50
CL = 50 pF
1.5
5
CL = 100 pF
3
9
CL = 150 pF
4.5
12.5
CL = 15 pF
0.5
2.5
CL = 50 pF
1.5
5
CL = 100 pF
3
9
CL = 150 pF
4.5
12.5
CL = 15 pF
2.5
8
CL= 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
8
CL= 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
10
CL = 50 pF
6.0
25
CL = 100 pF
12
45
CL = 150 pF
18
65
CL = 15 pF
3
10
CL = 50 pF
8.5
25
CL = 100 pF
16
45
CL = 150 pF
23
65
tr
ns
ns
ns
ns
ns
ns
tf
80%
Output
MAX UNIT
CL = 15 pF
20%
VCC
80%
20%
0
Figure 9. CMOS-Level Outputs
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31
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
input timings
timing requirements for input timings† (see Figure 10)
PARAMETER
tpw
MIN
tc(ICLK) + 10
Input minimum pulse width
† tc(ICLK) = interface clock cycle time = 1/f(ICLK)
tpw
Input
80%
20%
VCC
80%
20%
Figure 10. CMOS-Level Inputs
32
POST OFFICE BOX 1443
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0
MAX
UNIT
ns
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
flash timings
timing requirements for program flash†
MIN
PARAMETER
tprog(16-bit)
64K-byte programming
MAX
UNIT
16
200
μs
0.5
2
s
4
Half word (16-bit) programming time
tprog(Total)
TYP
time‡
terase(sector)
Sector erase time
twec
Write/erase cycles at TA = 125°C
tfp(RST)
2
15
s
100
cycles
Flash pump settling time from RST to SLEEP
67tc(SYS)
ns
tfp(SLEEP)
Initial flash pump settling time from SLEEP to STANDBY
67tc(SYS)
ns
tfp(STDBY)
Initial flash pump settling time from STANDBY to ACTIVE
34tc(SYS)
ns
† For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.
‡ The 64K-byte programming times include overhead of state machine.
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33
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
SPIn master mode timing parameters
SPIn master mode external timing parameters (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)†‡§ (see Figure 11)
NO.
1
2#
3#
MIN
tc(SPC)M
6
MAX
100
256tc(ICLK)
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid
(clock polarity = 0)
0
10
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid
(clock polarity = 1)
0
10
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 0)
6
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 1)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 0)
4
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 1)
4
4#
5#
Cycle time, SPInCLK
¶
#
7#
UNIT
ns
ns
ns
ns
tc(SPC)M – 5 – tr/f
ns
ns
ns
† The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the “switching characteristics for output timings versus load capacitance” table.
¶ When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
# The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
34
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SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 11. SPIn Master Mode External Timing (CLOCK PHASE = 0)
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SPIn master mode timing parameters (continued)
SPIn master mode external timing parameters (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)†‡§ (see Figure 12)
MIN
MAX
UNIT
100
256tc(ICLK)
ns
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
NO.
1
2#
3#
4
tc(SPC)M
Cycle time, SPInCLK
tw(SPCH)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0)
0.5tc(SPC)M – 10
tv(SIMO-SPCL)M
Valid time, SPInCLK low after SPInSIMO data valid
(clock polarity = 1)
0.5tc(SPC)M – 10
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)M – 5 – tr
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
0.5tc(SPC)M – 5 – tf
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 0)
6
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 1)
6
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
4
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
4
#
5#
6#
7
¶
#
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
# The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
36
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SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
Data Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 1)
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SPIn slave mode timing parameters
SPIn slave mode external timing parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)†‡§¶ (see Figure 13)
NO.
1
4
5
MAX
UNIT
ns
Cycle time, SPInCLK
100
256tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high
(clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
td(SPCH-SOMI)S
Delay time, SPInCLK high to SPInSOMI valid
(clock polarity = 0)
6 + tr
td(SPCL-SOMI)S
Delay time, SPInCLK low to SPInSOMI valid
(clock polarity = 1)
6 + tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after
SPInCLK high (clock polarity =0)
tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after
SPInCLK low (clock polarity =1)
tc(SPC)S – 6 – tf
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 0)
6
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 1)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after
SPInCLK low (clock polarity = 0)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after
SPInCLK high (clock polarity = 1)
6
2||
3
MIN
tc(SPC)S
||
||
||
6||
7||
#
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
‡ If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
# When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
||
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
6
7
SPInSIMO
SPISIMO Data
Must Be Valid
Figure 13. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
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SPIn slave mode timing parameters (continued)
SPIn slave mode external timing parameters (CLOCK PHASE = 1, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)†‡§¶ (see Figure 14)
NO.
1
2
MIN
MAX
UNIT
100
256tc(ICLK)
ns
Pulse duration, SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high
(clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tv(SOMI-SPCH)S
Valid time, SPInCLK high after SPInSOMI
data valid (clock polarity = 0)
0.5tc(SPC)S – 6 – tr
tv(SOMI-SPCL)S
Valid time, SPInCLK low after SPInSOMI
data valid (clock polarity = 1)
0.5tc(SPC)S – 6 – tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after
SPInCLK high (clock polarity =0)
0.5tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after
SPInCLK low (clock polarity =1)
0.5tc(SPC)S – 6 – tf
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK
high (clock polarity = 0)
6
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK
low (clock polarity = 1)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after
SPInCLK high (clock polarity = 0)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after
SPInCLK low (clock polarity = 1)
6
tc(SPC)S
Cycle time, SPInCLK
tw(SPCH)S
||
3||
4||
5||
6||
7||
#
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
‡ If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
# When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
||
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
40
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SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
Data Valid
6
7
SPInSIMO
SPISIMO Data Must
Be Valid
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
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SCIn isosynchronous mode timings — internal clock
timing requirements for internal clock SCIn isosynchronous mode†‡§ (see Figure 15)
(BAUD + 1)
IS EVEN OR BAUD = 0
NO.
(BAUD + 1)
IS ODD AND BAUD ≠ 0
UNIT
MIN
MAX
MIN
MAX
2tc(ICLK)
224tc(ICLK)
3tc(ICLK)
(224 –1) tc(ICLK)
1
tc(SCC)
Cycle time, SCInCLK
2
tw(SCCL)
Pulse duration,
SCInCLK low
0.5tc(SCC) – tf
0.5tc(SCC) + 5
0.5tc(SCC) +0.5tc(ICLK) – tf 0.5tc(SCC) +0.5tc(ICLK)
ns
3
tw(SCCH)
Pulse duration,
SCInCLK high
0.5tc(SCC) – tr
0.5tc(SCC) + 5
0.5tc(SCC) –0.5tc(ICLK) – tr 0.5tc(SCC) –0.5tc(ICLK)
ns
4
td(SCCH-TXV)
Delay time, SCInCLK
high to SCInTX valid
5
tv(TX)
Valid time, SCInTX data
after SCInCLK low
6
tsu(RX-SCCL)
Setup time, SCInRX
before SCInCLK low
7
tv(SCCL-RX)
Valid time, SCInRX data
- tc(ICLK) + tf + 20
after SCInCLK low
10
10
ns
tc(SCC) – 10
tc(SCC) – 10
ns
tc(ICLK) + tf + 20
tc(ICLK) + tf + 20
ns
- tc(ICLK) + tf + 20
ns
† BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the switching characteristics for output timings versus load capacitance table.
1
3
2
SCICLK
5
4
Data Valid
SCITX
6
7
Data Valid
SCIRX
NOTE A: Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 15. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
42
ns
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SCIn isosynchronous mode timings — external clock
timing requirements for external clock SCIn isosynchronous mode†‡ (see Figure 16)
NO.
MIN
MAX
8tc(ICLK)
UNIT
1
tc(SCC)
Cycle time, SCInCLK
2
tw(SCCH)
Pulse duration, SCInCLK high
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
3
tw(SCCL)
Pulse duration, SCInCLK low
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
4
td(SCCH-TXV)
Delay time, SCInCLK high to SCInTX valid
2tc(ICLK) + 12 + tr
ns
5
tv(TX)
Valid time, SCInTX data after SCInCLK low
6
tsu(RX-SCCL)
Setup time, SCInRX before SCInCLK low
7
tv(SCCL-RX)
Valid time, SCInRX data after SCInCLK low
§
ns
2tc(SCC)–10
ns
0
ns
2tc(ICLK) + 10
ns
† tc(ICLK) = interface clock cycle time = 1/f(ICLK)
‡ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
§ When driving an external SCInCLK, the following must be true: tc(SCC) ≥ 8tc(ICLK)
1
2
3
SCICLK
5
4
Data Valid
SCITX
6
7
Data Valid
SCIRX
NOTE A: Data transmission/reception characteristics for isosynchronous mode with external clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 16. SCIn Isosynchronous Mode Timing Diagram for External Clock
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high-end timer (HET) timings
minimum PWM output pulse width:
This is equal to one High Resolution Clock Period (HRP). The HRP is defined by the 6-bit High Resolution
Prescale Factor (hr) which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.
Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK
For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns
minimum input pulses we can capture:
The input pulse width must be greater or equal to the Low Resolution Clock Period (LRP), i.e., the HET loop
(the HET program must fit within the LRP). The LRP is defined by the 3-bit Loop-Resolution Prescale Factor
(lr), which is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.
Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK
For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns
Note: Once the input pulse width is greater than LRP, the resolution of the measurement is still HRP. (That is,
the captured value gives the number of HRP clocks inside the pulse.)
Abbreviations:
High resolution clock period = HRP = hr/SYSCLK
Loop resolution clock period = LRP = hr*lr/SYSCLK
hr = HET high resolution divide rate = 1, 2, 3,...63, 64
lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32
44
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standard CAN controller (SCC) mode timings
dynamic characteristics for the CANSTX and CANSRX pins
MIN
PARAMETER
td(CANSTX)
Delay time, transmit shift register to CANSTX pin†
td(CANSRX)
Delay time, CANSRX pin to receive shift register
MAX
UNIT
15
ns
5
ns
† These values do not include rise/fall times of the output buffer.
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multi-buffered A-to-D converter (MibADC)
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on
VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to
ADREFLO unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bits (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assured
Output conversion code . . . . . . . . . . . . . . . . . . . . . . . .00h to 3FFh [00 for VAI ≤ADREFLO; 3FF for VAI ≥ ADREFHI]
MibADC recommended operating conditions†
ADREFHI
A-to-D high -voltage reference source
ADREFLO
A-to-D low-voltage reference source
VAI
Analog input voltage
MAX
UNIT
VCCAD
V
VSSAD
VCCAD
V
VSSAD − 0.3
VCCAD + 0.3
V
−2
2
mA
‡
Analog input clamp current
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
IAIC
MIN
VSSAD
† For VCCAD and VSSAD recommended operating conditions, see the "device recommended operating conditions" table.
‡ Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
operating characteristics over full ranges of recommended operating conditions§¶
PARAMETER
Analog input resistance
See Figure 17
Ci
Analog input capacitance
See Figure 17
IAIL
Analog input leakage current
See Figure 17
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
CR
Conversion range over which specified
accuracy is maintained
ADREFHI − ADREFLO
EDNL
Differential nonlinearity error
EINL
ETOT
MIN
MAX
UNIT
250
500
Ω
Conversion
10
pF
Sampling
30
pF
1
μA
5
mA
–1
3.6
V
Difference between the actual step width and the
ideal value after offset correction. (See Figure 18)
±2
LSB
Integral nonlinearity error
Maximum deviation from the best straight line through
the MibADC. MibADC transfer characteristics,
excluding the quantization error after offset
correction.
(See Figure 19)
±2
LSB
Total error/Absolute accuracy
Maximum value of the difference between an analog
value and the ideal midstep value.
(See Figure 20)
±2
LSB
§ VCCAD = ADREFHI
¶ 1 LSB = (ADREFHI – ADREFLO)/210 for the MibADC
46
TYP
DESCRIPTION/CONDITIONS
Ri
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multi-buffered A-to-D converter (MibADC) (continued)
External
Rs
MibADC
Input Pin
Ri
Sample Switch
Parasitic
Capacitance
Vsrc
Sample
Capacitor
Rleak
Ci
Figure 17. MibADC Input Equivalent Circuit
multi-buffer ADC timing requirements
MIN
MAX
UNIT
μs
tc(ADCLK)
Cycle time, MibADC clock
td(SH)
Delay time, sample and hold time
1
μs
td(C)
Delay time, conversion time
0.55
μs
td(SHC)†
Delay time, total sample/hold and conversion time
1.55
μs
0.05
† This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for more
details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
multi-buffered A-to-D converter (MibADC) (continued)
The differential nonlinearity error shown in Figure 18 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
Digital Output Code
0 ... 101
0 ... 100
0 ... 011
Differential
Linearity Error (1/2 LSB)
1 LSB
0 ... 010
0 ... 001
1 LSB
Differential Linearity
Error (–1/2 LSB)
0 ... 000
0
1
2
3
4
Analog Input Value (LSB)
5
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
Figure 18. Differential Nonlinearity (DNL)
The integral nonlinearity error shown in Figure 19 (sometimes referred to as linearity error) is the deviation of
the values on the actual transfer function from a straight line.
0 ... 111
Digital Output Code
0 ... 110
Ideal
Transition
0 ... 101
Actual
Transition
0 ... 100
At Transition
011/100
(– 1/2 LSB)
0 ... 011
0 ... 010
End-Point Lin. Error
At Transition
001/010 (– 1/4 LSB)
0 ... 001
0 ... 000
0
1
2
3
4
5
6
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
7
Figure 19. Integral Nonlinearity (INL) Error
48
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
multi-buffer A-to-D converter (MibADC) (continued)
The absolute accuracy or total error of an MibADC as shown in Figure 20 is the maximum value of the difference
between an analog value and the ideal midstep value.
0 ... 111
Digital Output Code
0 ... 110
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
0 ... 011
0 ... 010
Total Error
At Step
0 ... 001 (1/2 LSB)
0 ... 001
0 ... 000
0
1
2
3
4
5
6
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
7
Figure 20. Absolute Accuracy (Total) Error
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49
TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
MECHANICAL DATA
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
1
0,13 NOM
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
14,20
SQ
13,80
0,05 MIN
0°-7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
50
PARAMETER
°C/W
RΘJA
48
RΘJC
5
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
List of Figures
TMS470R1VF334 80-Pin Pin Package (TOP VIEW)
Functional Block Diagram
Figure 1. Memory Map
Figure 2. TMS470R1x Family Nomenclature
Figure 3. Test Load Circuit
Figure 4. Crystal/Clock Connection
Figure 5. CLKOUT Timing Diagram
Figure 6. ECLK Timing Diagram
Figure 7. PORRST Timing Diagram
Figure 8. JTAG Scan Timing
Figure 9. CMOS-Level Outputs
Figure 10. CMOS-Level Inputs
Figure 11. SPIn Master Mode External Timing (CLOCK PHASE = 0)
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 1)
Figure 13. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
Figure 15. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
Figure 16. SCIn Isosynchronous Mode Timing Diagram for External Clock
Figure 17. MibADC Input Equivalent Circuit
Figure 18. Differential Nonlinearity (DNL)
Figure 19. Integral Nonlinearity (INL) Error
Figure 20. Absolute Accuracy (Total) Error
Mechanical Data
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
52
Device Characteristics
Memory Selection Assignment
Flash Sectors
VF334 Peripherals, System Module, and Flash Base Addresses
Interrupt Priority
MibADC Event Hookup Configuration
TMS470 Device ID Bit Allocation Register
Device Part Number
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TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
REVISION HISTORY
REVISION HISTORY
REV
D
DATE
8/06
NOTES
Updates:
Page 21, operating junction temperature range broken out into A, T, and Q versions
Page 34, timing #5 updated
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53
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