TLV5610IYZ SBAS389A – JULY 2006 – REVISED JULY 2006 2.7V to 5.5V, 12-Bit, Octal DIGITAL-TO-ANALOG CONVERTER in a Wafer Chip-Scale Package—Pb-Free/Green FEATURES APPLICATIONS • • • • • • • • • • • • • • • • Eight, 12-Bit, Voltage Output DACs in One Package Pin-Compatible, Pb-Free, RoHS-Compliant Upgrade to the TLV5610IYE Programmable Settling Time versus Power Consumption: – 1µs in Fast Mode – 3µs in Slow Mode Compatible With TMS320™ DSP Family and SPI™ Serial Ports Differential and Single-Ended Analog Input/Output Separate Software Control for ADC and DAC Power Down Monotonic Over Temperature Low Power Consumption: – 18mW in Slow Mode at 3V – 48mW in Fast Mode at 3V Power Down Mode Buffered, High-Impedance Reference Inputs Data Output for Daisy-Chaining Digital Servo-Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices WAFER CHIP-SCALE PACKAGE (BOTTOM VIEW) LDAC MODE OUTD REF 18 17 16 DOUT 19 DVDD 20 OUTB OUTC 15 14 13 12 DGND 1 DIN 2 34 56 FS SCLK AVDD 10 AGND 9 OUTH 78 OUTE PRE OUTA 11 OUTG OUTF DESCRIPTION The TLV5610IYZ is the lead-free version of the TLV5610IYE, an eight-channel, 12-bit, voltage output digital-to-analog converter (DAC) with a flexible serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI™, and Microwire™ serial ports. It is programmed with a 16-bit serial string containing four control and 12 data bits. Additional features include a power-down mode, an LDAC input for simultaneous update of all eight DAC outputs, and a data output that can be used to cascade multiple devices. The resistor string output voltage is buffered by a rail-to-rail output amplifier with a programmable settling time to allow the designer to optimize speed versus power dissipation. The buffered, high-impedance reference input can be connected to the supply voltage. The TLV5610IYZ is implemented in a CMOS process and is available in a 20-terminal wafer chip-scale package (WCSP). The TLV5610IYZ is characterized for operation from –40°C to +85°C in a wire-bonded small outline (SO) package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320 is a trademark of Texas Instruments, Inc. SPI, QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TLV5610IYZ www.ti.com SBAS389A – JULY 2006 – REVISED JULY 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TA WCSP-20 PACKAGE (1) –40°C to +85°C TLV5610IYZ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted) (1) TLV5610IYZ UNIT 7 V Reference input voltage range – 0.3 to AVDD + 0.3 V Digital input voltage range – 0.3 to DVDD + 0.3 V –40 to +85 °C Supply voltage (AVDD, DVDD to GND) Operating free-air temperature range, TA (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Supply voltage, AVDD, DVDD MIN NOM MAX 5V operation 4.5 5 5.5 V 3V operation 2.7 3 3.3 V High-level digital input, VIH DVDD = 2.7V to 5.5V Low-level digital input, VIL DVDD = 2.7V to 5.5V Reference voltage, VREF 2 V V GND 4.096 AVDD AVDD = 3V GND 2.048 AVDD 2 V kΩ Load capacitance, CL 100 pF Clock frequency, fCLK 30 MHz +85 °C Operating free-air temperature, TA 2 V 0..8 AVDD = 5V Load resistance. RL UNIT –40 Submit Documentation Feedback TLV5610IYZ www.ti.com SBAS389A – JULY 2006 – REVISED JULY 2006 ELECTRICAL CHARACTERISTICS Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 16 21 mA 6 8 mA Power Supply IDD Power-supply current Fast Slow No load, VREF = 4.096V, all inputs = DVDD or GND Power-down supply current POR Power-on threshold PSRR Power-supply rejection ratio µA 0.1 Full-scale; see Note (1) 2 V –60 dB Static DAC Specifications Resolution 12 INL Integral nonlinearity Code 40 to 4095, VREF = 2V, 4V ±2 DNL Differential nonlinearity Code 40 to 4095, VREF = 2V, 4V ±0.5 EZS Zero-scale error (offset error at zero-scale) EZS TC Zero-scale error temperature coefficient EG Gain error EG TC Gain error temperature coefficient Bits ±6 LSB ±1 LSB ±30 mV µV/°C 30 ±0.6 10 % Full-Scale V ppm/°C Output Specifications VO Voltage output range RL = 10kΩ Output load regulation accuracy RL = 2kΩ vs 10kΩ 0 AVDD – 4 ±0.3 V % Full-Scale V Reference Input VI Input voltage range RI Input resistance CI Input capacitance Reference input bandwidth 0 AVDD 100 5 Fast Slow VREF = 0.4VPP + 2.048VDC, input code = 0x800 VREF = 2VPP at 1kHz + 2.048VDC (2) Reference feedthrough V kΩ pF 2.2 MHz 1.9 MHz –84 dB Digital Inputs IIH High-level digital input current VI = DVDD IIL Low-level digital input current VI = 0V CI Input capacitance 1 µA µA –1 8 pF Digital Outputs VOH High-level digital output voltage RL = 10kΩ VOL Low-level digital output voltage RL = 10kΩ Output voltage rise time RL = 10kΩ, CL = 20pF, incl. propagation delay 2.6 V 0.4 V 7 20 ns 1 3 µs 3 7 µs 0.5 1 µs 1 2 Analog Output Dynamic Performance tS(FS) tS(CC) SR (1) (2) (3) (4) (5) (6) Output settling time (3), full-scale Output settling time (4), code to code Slew rate (5) Fast Slow Fast Slow Fast Slow RL = 10kΩ, CL = 1000pF RL = 10kΩ, CL = 1000pF RL = 10kΩ, CL = 1000pF (6) Glitch energy See Note Channel crosstalk 10kHz sine, 4VPP µs 4 10 1 3 V/µs 4 nV-s –90 V/µs dB Power-supply rejection ratio at full-scale is measured by varying AVDD and is given by the following equation: PSRR = 20 log[(EG(AVDDmax) – EG(AVDDmin))]/VDDmax. Reference feedthrough is measured at the DAC output with an input code = 0x000. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x80 to 0xFFF and 0xFFF to 0x080, respectively. Assured by design; not production tested. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one count. The max time applies to code changes near zero scale or full-scale. Assured by design; not production tested. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. Code transition: 0x7FF to 0x800. Submit Documentation Feedback 3 TLV5610IYZ www.ti.com SBAS389A – JULY 2006 – REVISED JULY 2006 twH twL SCLK X 4 3 2 1 16 17 X th(D) tsu(D) DIN X D15 DOUT X D15 D14 (1) D14 D13 (1) D13 D12 (1) D12 D1 (1) D1 D0 (1) D0 X (1) X tsu(FS - C17) tsu(FS - CK) tsu(C16 - FS) twH(FS) FS (mC Mode) tsu(CK - FS) twL(FS) FS (DSP Mode) X NOTE: (1) Previous input data. Figure 1. Serial Interface Timing t wL(LDAC) LDAC ts ±0.5 LSB OUTx Figure 2. Output Timing DIGITAL INPUT TIMING REQUIREMENTS PARAMETER tsu(FS-CK) Setup time, FS low before next negative SCLK edge TYP MAX UNIT 8 ns tsu(C16-FS) Setup time, 16th negative edge after FS low on which bit D0 is sampled before rising edge of FS. µC mode only 10 ns tsu(FS-C17) µC mode, setup time, FS high before 17th positive SCLK. 10 ns tsu(CK-FS) DSP mode, setup time, SLCK low before FS low. 5 ns twL(LDAC) LDAC duration low 10 ns twH SCLK pulse duration high 16 ns twL SCLK pulse duration low 16 ns tsu(D) Setup time, data ready before SCLK falling edge 8 ns th(D) Hold time, data held valid after SCLK falling edge 5 ns twH(FS) FS duration high 10 ns twL(FS) FS duration low 10 ns ts 4 MIN See Analog Output Dynamic Performance Settling time Submit Documentation Feedback TLV5610IYZ www.ti.com SBAS389A – JULY 2006 – REVISED JULY 2006 Functional Block Diagram REF 12/10 12/10 12/10 X2 DAC A Holding Latch OUTA DAC A Latch SCLK DIN DOUT 12 Serial Interface FS 8 DAC B, C, D, E, F, G, and H Same as DAC A MODE PRE LDAC OUT B, C, D, E, F, G, and H Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AGND 10 P Analog ground AVDD 11 P Analog power supply DGND 1 P Digital ground DIN 2 I Digital serial data input DOUT 19 O Digital serial data output DVDD 20 P Digital power supply FS 4 I Frame sync input LDAC 18 I Load DAC. The DAC outputs are only updated if this signal is low. It is an asynchronous input. MODE 17 I DSP/µC mode pin. High = µC mode; NC = DSP mode. PRE 5 I Preset input REF 16 I Voltage reference input SCLK 3 I Serial clock input 12–15, 6–9 O DAC outputs A, B, C, D, E, F, G and H OUTA–OUTH Submit Documentation Feedback 5 TLV5610IYZ www.ti.com SBAS389A – JULY 2006 – REVISED JULY 2006 TYPICAL CHARACTERISTICS OUTPUT LOAD REGULATION OUTPUT LOAD REGULATION 1.0 1.0 VDD = 3V, VREF = 2V, Zero Scale 0.9 VDD = 5V, VREF = 4V Zero Scale 0.9 0.8 0.8 0.7 VO, Output Voltage (V) VO, Output Voltage (V) Fast 0.6 0.5 0.4 0.3 0.7 0.6 0.5 Fast 0.4 0.3 0.2 0.2 0.1 0.1 Slow Slow 0 0 0.5 0 1.5 1.0 Sinking Current, mA 0 2.0 0.5 Figure 3. 1.5 1.0 Sinking Current (mA) 2.0 Figure 4. OUTPUT LOAD REGULATION OUTPUT LOAD REGULATION 2.06 4.12 2.055 Slow VDD = 3V, VREF = 2V, Full Scale VDD = 5V, VREF = 4V Full Scale 4.11 Fast 2.05 VO, Output Voltage (V) VO, Output Voltage (V) 4.10 Fast 2.045 2.04 2.035 Slow 4.09 4.08 4.07 4.06 2.03 2.025 0.05 4.05 4.04 0.5 1 1.5 2 2.5 3 Sourcing Current (mA) 3.5 4 0 1.0 1.5 2.0 2.5 Sourcing Current (mA) Figure 5. 6 0.5 Figure 6. Submit Documentation Feedback 3.0 3.5 4.0 TLV5610IYZ www.ti.com SBAS389A – JULY 2006 – REVISED JULY 2006 TYPICAL CHARACTERISTICS (continued) INTEGRAL NONLINEARITY vs CODE 4 3 INL (LSB) 2 1 0 -1 -2 -3 -4 0 1024 2048 3072 4096 3072 4096 Code Figure 7. DIFFERENTIAL NONLINEARITY vs CODE 1.0 0.8 0.4 DNL (LSB) 0.6 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 Code Figure 8. Submit Documentation Feedback 7 TLV5610IYZ www.ti.com SBAS389A – JULY 2006 – REVISED JULY 2006 APPLICATION INFORMATION GENERAL FUNCTION The TLV5610IYZ is an eight-channel, 12-bit, single-supply DAC, based on a resistor string architecture. The TLV5610IYZ, a green/PB-free device, is pin-compatible with the TLV5610IYE. The TLV5610IYZ consists of a serial interface, a speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer. The output voltage (full-scale determined by external reference) for each channel is given by: REF CODE [V] 0x1000 (1) Where: REF is the reference voltage. CODE is the digital input value. The input range is 0x000 to 0xFFF. A power on reset initially puts the internal latches to a defined state (all bits zero). SERIAL INTERFACE A falling edge of FS starts shifting the data on DIN, starting with the MSB to the internal register on the falling edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC holding registers, depending on the address bits within the data word. A logic '0' on the LDAC pin is required to transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an asynchronous input; it can be held low if a simultaneous update of all eight channels is not needed. For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles. DSP Mode: SCLK FS DIN X D15 D14 D1 D0 E15 E14 X D15 D14 D1 D0 X E15 E1 E0 X E1 E0 X X F15 F15 X F15 F15 mC Mode: SCLK FS DIN E14 X Figure 9. Timing Diagrams The differences between DSP mode (MODE = NC or 0) and µC (MODE = 1) mode: • In µC mode, FS must be held low until all 16 data bits have been transferred. If FS is driven high before the 16th falling clock edge, the data transfer is cancelled. The DAC is updated after a rising edge on FS. • In DSP mode, FS must only stay low for 20ns and can go high before the 16th falling clock edge. 8 Submit Documentation Feedback TLV5610IYZ www.ti.com SBAS389A – JULY 2006 – REVISED JULY 2006 APPLICATION INFORMATION (continued) SERIAL CLOCK FREQUENCY AND UPDATE RATE The maximum serial clock frequency is given by: 1 f + + 30MHz sclkmax t )t whmin wlmin (2) The maximum update rate is given by: 1 f + + 1.95MHz updatemax Ǔ 16ǒt )t whmin wlmin (3) Note that the maximum update rate is just a theoretical value for the serial interface because the settling time of the DAC must also be considered. DATA FORMAT The 16 bit data word consists of two parts: 1. Address bits (D15...D12) 2. Data bits (D11...D0) Table 1. Data Format (1) D15 D14 D13 D12 A3 A2 A1 A0 (1) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data Ax: Address bits. See Table 2. REGISTER MAP Table 2. Register Map A3 A2 A1 A0 FUNCTION 0 0 0 0 DAC A 0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 0 1 0 0 DAC E 0 1 0 1 DAC F 0 1 1 0 DAC G 0 1 1 1 DAC H 1 0 0 0 CTRL0 1 0 0 1 CTRL1 1 0 1 0 Preset 1 0 1 1 Reserved 1 1 0 0 DAC A and B 1 1 0 1 DAC C and D 1 1 1 0 DAC E and F 1 1 1 1 DAC G and H Submit Documentation Feedback 9 TLV5610IYZ www.ti.com SBAS389A – JULY 2006 – REVISED JULY 2006 DAC A-H AND TWO-CHANNEL REGISTERS Writing to DAC A–H sets the output voltage of channel A–H. It is possible to automatically generate the complement of one channel by writing to one of the four, two-channel registers (DAC A and B, etc.). The TLV5610IYZ decodes all 12 data bits. PRESET The outputs of all DAC channels can be driven to a predefined value stored in the preset register by driving the PRE input low. The PRE input is asynchronous to the clock. CTRL0 Table 3. CTRL0 Bit Register D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X PD DO X X IM Bit Definitions: PD Full Device Power Down. 0 = Normal 1 = Power Down DO Digital Output Enable. 0 = Disable 1 = Enable IM Input Mode. 0 = Straight Binary 1 = Twos Complement X Reserved. If DOUT is enabled, the data input on DIN is output on DOUT with a 16-cycle delay. This feature makes it possible to daisy-chain multiple DACs on one serial bus. CTRL1 Table 4. CTRL1 Bit Register D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X PD DO X X IM Bit Definitions: PXY Power Down DACXY. In power-down mode, the amplifiers of the selected DAC pair within the device are disabled and the total power consumption of the device is significantly reduced. Power-down mode of a specific DAC pair can be selected by setting the PXY bit within the data word to '1'. 0 = Normal 1 = Power Down SXY DACXY Speed Mode. There are two settling time modes: fast and slow. Fast mode of a DAC pair is selected by setting SXY to '1', and slow mode is selected by setting SXY to '0'. 0 = Slow 1 = Fast NOTE: XY refers to DAC pair AB, CD, EF, or GH. 10 Submit Documentation Feedback TLV5610IYZ www.ti.com SBAS389A – JULY 2006 – REVISED JULY 2006 USING THE TLV5610IYZ WAFER CHIP-SCALE PACKAGE (WCSP) TLV5610 qualifications are done using a wire-bonded small outline (SO) package. The qualifications include: steady state life, thermal shock, ESD, latch-up, biased HAST, autoclave, and characterization. These qualified devices are orderable as TLV5610IDW. NOTE: The wafer chip-scale package (WCSP) for the TLV5610IYZ uses the same die as TLV5610IDW, but is not qualified. WCSP qualification, including board level reliability (BLR), is the responsibility of the customer. It is recommended that underfill be used for increased reliability. BLR is application-dependent, but may include tests such as: temperature cycling, drop test, key push, bend, vibration, and package shear. For general guidelines on board assembly of the WCSP, the following documentation provides more details: • • Application Report NanoStar™ & NanoFree™ 300µm Solder Bump WCSP Application—SBVA017 Design Summary WCSP Little Logic—SCET007B NOTE: The use of underfill is required and greatly reduces the risk of thermal mismatch fails. Underfill is an epoxy/adhesive that may be added during the board assembly process to improve board level/system level reliability. The process is to dispense the epoxy under the dice after die attach reflow. The epoxy adheres to the body of the device and to the printed-circuit board. It reduces stress placed upon the solder joints because of thermal coefficient of expansion (TCE) mismatch between the board and the component. Underfill material is highly filled with silica or other fillers to increase epoxy modulus, reduce creep sensitivity, and decrease material TCE. NOTE: The recommendation for peak flow temperatures of +250°C to +260°C is based on general empirical results that indicate that this temperature range is needed to facilitate good wetting of the solder bump to the substrate or circuit board pad. Lower peak temperatures may cause nonwets (cold solder joints). Bottom View Top View A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. Figure 10. TLV5610IYZ Wafer Chip-Scale Package Submit Documentation Feedback 11 TLV5610IYZ www.ti.com SBAS389A – JULY 2006 – REVISED JULY 2006 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (July 2006) to A Revision ......................................................................................................... Page • • • 12 Deleted separate INL and DNL specifications for Code 20 to 1023; not relevant to this device.......................................... 3 Replaced timing diagram ...................................................................................................................................................... 4 Updated Digital Input Timing Requirements Table ............................................................................................................... 4 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 21-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TLV5610IYZR ACTIVE DSBGA YZ 20 3000 Green (RoHS & no Sb/Br) SNAGCU Level-NC-NC-UNLIM TLV5610IYZT ACTIVE DSBGA YZ 20 250 Green (RoHS & no Sb/Br) SNAGCU Level-NC-NC-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TLV5610IYZR DSBGA YZ 20 3000 180.0 8.4 TLV5610IYZT DSBGA YZ 20 250 180.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.18 3.18 1.0 4.0 8.0 Q2 2.18 3.18 1.0 4.0 8.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5610IYZR DSBGA YZ 20 3000 220.0 220.0 34.0 TLV5610IYZT DSBGA YZ 20 250 220.0 220.0 34.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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