EXAR XRS10L120IL-F

EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
JUNE 2009
REV. 1.06
test and loopback features is achieved in a low cost
and lower power implementation.
FEATURES
GENERAL FEATURES
• Three independent 3/1.5Gbps SATA ports.
• Connects 1 host port to 2 device ports.
• Supports 3/1.5Gbps rate detection/speed
negotiation.
• Supports power down modes - Active, partial,
slumber and power down.
• Advanced features configurable through MDIO
bus.
The port multiplier function is used when one active
host has to communicate with multiple SATA drives.
The XRS10L120 supports up to 2 SATA drives and
utilizes the full bandwidth of the host connection.
The XRS10L120 includes enhanced features such as
staggered HDD spin-up, power management control,
hot plug capability and support for legacy software.
The XRS10L120 acts as a retimer, maintaining
independent signaling domains between the drives,
hosts and the external interconnect.
COMRESET/
The high-speed serial input feature: selectable
equalization and the high-speed serial output feature:
programmable pre-emphasis can be used to
compensate for ISI (Inter-Symbol Interference) and
increase maximum cable distances.
• High speed outputs with programmable pre-
XRS10L120 meets tight jitter budgets in SATA
applications. Exar's serial I/O technology enables
reliable data transmission over 1 meter of FR-4 and 4
meters of unequalized copper cable.
PORT MULTIPLIER LOGIC FEATURES
• Low latency architecture.
• Supports OOB signaling for SATA applications.
Internal OOB detectors
COMINIT and COMWAKE.
for
HIGH SPEED I/O FEATURES
emphasis to drive long interconnects.
• Selectable high speed input equalization for
optimum reception.
• Compliant with SATA Gen-2i & Gen-2m
specification.
• Enables reliable data transmission over 1 meter
of FR-4 and 4 meters or more of unequalized
copper cable.
• Supports spread spectrum clocking (SSC) to
reduce EMI.
PHYSICAL FEATURES
• CMOS 0.13 Micron Technology
• Single 1.2 V Power Supply
• -40°C to 85°C Industrial Temperature Range
• No heatsink or airflow required
• 64-Pin QFN Package
1.0
INTRODUCTION
The XRS10L120 provides the advantages of the
Serial ATA II Port Multiplier implementations for Serial
ATA II systems at 3.0 Gbps and 1.5 Gbps. The
XRS10L120 offers a leading solution for propagation
of high data rate Serial ATA products in a wide variety
of applications. The integration of Serial ATA PHY
links, a variety of digital logic capabilities, rate adjust
FIFOs, integrated low-cost clock oscillator support,
Host and drive port speeds can be mixed and
matched, based upon inherent data rate negotiation
present in the SATA II specifications.
The MDIO bus allows simple configuration of the
XRS10L120 when needed. Receive equalization,
transmit amplitude and pre-emphasis and SSC
control are all configurable via the 2-wire MDIO
interface
To summarize, the port multiplier functionality in the
XRS10L120 allows the system designer to increase
the number of serial ATA connections in an enclosure
that does not have a sufficient number of serial ATA
connections for all of the drives in the enclosure.
STANDARDS COMPLIANCE
The XRS10L120 is compliant with the following
industry specifications:
• Serial ATA, Revision 1.0a
• Serial ATA II: Extensions to Serial ATA 1.0a,
Revision 1.2
• Serial ATA II PHY Electrical Specifications,
Revision 1.0
• Serial ATA II: Port Multiplier, Revision 1.2
• Serial ATA II: Revision 2.6
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
APPLICATIONS
• Serial ATA Enclosures
• Other Serial ATA link replicator applications
• Buffers for externally connected links
• High density storage boxes
• RAID Subsystems
APPLICATION EXAMPLE
The XRS10L120 is ideally suited for use within an external drive enclosure as a means of providing redundant
host access to ensure system availability and reliability, while enabling access to up to four target devices per
XRS10L120. This application is shown in Figure 1. Other applications for the XRS10L120 include use in fixedcontent or network attached storage systems, storage arrays, desktop applications or entry-level servers,
RAID storage or disk-to-disk backup.
FIGURE 1. SYSTEM BLOCK DIAGRAM FOR XRS10L120 IN A DRIVE ENCLOSURE APPLICATION
DRIVE ENCLOSURE
XRS10L 120
PORT MULTIPLIER
SATA
SATA
XRS10L 120
PORT MULTIPLIER
SATA
SATA
2
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
50 RESETB
49 DRACT0
51 NC
52 VSS
53 VSS
VSS
54 VDD
55
56 VDDA
57 VSSA
58 VSS
60 SIRN0
59 SIRP0
SITP0
61 VDD
62
63 SITN0
64 VSS
FIGURE 2. PINOUT OF THE XRS10L120
TCK
1
48
DR AC T 1
TM S
2
47
V SS
TDO
3
46 S O TN 0
TDI
4
45 SO TP 0
TRS T
5
44 V DD
VS S
6
M DC
7
43 S O RN 0
VSS
8
M DIO
9
VS S
10
39 V DD A
V DD
11
38 V SS
VSS
12
37 S O RP 1
V DD
13
36 SO R N 1
XR S 10L120
42 S O R P 0
41 V SS
64-pin Q FN
40 V SS A
26
28
29
30
31
32
RBIAS
VDDA
ANTEST
PWRDNB
VSS
25
CMUREFP
27
24
VSSA
23
XOG
VDDA
3
CMUREFN
21
22
XOD
20
VSSA
19
VDD
33 S O TN 1
SCANMODE
16
18
34 S O TP 1
CLK S TN
VSS
35 V D D
15
17
14
CLKSTP
VSS
V DD
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
2.0 PIN DESCRIPTIONS
TABLE 1: XRS10L120 PIN DESCRIPTIONS
Pin Name
Pin Number
64 QFN
I/O
Type
DESCRIPTION
DATA INTERFACE
SOTP0/SOTN0
45, 46
SOTP1/SOTN1
34, 33
SORP0/SORN0
42, 43
SORP1/SORN1
37, 36
SITP/SITN
62, 63
SIRP/SIRN
O
CML
AC
Coupled
I
Serial ATA Output Transmitters. These ports communicate
from the XRS10L120 to downstream devices
Serial ATA Input Receivers. These ports receive signals from
downstream devices
O
Serial ATA Output Transmitters. These ports communicate
from the XRS10L120 to upstream hosts.
I
Serial ATA Input Receivers. These ports receive signals from
upstream hosts.
59, 60
CLOCK INTERFACE
CMU_REFP/
CMU_REFN
25, 26
XOD
22
XOG
23
CML
AC
Coupled
Reference clock input
O
Analog
Crystal oscillator output
I
Analog
Crystal oscillator input, 1.26V max
MDIO INTERFACE SIGNALS
MDC
7
I
LVCMOS
MDIO clock input, +3.3V LVCMOS
MDIO
9
I/O
LVCMOS
MDIO data port, +3.3V LVCMOS. Open drain
JTAG Interface Signals
TCK
1
I
LVCMOS
JTAG test clock, +3.3V LVCMOS
TDI
4
I
JTAG test data in, +3.3V LVCMOS
TDO
3
O
JTAG test data out, +3.3V LVCMOS. Open drain. If used to
daisy chain JTAG devices, pull up externally using 3.3KOhm
resistor.
TMS
2
I
JTAG mode select, +3.3V LVCMOS
TRST
5
I
JTAG test reset, +3.3V LVCMOS. Pull low externally using
3.3KOhm resistor for normal operation of the device
GENERAL CONTROL AND CONFIGURATION SIGNALS (CMOS)
RBIAS
28
I
Analog
Connection point for calibration termination resistor.
RESETB
50
I
LVCMOS
Active low reset pin, +3.3V LVCMOS.
PWRDNB
31
I
LVCMOS
Active low power down signal for chip, +3.3V LVCMOS.
4
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 1: XRS10L120 PIN DESCRIPTIONS
Pin Name
DRACT[1:0]
Pin Number
64 QFN
I/O
48, 49
O
Type
DESCRIPTION
LVCMOS
Drive activity port for external LED. Active Low, 3.3V LVCMOS, open drain
TEST PINS
ANTEST
30
O
Analog
Analog test pin
CLKSTN/
CLKSTP
16, 17
O
CML
AC
Coupled
Output clock test pin
RESERVED PINS
NC
51
SCANMODE
20
No Connect
I
LVCMOS
For factory use only. connect to ground.
POWER AND GROUND SIGNALS
VDD
11, 13, 15,
19, 35, 44,
54, 61
I
1.2V supply.
VDDA
24, 29, 39, 56
I
1.2V Analog supply.
VSS
6, 8, 10, 12,
14, 18, 32,
38, 41, 47,
52, 53, 55,
58, 64
I
Ground.
VSSA
21, 27, 40, 57
I
Analog Ground.
5
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
3.0
REV. 1.06
FUNCTIONAL DESCRIPTION
A top-level view of the XRS10L120 is shown in Figure 3 outlining the interfaces to the device and the required
support components. The data path can be seen at the top of the device. This includes the output transmit and
input receive paths at the top left, providing the upstream interface to the host, and the two output transmit and
input receive paths at the top right, providing the downstream interface to the target devices. The clocking,
control, and configuration interfaces are shown below the dotted line.
FIGURE 3. XRS10L120 INTERFACES
Serial ATA Upstream
SIT_P/N
SOT_P/N[1:0]
Interface to HBAs
SIR_P/N
SOR_P/N[1:0]
DRACT[1:0]
Control and
Status
Interface
CMU_REF_P/N
Serial ATA Downstream
Interface to Devices
Reference Clock
PS_SIDEBAND_B
XOD
PORTSEL
XOG
Crystal Oscillator I/O
RESETB
PWRDNB
TCK
TDI
MDC
Configuration
Interface
TDO
MDIO
JTAG
Interface
TMS
TRST
VDDA
RBIAS
Calibration Resistor
49.9 Ω ± 0.5%
The XRS10L120 incorporates identical instantiations of a dual-channel Serial ATA II 3 Gbps PHY macro. This
common building block provides a uniform implementation with common characteristics and a common
register map, but provides a functional implementation of independent PHY blocks. Digital logic
implementations of Serial ATA link layer blocks along with port multiplier logic provide the remainder of the data
path within the XRS10L120. In addition, management and control interfaces including an MDIO interface for
6
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
register control, a JTAG interface for boundary scan purposes, and a resistor calibration circuit complete the
device. A block diagram of the XRS10L120 is shown in Figure 4.
FIGURE 4. XRS10L120 BLOCK DIAGRAM
SIR
SIT
SATA II
3G PHY
SATA II
LINK
LAYER
SATA II
LINK
LAYER
SATA II
3G PHY
SOT0
SATA II
LINK
LAYER
SATA II
3G PHY
SOT1
SOR0
RATE
ADJUST
FIFO
PORT
MULTIPLIER
7
SOR1
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
3.1
REV. 1.06
Out Of Band Feature
Each Serial ATA link provides full support for the three Out Of Band (OOB) signals supported by Serial ATA:
COMRESET, COMINIT and COMWAKE. These sequences must be separated by idle periods as shown in
Figure 5. The sequences are comprised of 106.7ns bursts of activity that are interleaved with varying length
stretches of electrical idle. This alternating sequence must be repeated four times to be recognized.
FIGURE 5. COMWAKE AND COMRESET/COMINIT SEQUENCES
106.7ns
COMWAKE
106.7ns
COMRESET
COMINIT
320ns
An example OOB sequence and the resulting burst and idle widths are shown in Figure 6. If the sequence of
burstWidth and idleWidth counts falls within the range specified in the MDIO registers for four consecutive
burst/idle sequences, then the link will assert COMINIT or COMWAKE. This OOB signal will remain asserted
for as long as the corresponding sequence on the input pins continues.
FIGURE 6. EXAMPLE OOB SEQUENCE
rxdP, rxdN
squelchClock
burstWidth
idleWidth
15
15
17
15
17
COMINT = (MaxBurstWidth≥burstWidth≥MinBurstWidth) && (MaxInitWidth≥idleWidth≥MinInitWidth)
COMWAKE = (MaxBurstWidth≥burstWidth≥MinBurstWidth) && (MaxWakeWidth≥idleWidth³MinWakeWidth)
8
17
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
3.2
Power Down Modes
The XRS10L120 features independent support for the 3 transceiver power modes, as follows:
• Active: All parts of the transceiver are active. All power-down signals are de-asserted.
• Partial: In partial mode, the input and output pipelines are shut down, but the PLL and the OOB generation
circuits are active.
• Slumber: In slumber mode, the PLL is also shut down, saving additional power but adding latency on exit.
The XRS10L120 transceiver components (transmitter, receive CDR, PLL, etc.) can be powered down through
MDIO register settings. Please refer to Table 12, “Powerdown Registers (MDIO Devices 1 & 2),” on
page 27
The XRS10L120 does not support Link Power Management as defined in the SATA standard revision 2.6.
3.3
Speed Negotiation
The XRS10L120 will automatically perform speed negotiation with the host and devices in order to verify
whether the second generation Serial ATA 3.0 Gbps data rate is available or whether the system will need to
fall back upon the first generation Serial ATA 1.5 Gbps data rate. Speed negotiation is performed on an
independent basis by each of the dual-channel macros. Speed negotiation is done independently on all host
and device ports by default. MDIO configuration can request a common negotiated speed on the host and
device ports if such a speed exists. To perform speed negotiation with a downstream device, the XRS10L120
will first perform a COMRESET/COMINIT handshake with the device and then performs a calibrate/
COMWAKE handshake. Following receipt of the device COMWAKE signal, the XRS10L120 will continually
send out a D10.2 signal while awaiting receipt of the device ALIGN primitive. Depending on the speed of the
ALIGN primitive, the XRS10L120 will be able to determine the PHY generation of the device, and provide the
appropriate 1.5 Gbps or 3.0 Gbps ALIGN primitive in return to the device, thus completing speed negotiation.
This process is outlined in Figure 7.
FIGURE 7. SERIAL ATA SPEED NEGOTIATION
For speed negotiation with an upstream host, after the COMRESET/COMINIT and COMWAKE handshake is
complete, the XRS10L120 will initially send out an ALIGN primitive at the 2nd generation 3.0 Gbps data rate. If
no confirming 3.0 Gbps ALIGN primitive is received from the host, the XRS10L120 will then step down and
attempt negotiation at the lower 1.5 Gbps data rate.
3.4
Port Multiplier Implementation
9
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
The XRS10L120 provides full support for the functionality outlined in the Serial ATA II Port Multiplier
specification. A Serial ATA II Port Multiplier is a mechanism for one active host connection to communicate
with multiple devices. A Port Multiplier is conceptually a simple multiplexer in which one active host connection
is multiplexed to multiple device connections.
The XRS10L120 uses four bits, known as the PM Port field in all Serial ATA frame types, to route frames
between the selected host and the appropriate device. PM ports 0 through 1 are valid device ports within the 2output XRS10L120, while PM port 15 is designated for communication between the host and the XRS10L120
itself. For host-to-device transactions, the PM Port field is designated by the host in order to specify which
device the frame is intended for. For device-to-host transactions, the XRS10L120 fills in the PM Port field with
the port address of the device that is transmitting the frame.
The PM Port field is defined in the Serial ATA port multiplier specification to be the first 32-bit Dword in the
Frame Information Structure (FIS) for all FIS types, as shown in Figure 8.
FIGURE 8. PORT SELECTION SIGNAL - TRANSMITTED COMRESET SIGNALS
As defined in Serial ATA1.0
3.4.1
PM Port
FIS Type
Transmission from a host to a device
A host indicates the target device for receipt of a transmitted frame by setting the PM Port field in the frame to
the device's port address. When an XRS10L120 receives a frame from the host, it checks the PM Port field in
the frame to determine which port address should be used. If the frame is set for transmission to the control
port (15), the XRS10L120 receives the frame and performs the command or operation requested. If the frame
is designated for a device port, the XRS10L120 obeys the following procedure:
1. The XRS10L120 first determines if the device port is valid. If the device port is not valid, the XRS10L120
will issue a SYNC primitive to the host and terminate reception of the frame.
2. The XRS10L120 determines if the X bit is set in the device port's PSCR[1] (SError) register. If the X bit is
set, the XRS10L120 issues a SYNC primitive to the host and terminates reception of the frame.
3. The XRS10L120 determines if a collision has occurred. A collision occurs when a reception is already in
progress from the device that the host wants to transmit to. If a collision has occurred, the XRS10L120 will
finish receiving the frame from the host and will then issue an R_ERR primitive to the host as the ending
status. The XRS10L120 will then discard the frame, but will not return an R_RDY primitive to the host until
the frame from the affected device port has been transmitted to the host, thus indicating to the host when it
can retry to send the frame. The transmission from the device will proceed as requested, as the device will
always take collision precedence over the host.
4. The XRS10L120 initiates a transfer with the device by issuing an X_RDY primitive to the device. A collision
may occur as the XRS10L120 is issuing the X_RDY to the device if the device has started transmitting an
X_RDY primitive to the XRS10L120, indicating a decision to start a transmission to the host. In this case,
the XRS10L120 will finish receiving the frame from the host and then issue an R_ERR primitive to the host
to indicate an unsuccessful transmission. The transmission from the device will proceed as requested, as
the device will always take collision precedence over the host.
5. After the device issues an R_RDY primitive to the XRS10L120, the XRS10L120 will transmit the frame
from the host to the device. The XRS10L120 will not send an R_OK status primitive to the host until the
device has issued an R_OK primitive to indicate successful frame reception. In this way, the R_OK status
handshake is interlocked from the device to the host.
If an error is detected during any part of the frame transfer, the XRS10L120 will ensure that the error condition
is propagated to the host and the device. If no error occurs during frame transfer, the XRS10L120 will not alter
the contents of the frame, or modify the CRC in any way.
10
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
3.4.2
Transmission from a device to a host
A device indicates a transmit to a host in the same way as would be done if the host and device were attached
directly. This transaction obeys the following procedure:
1. After receiving an X_RDY primitive from the device, the XRS10L120 will determine if the X bit is set in the
device port's PSCR[1] (SError) register. The XRS10L120 will not issue an R_RDY primitive to the device
until this bit is cleared to zero.
2. The XRS10L120 will then receive the frame from the device. The XRS10L120 will fill in the PM Port field
with the port address of the transmitting device. The XRS10L120 will then check the CRC received from
the device, and if valid, it will recalculate the CRC based upon the new PM Port field. If the CRC calculated
from the device is incorrect, the XRS10L120 will corrupt the CRC sent to the host to ensure propagation of
the error condition
3. The XRS10L120 will issue an X_RDY primitive to the host to start the transmission of the frame to the host.
After the host issues an R_RDY primitive to the XRS10L120, the frame from the device, with the updated
CRC, will then be transmitted to the host. The XRS10L120 will not send an R_OK status primitive to the
device until the host has issued an R_OK primitive to indicate successful frame reception. In this way, the
R_OK status handshake will be interlocked from the device to the host.
If an error is detected during any part of the frame transfer, the XRS10L120 will ensure that the error condition
is propagated to the host and the device.
11
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
Clocking
3.5
The XRS10L120 allows the use of either an external reference clock or of a low cost crystal oscillator to act as
a reference clock. Separate device inputs are available for each approach, with full rate reference clock inputs
provided on pins CMU_REFP and CMU_REFN, and crystal oscillator inputs provided on pins XOD and XOG.
Supported data rates and their appropriate PLL divide factors are outlined in Table 2.
TABLE 2: PLL DIVIDE FACTORS
MODE
SYSCLK
/REF
/FB
DINCLK
RXCLK
SERIAL
CLOCK
DATA
RATE
SATA Gen. 2
25MHz
1
60
300MHz
1.5GHz
3.0Gbps*
SATA Gen. 2
75MHz
1
20
300MHz
1.5GHz
3.0Gbps*
SATA Gen. 2
100MHz
2
30
300MHz
1.5GHz
3.0Gbps*
SATA Gen. 2
150MHz
1
10
300MHz
1.5GHz
3.0Gbps*
NOTE: * All link start with 3.0Gbps, then negotiate down to 1.5Gbps for SATA Generation 1 devices.
3.5.1
Spread Spectrum Clocking
The XRS10L120 provides full support for receipt and generation of signals that have been configured for
Spread Spectrum Clocking (SSC) support. The spread technique is implemented by down-spreading the data
rate by 0.5% as a means of reducing EMI. Generation of the down-spread clock is performed within the
XRS10L120. An example of the resultant spectral fundamental frequency before and after SSC can be seen in
Figure 9.
FIGURE 9. SPREAD SPECTRUM CLOCKING
12
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
4.0
ELECTRICAL SPECIFICATIONS
This section contains the electrical specifications for the XRS10L120.
4.1
Serial ATA Specifications
The XRS10L120 electrical transmit and receive specifications are outlined in this section. The XRS10L120 is
fully compliant to the Serial ATA II specification for Gen2i, Gen2x, Gen2m, Gen1i, Gen1x and Gen1m
variations at 3.0 and 1.5 Gbps.
4.1.1
Serial ATA Transmitter
A simplified version of the output circuit and test fixture for each of the 3 Serial ATA transmit output pairs on the
XRS10L120 is shown in Figure 10. The output differential pair is terminated to the supply VDD. The circuit is
designed to be AC coupled.
FIGURE 10. SERIAL ATA EQUIVALENT OUTPUT CIRCUIT
The XRS10L120 Serial ATA outputs include a simple one-tap equalizer, that is useful in driving longer printed
circuit traces and is a required component in second generation Serial ATA PHYs. This equalizer preemphasizes the output signal whenever there is a data transition. The amount of pre-emphasis can vary
between 0 and 45.5%, and is configured via MDIO register settings. Note that pre-emphasis doesn't increase
the overall swing, but instead reduces the output amplitude when there is no transition.
13
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
FIGURE 11. EFFECTS OF TRANSMIT PRE-EMPHASIS
The overall swing level can also be modified via MDIO register settings. The XRS10L120 transmit mask is
shown in Figure 12.
FIGURE 12. TRANSMIT EYE MASK FOR SERIAL ATA OUTPUT
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EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
4.1.2
Serial ATA Receiver
An equivalent circuit for the XRS10L120 Serial ATA inputs is shown in Figure 13. The device receiver mask is
shown in Figure 14. This circuit is designed to be AC coupled. The termination resistors are not connected
during power-up
FIGURE 13. SERIAL ATA EQUIVALENT INPUT CIRCUIT
FIGURE 14. RECEIVE EYE MASK FOR SERIAL ATA INPUT
15
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 3: SERIAL ATA LINK SPECIFICATIONS
NAME
MIN.
NOM
MAX
UNITS
Bit Time
670
-
333
ps
JXR1
Input Jitter Tolerance Mask at signal crossover
0.32
-
-
UI
JXR1,DJ
Deterministic jitter tolerance at signal crossover
0.18
-
-
UI
Output jitter mask at signal crossover
-
-
0.15
UI
Deterministic output jitter at signal crossover
-
-
0.07
UI
Input signal rise/fall times (20% - 80%)
0.2
-
0.46
UI
tQR/tQF
Output signal rise/fall times (20% - 80%)
0.2
-
0.41
UI
tTOL,RX1
RX to sysclock frequency offset tolerance
-5350
0
350
ppm
Input swing, differential peak-peak
175
-
1600
mV
Output swing, differential peak-peak
800
-
1200
mV
VIN,IDLE
No swing detection threshold
65
120
155
mV
RIN,DIFF
Differential mode input resistance
85
100
115
Ω
RIN,CM3
Common mode input resistance
40
50
60
Ω
RIN,OFF
Common mode input resistance, no power
200
-
-
kΩ
RIN,XS
Output termination resistance
40
50
60
Ω
S11,IN,DIFF
Differential input return loss, 50MHz - 1.5GHz
12
-
-
dB
S11,IN,CM
Common mode input return loss 50MHz-1.5GHz
6
-
-
dB
S22,OUT,DIFF Differential output return loss 50MHz-1.5GHz
12
-
-
dB
S22,OUT,CM
6
-
-
dB
tBIT,XS
JXT1
JXT1,DJ
tR/tF
VIN
VSW2
DESCRIPTION
Common mode output return loss 50MHz-1.5GHz
tS,REG
Setup time for register port
1.5
-
-
ns
tH,REG
Hold time for register port
1.5
-
-
ns
tQ,REG
Clock to Q time for register port
0
-
2
ns
tCYC,REG
Register port clock cycle time
10
-
-
ns
tHI,REG
R register port clock high time
4
-
-
ns
tLO,REG
Register port clock low time
4
-
-
ns
tRF,REG
Register port input rise/fall time
-
-
0.5
ns
NOTES:
1.
This value includes 0.5% downspread Spread Spectrum clocking, plus 350ppm tolerance around the center
frequency.
2.
This is measured at the package ball and does not include any board or connector loss.
3.
This value can be as low as 5Ω during power on.
16
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
4.2
CMOS Interface
AC and DC specifications for the CMOS inputs and outputs are listed in Table 4. Since all these signals are
asynchronous, there are no setup or hold times defined. The CMOS pins are defined in the General Control
and Configuration portion of Table 1 in Section 3, "Pin Descriptions".
TABLE 4: CMOS I/O SPECIFICATIONS
NAME
tDR/tDF,CMOS
DESCRIPTION
CMOS input signal rise/fall times (20% - 80%)
tQR/tQF,CMOS1 CMOS output signal rise/fall times (20% - 80%)
MIN
NOM
MAX
UNITS
0.2
-
5
ns
0.2
-
5
ns
VIL,CMOS
CMOS input low voltage
-0.3
0
0.8
V
VIH,CMOS
CMOS input high voltage
1.7
3.3
3.6
V
VOL,CMOS
CMOS output low voltage
-0.3
-
0.4
V
VPULLUP
Open Drain Pull-up Voltage
2.3
3.6
V
IOL,CMOS
Output current for VOL = 0.4V
10
-
20
mA
dIOL/dt,CMOS
Output current rate of change
-10
-
10
mA/ns
LI,CMOS
CMOS I/O inductance
-
-
8
nH
CI,CMOS
CMOS I/O capacitance
-
-
5
pF
150
uA
ILEAKAGE2
CMOS I/O Leakage Current
NOTE: .1. This value is measured driving a load of 20pF.
NOTE: .2. This values is measured at 2.5 VDC.
4.3
MDIO Interface
The Management Data Input/Output (MDIO) port complies with Clause 45 of the IEEE 802.3ae specification. A
representative MDIO driver/receiver is shown in Figure 15. MDIO uses an open drain driver with a pullup
resistor.
17
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
FIGURE 15. REPRESENTATIVE MDIO CIRCUIT
2.5V/3.3V
Pin
To other MDIO Devices
Open Drain
Driver
Representative MDIO Read and Write waveforms are shown in Figure 16. The XRS10L120 samples MDIO on
the rising edge of MDC for input and drives MDIO after the rising edge of MDC for output. Note that setup,
hold, and output timings are defined from the maximum vIL and minimum VIH levels.
FIGURE 16. MDIO INPUT AND OUTPUT WAVEFORMS
Values for MDIO parameters are shown in Table 5
18
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 5: MDIO DC AND AC CHARACTERISTICS
NAME
DESCRIPTION
MIN
NOM
MAX
UNITS
tCYCLE,MDIO
MDC cycle time
400
-
-
ns
tLOW,MDC
MDC low time
160
-
-
ns
tHIGH,MDC
MDC high time
160
-
-
ns
tS,MDIO1
MDIO input to MDC setup time
10
-
-
ns
tH,MDIO2
MDC to MDIO input hold time
10
-
-
ns
tQ,MDIO3
MDC to MDIO output time
0
-
150
ns
tDR/tDF,MDIO
MDIO input signal rise/fall times (20% - 80%)
0.2
-
100
ns
tQR/tQF,MDIO4
MDIO output signal rise/fall times (20% - 80%)
0.2
-
80
ns
VIL,MDIO
MDIO input low voltage
-0.3
0
0.8
V
VIH,MDIO
MDIO input high voltage
1.7
3.3
3.6
V
VOL,MDIO4
MDIO output low voltage
-0.3
0
0.4
V
VPULLUP
Open Drain Pull-up Voltage
2.3
3.6
V
IOL,MDIO
MDIO Output current for VOL = 0.4V
10
-
20
mA
dIOL/dt,MDIO
MDIO Output current rate of change
-10
-
10
mA/ns
LI,MDIO
MDIO input inductance
-
-
8
nH
CI,MDIO
MDIO input capacitance
-
-
5
pF
NOTES:
1.
Measured from minimum MDIO VIH to maximum MDC VIL for MDIO rising edge.
2.
Measured from minimum MDC VIH to maximum MDIO VIL for MDIO rising edge.
Measured from maximum MDIO VIL to maximum MDC VIL for MDIO falling edge.
Measured from minimum MDC VIH to minimum MDIO VIH for MDIO falling edge.
3.
Measured from minimum MDC VIH to maximum MDIO VIL for MDIO rising edge and MDC rising edge.
4.
Measured from minimum MDC VIH to minimum MDIO VIH for MDIO falling edge and MDC rising edge.
Measured from maximum MDC VIL to maximum MDIO VIL for MDIO rising edge and MDC falling edge.
Measured from maximum MDC VIL to minimum MDIO VIH for MDIO falling edge and MDC falling edge.
Measured driving a load of 470pF.
TABLE 6: OPERATING CONDITIONS
Name
Min
Nom
Max
Units
Ambient temperature under bias
-40
25
85
°C
VDD
Core power supply voltage
1.14
1.2
1.26
V
IDD
Core power supply current
-
300
400
mA
TA
Description
19
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 6: OPERATING CONDITIONS
Name
Description
Min
Nom
Max
Units
VESD1
Electrostatic discharge tolerance, Human Body Model Any pin with respect to any other pin except VDDA pins
-1400
1400
V
VESD2
Electrostatic discharge tolerance, Human Body Model Any pin with respect to VDDA pins
-300
300
V
θJA
Junction-to-ambient thermal resistance (64 QFN)
20
26.00
0
C/W
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
5.0 REGISTERS DESCRIPTION
The XRS10L120 provides a variety of registers for the purpose of device configuration, testing and monitoring.
These registers are accessed through the MDIO interface, outlined in “Section 4.3, MDIO Interface” on
page 17. Operational registers available to the customer are given below. Note that all other addres space
should be left unmodified in order to ensure proper behaviour of the device.
5.1
Register Overview
The XRS10L120 port address is hardwired to 0; this field should be set to 0 in all packets.The XRS10L120
contains three identical instantiations of a dual Serial ATA PHY macro. A common set of registers exists within
each of these macros, and are outlined in “Section 5.2, Macro Registers” on page 22. MDIO device
designations 1-3 are used for each of these three macros as shown in Table 7. Registers relating to the
XRS10L120 as a whole are outlined in “Section 5.3, XRS10L120 Device Generic Registers” on page 27
and make use of MDIO device 0.
TABLE 7: MDIO DEVICE DESIGNATIONS
MDIO DEVICE DESIGNATION
MACRO
RELEVANT PINS
0
XRS10L120 Device Generic Registers
N/A
1
Serial ATA Host Interface Macro (Lane 0)
SI
2
Serial ATA Devoce Interface Macro 0
SO0, SO1
The XRS10L120 registers are arranged as 8-bit fields with 8-bit addresses. These are mapped into the 16-bit
MDIO address and data fields by setting the most significant byte of each to be 0. An example mapping from a
macro address/data combination to an MDIO address & data combination is shown in Table 8.
TABLE 8: MDIO ADDRESSING
MACRO ADDRESS
MACRO DATA
MDIO ADDRESS
MDIO DATA
0x40
abcde
0x0040
00000000000abcde
NOTE: The unused upper 3 bits in FBDIV are also set to 0 during MDIO writes and are undefined during MDIO reads.
In the description of each register field, there is an entry describing its read/write status. This may fall into one
of the following categories:
• R/W- register field is read/write
• RO - register field is read only
• LL - Latching Low - Used with bits that monitor some state internal to the XRS10L120. When the condition
for the bit to go low is reached, the bit stays low until the next time it is read. Once it is read, its value reverts
to the cur-rent state of the condition it monitors.
• LH - Latching High - When the condition for the bit to go high is reached, the bit stays high until the next time
it is read. Once it is read, its value reverts to the current state of the condition it monitors.
• SC - When an SC bit is set, some action is initiated; once the action is complete, the bit is cleared.
21
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
5.2
REV. 1.06
Macro Registers
The registers outlined in this section are common to each of the two Serial ATA dual PHY macros as described
in the previous section. As such, each listed register is present in each of the 1 and 2 MDIO register spaces,
and will perform the stated function on the specified Serial ATA lane.
The registers within each dual PHY macro are split into the following sections:
Transmit/Receive lane 0 registers:
Address range 000*****
Transmit/Receive lane 1 registers:
Address range 001*****
PLL registers:
Address range 010*****
Bias generator registers:
Address range 011*****
TABLE 9: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2)
ADDRESS
HEX
N.0000
N.0020
N.0001
N.0021
BIT(S)
NAME
R/W
DEFAULT
7
Reserved
R/W
0
DO NOT MODIFY
6
SATAPCIEXB_G1
R/W
0
Tx output swing booster bit (Gen 1)
0 = boost swing by 15%
1 = nominal swing
5:1
Reserved
R/W
00001
0
SATAPCIEXB_G2
R/W
0
7:3
Reserved
R/W
00000
2:0
Transmit_Eq0[2:0]
Transmit_Eq1[2:0]
R/W
011
22
DESCRPTION
DO NOT MODIFY
Tx output swing booster bit (Gen 2)
0 = boost swing by 15%
1 = nominal swing
DO NOT MODIFY
Transmit pre-emphasis control
000 = 0% transmit preemphasis
001 = 6.5% transmit preemphasis
010 = 13% transmit preemphasis
011 = 19.5% transmit preemphasis
100 = 26% transmit preemphasis
101 = 32.5% transmit preemphasis
110 = 39% transmit preemphasis
111 = 45.5% transmit preemphasis
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 9: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2)
ADDRESS
HEX
BIT(S)
NAME
R/W
DEFAULT
N.0002
N.0022
7:6
7:6
mscProg0[1:0]
mscProg1[1:0]
RW
01
Receive equalization control – boost at 1.5GHz
00 = Lowest boost level
01 = 2nd boost level
10 = 3rd boost level
11 = Highest boost level
5:3
5:3
Beacon_Swing0[2:0]
Beacon_Swing1[2:0]
R/W
100
Transmit swing size for OOB Signals
000 = 800mV
001 = 700mV
010 = 600mV
011 = 500mV
100 = 400mV
101 = 300mV
110 = 200mV
111 = 0mV
2:0
2:0
Output_Swing0[2:0]
Output_Swing1[2:0]
R/W
100
Transmit swing size in normal operation
000 = 800mV
001 = 700mV
010 = 600mV
011 = 500mV
100 = 400mV
101 = 300mV
110 =200mV
111 = 0mV
7
enEqB
R/W
0
6:0
Reserved
RW
7
Reserved
RO
-
6:4
sysclk25divsel0[2:0]
sysclk25divsel1[2:0]
RW
000
Divider selection for sysclk-> sysclk25
000 = divide by 1 (sysclk is 25MHz)
001 = divide by 2 (sysclk is 50MHz)
010 = divide by 3 (sysclk is 75MHz)
011 = divide by 4 (sysclk is 100MHz)
100 = divide by 5 (sysclk is 125MHz)
101 = divide by 6 (sysclk is 150MHz)
110 = divide by 10 (sysclk is 250MHz)
111 = divide by 12 (sysclk is 300MHz)
3:0
Reserved
RW
0x5
DO NOT MODIFY
N.0003
N.0023
N.0015
N.0035
DESCRPTION
Enable receive equalization
0 = enable equalization
1 = disable equalization
0010000 DO NOT MODIFY
23
Reserved
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 9: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2)
ADDRESS
HEX
N.0018
N.0038
BIT(S)
NAME
R/W
DEFAULT
7:3
Reserved
RW
00100
2:0
txbiasbuffsela0[2:0]
txbiasbuffsela1[2:0]
RW
100
24
DESCRPTION
DO NOT MODIFY
Tx Predriver swing size in normal operation
000 = 800mV
001 = 700mV
010 = 600mV
011 = 500mV
100 = 400mV (sata default)
101 = 300mV
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 10: PLL CONFIGURATION (MDIO DEVICE 1, 2)
ADDRESS
HEX
BIT(S)
NAME
TYPE
DEFAULT
N.0040
7:6
Reserved
RO
-
5:0
FBDIV[5:0]
RW
101101
7:6
Reserved
RO
-
5:0
REFDIV[5:0]
RW
010000
7:6
Reserved
RO
-
5:0
SSCMax
RW
000000
N.0041
N.0044
25
DESCRIPTION
Reserved
Divide value for feedback clock
110000 = divide by 5
100000 = divide by 10
100001 = divide by 15
100010 = divide by 20
100011 = divide by 25
100101 = divide by 30
100111 = divide by 50
101101 = divide by 60 (default for 25MHz Ref))
Other - reserved
Reserved
Divide values for system clock
010000 = divide by 1 (default for 25MHz Ref))
000000 = divide by 2
000001 = divide by 3
000010 = divide by 4
000011 = divide by 5
000101 = divide by 6
000110 = divide by 8
000111 = divide by 10
001101 = divide by 12
001110 = divide by 16
001111 = divide by 20
Others - reserved
Reserved
Maximum value for spread (set to 45 [0x2D] when
SSCBypass is set to "0")
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 10: PLL CONFIGURATION (MDIO DEVICE 1, 2)
ADDRESS
HEX
N.0045
NOTE 1
BIT(S)
NAME
TYPE
DEFAULT
DESCRIPTION
7:5
Reserved
RO
0
Reserved
4
SSCmode
R/W
0
Selects position of spreading interpolator
0 = Interpolator in feedback path
1 = Interpolator in feedforward path
Set to ’1’ when SSCBypass = ’0’
3
Reserved
R/W
0
DO NOT MODIFY
2
SSCInvert
R/W
0
Inverting SSC profile - Setting for downspread per
SATA spec
Set to ’0’ when SSCmode = ’0’
Set to ’1’ when SSCmode = ’1’
1
Reserved
R/W
0
DO NOT MODIFY
0
SSCBypass
R/W
1
Bypass the saw generator and pulse density modulator and get increment from SSCMax (set SSCMax
to 45 [0x2D] when SSCBypass is set to 0)
NOTE: 1) In order to enable SSC generation, set register N.0044 to 0x2D, N.0045 to 0x14 and then reset the PLL by
writing register 0.0004 to 0x0 then 0xF.
TABLE 11: BIAS GENERATOR CONFIGURATION REGISTERS (MDIO DEVICES 1 & 2)
ADDRESS
HEX
BIT(S)
NAME
TYPE
RESET VALUE
N.0064
7:4
pr100Tx[3:0]
RW
0x0
Transmit pre-driver current bias
1010=50uA
0010=75uA
0000=100uA
0001=125uA
1100=150uA
0111=175uA
1111=200uA
3:0
Reserved
RW
0x0
DO NOT MODIFY
7:4
Reserved
RW
0x0
DO NOT MODIFY
3:0
prcal100Tx[3:0]
RW
0x0
Transmit driver current bias
1010=50uA
0010=75uA
0000=100uA
0001=125uA
1100=150uA
0111=175uA
1111=200uA
N.0065
26
DESCRIPTION
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 12: POWERDOWN REGISTERS (MDIO DEVICES 1 & 2)
ADDRESS
HEX
1.0080
2.0080
1.0081
2.0081
5.3
BIT(S)
NAME
TYPE
RESET VALUE
DESCRIPTION
7:6
SIpwrdnDetB[1:0]
SO01pwrdnDetB[1:0]
RW
11
Powers down the signal detector and COM*
circuits
1 = normal operation
0 = power down
5:4
SIpwrdnRxB[1:0]
SO01pwrdnRxB[1:0]
RW
11
Powers down the receivers and CDR
1 = normal operation
0 = power down
3:2
SIpwrdnTxDrvB[1:0]
SO01pwrdnTxDrvB[1:0]
RW
11
Powers down the transmitter
1 = normal operation
0 = power down
1:0
SIpwrdnTxB[1:0]
SO01pwrdnTxB[1:0]
RW
11
Powers down the transmit pipes and clock
1 = normal operation
0 = power down
7:2
Reserved
RO
-
Reserved
1
SIpwrdnBiasGen
SO01pwrdnBiasGen
RW
0
Powers down the bandgap.
1 = power down
0 = normal operation
0
SIpwrdnPLLB
SO01pwrdnPLLB
RW
1
Powers down the PLL
1 = normal operation
0 = power down
XRS10L120 Device Generic Registers
This section outlines generic registers relating to the XRS10L120 as a whole. These registers are accessed
through MDIO device 0.
TABLE 13: RESET CONTROL SIGNALS
ADDRESS
HEX
BIT(S)
NAME
TYPE
RESET VALUE
DESCRIPTION
0.0004
3:0
resetPLLB_reg[3:0]
RW
0x0F
Resets the PLL portion of the macros
0x00 = PLL reset
0x0F = clears PLL reset
0.0030
7:0
revision_id[7:0]
R/O
0x01
Deivice Revision ID
0.0031
7:0
device_id [15:8]
R/O
0x83
Device ID MSB
0.0032
7:0
device_id [7:0
R/O
0x04
Device ID LSB
27
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 14: PORT MULTIPLIER SATA STANDARD REGISTERS
REGISTER
BIT(S)
NAME
TYPE
DEFAULT
VALUE
GSCR(0)
Product
Identifier
31 - 16
Device ID
R/O
0x8304
Device ID allocated by the vendor.
15 - 0
Vendor ID
R/O
0x13A8
Vendor ID allocated by the PCI-SIG of the vendor
that produced the Port Multiplier.
GSCR(1)
Revision
Information
31 - 16
Reserved
R/O
0x0000
31-16 Reserved
15 - 8
REV_LEV
R/O
0x01
15-8 Revision level of the Port Multiplier.
7:4
Reserved
R/O
0x0
7-4 Reserved
3
PM_1,2
R/O
1
1=Supports Port Multiplier specification 1.2.
2
PM_1.1
R/O
1
1=Supports Port Multiplier specification 1.1.
1
PM_1.0
R/O
1
1=Supports Port Multiplier specification 1.0.
0
Reserved
R/O
0
Reserved
7:4
Reserved
R/O
0x0
Reserved
3-0
DEV_FAN_OUT_
PORTS
R/O
0x2
Number of exposed device fan-out ports.
31 - 15
Reserved
R/O
0x0
Reserved
14
OR_PORT-14
R/O
0x0
Reserved
13
OR_PORT-13
R/O
Reserved
12
OR_PORT-12
R/O
Reserved
11
OR_PORT-11
R/O
Reserved
10
OR_PORT-10
R/O
Reserved
9
OR_PORT-9
R/O
Reserved
8
OR_PORT-8
R/O
Reserved
7
OR_PORT-7
R/O
Reserved
6
OR_PORT-6
R/O
Reserved
5
OR_PORT-5
R/O
Reserved
4
OR_PORT-4
R/O
Reserved
3
OR_PORT-3
R/O
OR of selectable bits in Port 3 PSCR[1] (SError)
2
OR_PORT-2
R/O
OR of selectable bits in Port 2 PSCR[1] (SError)
1
OR_PORT-1
R/O
OR of selectable bits in Port 1 PSCR[1] (SError)
0
OR_PORT-0
R/O
OR of selectable bits in Port 0 PSCR[1] (SError)
31 - 0
ERR_INFO_EN
R/O
GSCR(2)
Port
Information
GSCR(32)
Error
Information
GSCR(33)
Error Information Bit
Enable
0x0
28
DESCRIPTION
If set, bit is enabled for use in GSCR[32]
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 14: PORT MULTIPLIER SATA STANDARD REGISTERS
REGISTER
BIT(S)
NAME
TYPE
DEFAULT
VALUE
GSCR(64)
Port Multiplier Revision 1.X
Features
Support
31 - 5
Reserved
R/O
0x0
4
PHY_EVENT
R/O
0
1 = Supports Phy event counters
3
ASYNC
R/O
1
1 = Supports asynchronous notification
2
SSC
R/O
0
1 = Supports dynamic SSC transmit enable
1
PMREQP
R/O
1
1 = Supports issuing PMREQP to host
0
BIST
R/O
0
1 = Supports BIST
31 - 4
Reserved
R/O
0x0
3
ASYNC_EN
R/W
0
1 = Asynchronous notification enabled
2
SSC_EN
R/W
0
1 = Dynamic SSC transmit is enabled
1
PMREQP_EN
R/W
0
1 = Issuing PMREQP to host is enabled
0
BIST_EN
R/W
0
1 = BIST support is enabled
GSCR(96)
Port Multiplier Revision 1.X
Features
Enable
29
DESCRIPTION
Reserved
Resaerved
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 15: SATA STANDARD REGISTERS - DEVICE PORT (0 TO 1) - STATUS AND CONTROL
NOTE: Registers designated as WC are write clear. In order to clear a particular bit or bit field within a WC designated
register, write a ‘1’ to that bit or bit field.
DEFAULT
VALUE
REGISTER
BIT(S)
NAME
TYPE
DESCRIPTION
PSCR(0)
(SStatus)
31 - 12
Reserved
R/O
Reserved
11 - 8
IPM
R/O
The IPM value indicates the current interface power management state
0000b = Device not present or communication not established
0001b = Interface in active state
0010b= Interface in Partial power management state
0110b = Interface in Slumber power management state
All other values reserved
7 -4
SPD
R/O
The SPD value indicates the negotiated interface communication speed established
0000b = No negotiated speed (device not present or communication not established)
0001b = Generation 1 communication rate negotiated
0010b = Generation 2 communication rate negotiated
All other values reserved
3-0
DET
R/O
The DET value indicates the interface device detection and
Phy state.
0000b = No device detected and Phy communication not
established
0001b = Device presence detected but Phy communication
not established
0011b = Device presence detected and Phy communication
established
0100b = Phy in offline mode as a result of the interface being
disabled or running in a BIST loopback mode
All other values reserved
PSCR(1)
(SError)
31 - 16
DIAG
R/WC
See description below
15 - 0
ERR
R/WC
See description below
PSCR(2)
(SControl)
31 - 19
Reserved
R/O
Reserved All reserved fields shall be cleared to zero.
20 - 16
PMP
R/W
See description below
15 - 12
SPM
R/W
See description below
11 - 8
IPM
R/W
See description below
7-4
SPD
R/W
See description below
3-0
DET
R/W
See description below
30
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
SError register SCR(1) The Serial ATA interface Error register - SError - is a 32-bit register that conveys supplemental Interface error
information to complement the error information available in the Shadow Register Block Error register. The
register represents all the detected errors accumulated since the last time the SError register was cleared
(whether recovered by the interface of not). Set bits in the error register are explicitly cleared by a write
operation to the SError register, or a reset operation. The value written to clear set error bits shall have 1’s
encoded in the bit positions corresponding to the bits that are to be cleared. Host software should clear the
Interface SError register at appropriate checkpoints in order to best isolate error conditions and the commands
they impact.
Bits [31:16] DIAG
The DIAG field contains diagnostic error information for use by diagnostic software in validating correct
operation or isolating failure modes. The field is bit significant as defined in the following figure.
DIAG
R
R
R
R
A
X
F
T
S
H
C
D
B
W
I
N
A
Port Selector presence detected: This bit is set to one when COMWAKE is received while the host is
in state HP2: HR_AwaitCOMINIT. On power-up reset this bit is cleared to zero. The bit is cleared to zero when
the host writes a one to this bit location.
B
10b to 8b Decode error: When set to a one, this bit indicates that one or more 10b to 8b decoding
errors occurred since the bit was last cleared to zero.
C
CRC Error: When set to one, this bit indicates that one or more CRC errors occurred with the Link
layer since the bit was last cleared to zero.
D
Disparity Error: When set to one, this bit indicates that incorrect disparity was detected one or more
times since the last time the bit was cleared to zero.
F
Unrecognized FIS type: When set to one, this bit indicates that since the bit was last cleared one or
more FISes were received by the Transport layer with good CRC, but had atype field that was not recognized.
I
Phy Internal Error: When set to one, this bit indicates that the Phy detected some internal error since
the last time this bit was cleared to zero.
N
PHYRDY change: When set to one, this bit indicates that the PHYRDY signal changed state since the
last time this bit was cleared to zero.
H
Handshake error: When set to one, this bit indicates that one or more R_ERRPhandshake response
was received in response to frame transmission. Such errors may be the result of a CRC error detected by the
recipient, a disparity or 10b/8b decoding error, or other error condition leading to a negative handshake on a
transmitted frame.
R
Reserved bit for future use: Shall be cleared to zero.
S
Link Sequence Error: When set to one, this bit indicates that one or more Link state machine error
conditions was encountered since the last time this bit was cleared to zero. The Link layer state machine
defines the conditions under which the link layer detects an erroneous transition.
T
Transport state transition error: When set to one, this bit indicates that an error has occurred in the
transition from one state to another within the Transport layer since the last time this bit was cleared to zero.
W
COMWAKE Detected: When set to one this bit indicates that a COMWAKE signal was detected by the
Phy since the last time this bit was cleared to zero.
X
Exchanged: When set to one this bit indicates that device presence has changed since the last time
this bit was cleared to zero. The means by which the implementation determines that the device presence has
changed is vendor specific. This bit may be set to one anytime a Phy reset initialization sequence occurs as
determined by reception of the COMINIT signal whether in response to a new device being inserted, in
response to a COMRESET having been issued, or in response to power-up.
31
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
Bits [15:0] ERR
The ERR field contains error information for use by host software in determining the appropriate response to
the error condition. The field is bit significant as defined in the following figure.
ERR
R
R
R
R
E
P
C
T
R
R
R
R
R
R
M
I
C
Non-recovered persistent communication or data integrity error: A communication error that was not
recovered occurred that is expected to be persistent. Since the error condition is expected to be persistent the
operation need not be retried by host software. Persistent communications errors may arise from faulty
interconnect with the device, from adevice that has been removed or has failed, or a number of other causes.
E
Internal error: The host bus adapter experienced an internal error that caused the operation to fail and
may have put the host bus adapter into an error state. Host software should reset the interface before re-trying
the operation. If the condition persists, the host bus adapter may suffer from a design issue rendering it
incompatible with the attached device.
I
Recovered data integrity error: A data integrity error occurred that was recovered by the interface
through a retry operation or other recovery action. This may arise from a noise burst in the transmission, a
voltage supply variation, or from other causes. No action is required by host software since the operation
ultimately succeeded, however, host software may elect to track such recovered errors in order to gauge
overall communications integrity and potentially step down the negotiated communication speed.
M
Recovered communications error: Communications between the device and host was temporarily lost
but was re-established. This may arise from a device temporarily being removed, from a temporary loss of Phy
synchronization, or from other causes and may be derived from the PHYRDYn signal between the Phy and
Link layers. No action is required by the host software since the operation ultimately succeeded, however, host
software may elect to track such recovered errors in order to gauge overall communications integrity and
potentially step down the negotiated communication speed.
P
Protocol error: A violation of the Serial ATA protocol was detected. This may arise from invalid or
poorly formed FISes being received, from invalid state transitions, or from other causes. Host software should
reset the interface and retry the corresponding operation. If such an error persists, the attached device may
have a design issue rendering it incompatible with the host bus adapter.
R
Reserved bit for future use: Shall be cleared to zero.
T
Non-recovered transient data integrity error: A data integrity error occurred that was not recovered by
the interface. Since the error condition is not expected to be persistent the operation should be retried by host
software.
SControl register SCR(2)
The Serial ATA interface Control register - SControl - is a 32-bit read-write register that provides the interface
by which software controls Serial ATA interface capabilities. Writes to the SControl register result in an action
being taken by the host adapter or interface. Reads from the register return the last value written to it.
Bits [19:16] PMP
The Port Multiplier Port (PMP) field represents the 4-bit value to be placed in the PM Port field of all transmitted
FISes. This field is ‘0000’ upon power-up. This field is optional and an HBA implementation may choose to
ignore this field if the FIS to be transmitted is constructed via an alternative method.
Bits [15:12] SPM
The Select Power Management (SPM) field is used to select a power management state. Anon-zero value
written to this field shall cause the power management state specified to be initiated. A value written to this
field is treated as a one-shot. This field shall be read as 0000b.
■
0000b = No power management state transition requested
32
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
■
0001b = Transition to the Partial power management state initiated
■
0010b = Transition to the Slumber power management state initiated
■
0100b = Transition to the active power management state initiated
■
All other values reserved
Bits [11:8] IPM
The IPM field represents the enabled interface power management states that may be invoked via the Serial
ATA interface power management capabilities
■
0000b = No interface power management state restrictions
■
0001b = Transitions to the Partial power management state disabled
■
0010b = Transitions to the Slumber power management state disabled
■
0011b = Transitions to both the Partial and Slumber power management states disabled
■
All other values reserved
Bits [7:4]SPD
The SPD field represents the highest allowed communication speed the interface is allowed to negotiate when
interface communication speed is established
■
0000b = No speed negotiation restrictions
■
0001b = Limit speed negotiation to a rate not greater than Gen 1 communication rate
■
0010b = Limit speed negotiation to a rate not greater than Gen 2 communication rate
■
All other values reserved
Bits [3:0] DET
The DET field controls the host adapter device detection and interface initialization.
■
0000b = No device detection or initialization action requested
■
0001b = Perform interface communication initialization sequence to establish communication. This is
functionally equivalent to a hard reset and results in the interface being reset and communications
reinitialized. Upon a write to the SControl register that sets the DET field to 0001b, the host interface
shall transition to the HP1: HR_Reset state and shall remain in that state until the DET field is set to a
value other than 0001b, by a subsequent write to the SControl register.
■
0100b = Disable the Serial ATA interface and put Phy in offline mode.
■
All other values reserved
33
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
6.0 ORDERING INFORMATION
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
XRS10L120IL-F
64 Pin QFN (Lead Free)
-40°C to +85°C
XRS10L120IL
64 Pin QFN
-40°C to +85°C
34
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
64 LEAD QUAD FLAT NO LEAD
(9 mm x 9 mm x 0.9mm, 0.50 pitch QFN, Small Thermal Pad)
Rev. 1.00
Note: the actual center pad is
Metallic.
Note: The control dimension is in millimeter.
SYMBOL
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
A
0.031
0.039
0.80
1.00
A1
0.000
0.002
0.00
0.05
A3
0.006
0.010
0.15
0.25
D
0.350
0.358
8.90
9.10
D2
0.187
0.199
4.75
5.05
b
0.007
0.012
0.18
0.30
e
0.0197 BSC
0.50 BSC
L
0.014
0.018
0.35
0.45
k
0.008
-
0.20
-
35
EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
REVISION HISTORY
REV #
DATE
DESCRIPTION OF CHANGES
1.00
November 2007
1.01
January 2008
Corrected JTAG TRST, TDO pin desc., part ordering info.
1.02
February 2008
Corrected missing package / pinout diagrams.
1.03
March 2008
Revised to operational registers.
1.04
August 2008
Updated the ESD ratings and Link Power Management support.
1.05
February 2009
1.06
June 2009
Released
Updated transceiver power modes section, figure 4
Remove 100 pin LQFP Package
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2008 EXAR Corporation
Datasheet June 2009.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
36