EXAR XRT83VL38

XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JUNE 2009
REV. 1.0.0
GENERAL DESCRIPTION
The XRT83VL38 is a fully integrated Octal (eight
channel) long-haul and short-haul line interface unit
for T1 (1.544Mbps) 100, E1 (2.048Mbps) 75 or
120J1 110or BITS Timing applications.
In long-haul applications the XRT83VL38 accepts
signals that have been attenuated from 0 to 36dB at
772kHz in T1 mode (equivalent of 0 to 6000 feet of
cable loss) or 0 to 43dB at 1024kHz in E1 mode.
In T1 applications, the XRT83VL38 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements as
well as for Channel Service Units (CSU) Line Build
Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB
as required by FCC rules. It also provides
programmable transmit pulse generators for each
channel that can be used for output pulse shaping
allowing performance improvement over a wide
variety of conditions (The arbitrary pulse generators
are available in both T1 and E1 modes).
The XRT83VL38 provides both a parallel/serial Host
microprocessor interface as well as a Hardware
mode for programming and control.
Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. Two on-chip
crystal-less jitter attenuators with a 32 or 64 bit FIFO
can be placed in the receive and the transmit paths
with loop bandwidths of less than 3Hz. The
XRT83VL38 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75
100 110 and 120 for both transmitter and
receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing for redundancy applications The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master.
APPLICATIONS
 BITS Timing
 T1 Digital Cross-Connects (DSX-1)
 ISDN Primary Rate Interface
 CSU/DSU E1/T1/J1 Interface
 T1/E1/J1 LAN/WAN Routers
 Public switching Systems and PBX Interfaces
 T1/E1/J1 Multiplexer and Channel Banks
Features (See Page 2)
FIGURE 1. BLOCK DIAGRAM OF THE XRT83VL38 T1/E1/J1 LIU (HOST MODE)
MCLKE1
MCLKT1
MCLKOUT
MASTER CLOCK SYNTHESIZER
One of Eight channels, CHANNEL_n - (n= 0:7)
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TAOS
ENABLE
TX/RX JITTER
ATTENUATOR
DRIVE
MONITOR
DFM
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
DMO_n
TTIP_n
LINE
DRIVER
TRING_n
QRSS ENABLE
REMOTE
LOOPBACK
QRSS
DETECTOR
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
HDB3/
B8ZS
DECODER
NETWORK
LOOP
DETECTOR
NLCD ENABLE
JA
SELECT
LBO[3:0]
LOOPBACK
ENABLE
TIMING &
DATA
RECOVERY
TX/RX JITTER
ATTENUATOR
LOS
DETECTOR
TXON_n
LOCAL
ANALOG
LOOPBACK
DIGITAL
LOOPBACK
AIS
DETECTOR
PEAK
DETECTOR
& SLICER
RTIP_n
RRING_n
RX
EQUALIZER
EQUALIZER
CONTROL
RLOS_n
HW/HOST
WR_R/W
RD_DS
ALE_AS
CS
RDY_DTACK
INT
TEST
MICROPROCESSOR CONTROLLER
ICT
PTS1
PTS2
D[7:0]
PCLK
A[7:0]
RESET
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
FIGURE 2. BLOCK DIAGRAM OF THE XRT83VL38 T1/E1/J1 LIU (HARDWARE MODE)
MCLKE1
MCLKT1
CLKSEL[2:0]
MCLKOUT
MASTER CLOCK SYNTHESIZER
TAOS_n
One of Eight Channels, CHANNEL_n - (n=0 : 7)
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
DFM
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
DRIVE
MONITOR
DMO_n
TTIP_n
LINE
DRIVER
TRING_n
LBO[3:0]
REMOTE
LOOPBACK
QRSS
DETECTOR
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
HDB3/
B8ZS
DECODER
NETWORK
LOOP
DETECTOR
NLCD ENABLE
LOCAL
ANALOG
LOOPBACK
DIGITAL
LOOPBACK
JA
SELECT
QRSS ENABLE
TXON_n
LOOPBACK
ENABLE
TIMING &
DATA
RECOVERY
TX/RX JITTER
ATTENUATOR
LOS
DETECTOR
AIS
DETECTOR
PEAK
DETECTOR
& SLICER
RTIP_n
RRING_n
RX
EQUALIZER
LOOP1_n
LOOP0_n
EQUALIZER
CONTROL
RLOS_n
HW/HOST
GAUGE
JASEL1
JASEL0
RXTSEL
TXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
TEST
HARWARE CONTROL
ICT
RESET
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS
FEATURES
 Supports Section 13 - Synchronization Interface in ITU G.703 for both Transmit and Receive Paths
 Fully integrated eight channel long-haul or short-haul transceivers for E1,T1 or J1 applications
 Adaptive Receive Equalizer for up to 36dB cable attenuation
 Programable Transmit Pulse Shaper for E1,T1 or J1 short-haul interfaces
 Five fixed transmit pulse settings for T1 short-haul applications plus a fully programmable waveform
generator for transmit output pulse shaping available for both T1 and E1 modes
 Transmit Line Build-Outs (LBO) for T1 long-haul application from 0dB to -22.5dB in three 7.5dB steps
 Selectable receiver sensitivity from 0 to 36dB cable loss for T1 @772kHz and 0 to 43dB for E1 @1024kHz
 Receive monitor mode handles 0 to 29dB resistive attenuation along with 0 to 6dB of cable attenuation for
E1 and 0 to 3dB of cable attenuation for T1 modes
 Supports 75and 120(E1), 100 (T1) and 110 (J1) applications
 Internal and/or external impedance matching for 75, 100110 and 120
 Tri-State transmit output and receive input capability for redundancy applications
 Provides High Impedance for Tx and Rx during power off
 Transmit return loss meets or exceeds ETSI 300-166 standard
 On-chip digital clock recovery circuit for high input jitter tolerance
 Crystal-less digital jitter attenuator with 32-bit or 64-bit FIFO selectable in transmit or receive paths
 On-chip frequency multiplier generates T1 or E1 Master clocks
 High receiver interference immunity
 On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO)
2
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
 Receive loss of signal (RLOS) output
 On-chip HDB3/B8ZS/AMI encoder/decoder functions
 QRSS pattern generator and detection for testing and monitoring
 Error and Bipolar Violation Insertion and Detection
 Receiver Line Attenuation Indication Output in 1dB steps
 Network Loop-Code Detection for automatic Loop-Back Activation/Deactivation
 Transmit All Ones (TAOS) and In-Band Network Loop Up and Down code generators
 Supports Local Analog, Remote, Digital and Dual Loop-Back Modes
 Meets or exceeds T1 and E1 short-haul and long-haul network access specifications in ITU G.703, G.775,
G.736 and G.823; TR-TSY-000499; ANSI T1.403 and T1.408; ETSI 300-166 and AT&T Pub 62411
 Supports both Hardware and Host (parallel or serial) Microprocessor interface for programming
 Programmable Interrupt
 Low power dissipation
 Logic inputs accept either 3.3V or 5V levels
 Dual 3.3V and 1.8V Supply Operation
 225 ball BGA package
 -40°C to +85°C Temperature Range
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT83VL38IB
225 Ball BGA
-40°C to +85°C
3
4
RRING_0
TMS
RRING_1
RTIP_1
MCLKOUT
MCLKE1
MCLKT1
RTIP_5
RRING_5
TCLK
TVDD_5
TDI
RRING_4
RTIP_4
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
RCLK_1
RGND_1
TRING_1
TTIP_0
TGND_0
RLOS_0
RCLK_0
RLOS_1
TTIP_1
TVDD_1
TVDD_0
DMO_1
TNEG_0
TCLK_0
TPOS_1
RPOS_4
RGND_4
TTIP_4
TRING_4
TTIP_5
RGND_5
RLOS_5
2
3
RLOS_4
RCLK_4
TCLK_4
TGND_4
TGND_5
RVDD_5
RPOS_5
RCLK_5
DGND_DR GNDPLL_1
4
TPOS_4
TNEG_4
RNEG_4
TVDD_4
DMO_5
TRING_5
RNEG_5
GNDPLL_2
SR_DR
VDDPLL_2 VDDPLL_1 DVDD_DR
RNEG_1
RPOS_1
TGND_1
TRING_O
RGND_0
RVDD_0
DVDD_PDR RVDD_4
RTIP_0
C
RPOS_0
TCLK_1
5
TNEG_5
TPOS_5
TCLK_5
DMO_4
RVDD_1
DMO_0
TPOS_0
TNEG_1
6
TAOS_6
TAOS_5
TAOS_4
TAOS_7
TAOS_0
TAOS_3
TAOS_1
CLKSEL2
CLKSEL1
CLKSEL0
7
D[5]
D[6]
D[7]
D[0]
8
D[4]
D[2]
TXON_0 JASEL0
9
D[3]
D[1]
10
11
TXTSEL
DVDD_PDR RXTSEL
RXRES0
TCLK_2
DMO_2
TTIP_3
RNEG_3
RLOS_3
12
ICT
TEST
13
14
TXON_4 DMO_7
TXON_5 TNEG_6
TVDD_2
TRING_3
TVDD_7
TVDD_6
RCLK_6
PTS2
DVDD_DR
RLOS_6
RLOS_2
15
TPOS_6
TCLK_7
RLOS_7
16
TCLK_6
RCLK_7
TGND_6
TGND_7
TTIP_7
TTIP_6
RNEG_6
INT
RXON
PTS1
RCLK_2
DGND_DR RVDD_2
TRING_2
TGND_2
TXON_1 TNEG_2 TPOS_3 RPOS_2 RVDDD_3
TXON_2 DMO_3 TCLK_3
TX0N_3 JASEL1 TPOS_2 TNEG_3
A[7]
TERSEL0 TXON_6 TXON_7 TNEG_7 TRING_6
A[4]
A[5]
A[6]
A[3]
DGND_DR HW_HOST TERSEL1 RXMUTE µPCLK TPOS_7
RXRES1
225 Ball BGA
(Top View)
DGND_PDR DVDD_DR
RESET
A[0]
A[2]
A[1]
DVDD_DR DVDD_PDR
DGND_PDR
DGND
DVDD
XRT83VL38
WR_R/W DGND_DR
RD_DS
CS
TAOS_2 RDY_DTACK ALE_AS
GAUGE
RNEG_2
RTIP_2
RRING_2
NC11
RRING_3
RTIP_3
NC12
DVDD_DR
17
RNEG_7
DMO_6
RPOS_7
RGND_7
TRING_7
RVDD_6
RGND_6
RPOS_6
18
DGND_DR
RVDD_7
RTIP_7
RRING_7
SER_PAR
SENSE
RRING_6
RTIP_6
AVDD_BIAS DVDDD_µP
AGND_BIAS
DGND_µP
RGND_2
TTIP_2
TVDD_3
RGND_3
TGND_3
RPOS_3
RCLK_3
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
V
TDO
DGND_PDR RNEG_0
B
A
XRT83VL38
REV. 1.0.0
FIGURE 3. PACKAGE PIN OUT
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
GENERAL DESCRIPTION 1
Applications 1
Block Diagram of the XRT83VL38 T1/E1/J1 LIU (Host Mode) 1
Block Diagram of the XRT83VL38 T1/E1/J1 LIU (Hardware Mode) 2
Features 2
Ordering Information 3
Package Pin Out 4
PIN DESCRIPTION BY FUNCTION 5
Receive Sections 5
Transmitter Sections 7
Microprocessor Interface 11
jitter Attenuator 14
Clock Synthesizer 14
Alarm Functions/Redundancy Support 16
Power and Ground 19
FUNCTIONAL DESCRIPTION 22
Master Clock Generator 22
Two Input Clock Source 22
One Input Clock Source 22
Master Clock Generator 23
23
RECEIVER 23
Receiver Input 23
Receive Monitor Mode 24
Receiver Loss of Signal (RLOS) 24
Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition 24
Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition 25
Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition 25
Simplified Diagram of Extended RLOS mode (E1 Only) 26
Receive HDB3/B8ZS Decoder 26
Recovered Clock (RCLK) Sampling Edge 26
Receive Clock and Output Data Timing 27
Jitter Attenuator 27
Gapped Clock (JA Must be Enabled in the Transmit Path) 27
Maximum Gap Width for Multiplexer/Mapper Applications 27
Arbitrary Pulse Generator for T1 and e1 28
Arbitrary Pulse Segment Assignment 28
TRANSMITTER 28
Digital Data Format 28
Transmit Clock (TCLK) Sampling Edge 28
Transmit Clock and Input Data Timing 29
Transmit HDB3/B8ZS Encoder 29
Examples of HDB3 Encoding 29
Examples of B8ZS Encoding 29
29
Driver Failure Monitor (DMO) 30
Transmit Pulse Shaper & Line Build Out (LBO) circuit 30
I
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
Receive Equalizer Control and Transmit Line Build-Out Settings 30
Transmit and Receive Terminations 32
RECEIVER (Channels 0 - 7) 32
Internal Receive Termination Mode 32
Receive Termination Control 32
Simplified Diagram for the Internal Receive and Transmit Termination Mode 32
Receive Terminations 33
Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0 & TXTSEL= 0) 33
Simplified Diagram for E1 in External Receive Termination Mode (RXTSEL= 0) and Internal Transmit Termination Mode (TXTEL= 1) 34
TRANSMITTER (Channels 0 - 7) 34
Transmit Termination Mode 34
Termination Select Control 34
External Transmit Termination Mode 34
Transmit Terminations 35
35
35
REDUNDANCY APPLICATIONS 35
TYPICAL REDUNDANCY SCHEMES 36
Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy 37
Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy 37
Simplified Block Diagram - Transmit Section for N+1 Redundancy 38
Simplified Block Diagram - Receive Section for N+1 Redundancy 39
Pattern Transmit and Detect Function 40
Pattern transmission control 40
Transmit All Ones (TAOS) 40
Network Loop Code Detection and Transmission 40
Loop-Code Detection Control 40
Transmit and Detect Quasi-Random Signal Source (TDQRSS) 41
Loop-Back Modes 42
Loop-back control in Hardware mode 42
Loop-back control in Host mode 42
Local Analog Loop-Back (ALOOP) 42
Local Analog Loop-back signal flow 42
Remote Loop-Back (RLOOP) 43
Remote Loop-back mode with jitter attenuator selected in receive path 43
Remote Loop-back mode with jitter attenuator selected in Transmit path 43
Digital Loop-Back (DLOOP) 44
Digital Loop-back mode with jitter attenuator selected in Transmit path 44
Dual Loop-Back 44
Signal flow in Dual loop-back mode 44
MICROPROCESSOR Parallel INTERFACE 45
Microprocessor interface signal description 45
Microprocessor Register Tables 46
Microprocessor Register Address 46
Microprocessor Register Bit Description 46
Microprocessor Register Descriptions 50
II
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
Microprocessor Register #0, Bit Description 50
Microprocessor Register #1, Bit Description 52
Microprocessor Register #2, Bit Description 54
Microprocessor Register #3, Bit Description 56
Microprocessor Register #4, Bit Description 57
Microprocessor Register #5, Bit Description 59
Microprocessor Register #6, Bit Description 61
Microprocessor Register #7, Bit Description 62
Microprocessor Register #8, Bit Description 63
Microprocessor Register #9, Bit Description 63
Microprocessor Register #10, Bit Description 64
Microprocessor Register #11, Bit Description 64
Microprocessor Register #12, Bit Description 65
Microprocessor Register #13, Bit Description 65
Microprocessor Register #14, Bit Description 66
Microprocessor Register #15, Bit Description 66
Microprocessor Register #128, Bit Description 67
clock select register 68
Register 0x81h Sub Registers 68
Microprocessor Register #129, Bit Description 68
Microprocessor Register #130, Bit Description 69
Microprocessor Register #131, Bit Description 70
Microprocessor Register #192, Bit Description 71
ELECTRICAL CHARACTERISTICS 72
Absolute Maximum Ratings 72
DC Digital Input and Output Electrical Characteristics 72
XRT83VL38 Power Consumption 72
E1 Receiver Electrical Characteristics 73
T1 Receiver Electrical Characteristics 74
E1 Transmit Return Loss Requirement 74
E1 Transmitter Electrical Characteristics 75
T1 Transmitter Electrical Characteristics 75
ITU G.703 Pulse Template 76
Transmit Pulse Mask Specification 76
ITU G.703 Section 13 Synchronous Interface Pulse Template 77
E1 Synchronous Interface Transmit Pulse Mask Specification 77
DSX-1 Pulse Template (normalized amplitude) 78
DSX1 Interface Isolated pulse mask and corner points 78
AC Electrical Characteristics 79
Transmit Clock and Input Data Timing 79
Receive Clock and Output Data Timing 80
Microprocessor Interface I/O Timing 80
Intel Interface Timing - Asynchronous 80
Intel Asynchronous Programmed I/O Interface Timing 80
Asynchronous Mode 1 - Intel 8051 and 80188 Interface Timing 81
Motorola Asychronous Interface Timing 82
Motorola 68K Asynchronous Programmed I/O Interface Timing 82
III
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
Asynchronous - Motorola 68K - Interface Timing Specification 82
Microprocessor Interface Timing - Reset Pulse Width 82
Package dimensions 83
225 Ball Plastic Ball Grid Array (Bottom View) 83
(19.0 x 19.0 x 1.0mm) 83
ORDERING INFORMATION 84
REVISIONS 84
IV
REV. 1.0.0
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PIN DESCRIPTION BY FUNCTION
RECEIVE SECTIONS
SIGNAL NAME
LEAD #
TYPE
DESCRIPTION
RxON
K16
I
Receiver On - Harware Mode
Writing a “1” to this pin in Hardware mode turns on the Receive Sections of all channels. Writing a “0” shuts off the Receiver Sections of all channels.
RLOS_0
C3
O
Receiver Loss of Signal for Channel_ 0:
This output signal goes “High” for at least one RCLK_0 cycle to indicate loss of signal
at the receive 0 input. RLOS will remain “High” for the entire duration of the Loss of Signal detected by the receiver logic.
SEE”RECEIVER LOSS OF SIGNAL (RLOS)” ON PAGE 24.
Receiver Loss of Signal for Channel _1
Receiver Loss of Signal for Channel _2
Receiver Loss of Signal for Channel _3
Receiver Loss of Signal for Channel _4
Receiver Loss of Signal for Channel_ 5
Receiver Loss of Signal for Channel _6
Receiver Loss of Signal for Channel _7
RLOS_1
RLOS_2
RLOS_3
RLOS_4
RLOS_5
RLOS_6
RLOS_7
H4
H15
A16
V3
L2
J15
T15
RCLK_0
RCLK_1
RCLK_2
RCLK_3
RCLK_4
RCLK_5
RCLK_6
RCLK_7
B3
H3
H16
A17
U3
L3
M15
U16
O
Receiver Clock Output for Channel _0
Receiver Clock Output for Channel _1
Receiver Clock Output for Channel _2
Receiver Clock Output for Channel _3
Receiver Clock Output for Channel _4
Receiver Clock Output for Channel _5
Receiver Clock Output for Channel _6
Receiver Clock Output for Channel _7
RNEG_0
A2
O
LCV_0
A2
RNEG_1
LCV_1
RNEG_2
LCV_2
RNEG_3
LCV_3
RNEG_4
LCV_4
RNEG_5
LCV_5
RNEG_6
LCV_6
RNEG_7
LCV_7
H2
Receiver Negative Data Output for Channel_0 - Dual-Rail mode
This signal is the receive negative-rail output data.
Line Code Violation Output for Channel_0 - Single-Rail mode
This signal goes “High” for one RCLK_0 cycle to indicate a code violation is detected in
the received data of Channel _0. If AMI coding is selected, every bipolar violation
received will cause this pin to go “High”.
Receiver Negative Data Output for Channel _1
Line Code Violation Output for Channel _1
Receiver Negative Data Output for Channel _2
Line Code Violation Output for Channel _2
Receiver Negative Data Output for Channel _3
Line Code Violation Output for Channel _3
Receiver Negative Data Output for Channel _4
Line Code Violation Output for Channel _4
Receiver Negative Data Output for Channel _5
Line Code Violation Output for Channel _5
Receiver Negative Data Output for Channel _6
Line Code Violation Output for Channel _6
Receiver Negative Data Output for Channel _7
Line Code Violation Output for Channel _7
H18
B16
T4
M4
M16
V17
5
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
SIGNAL NAME
LEAD #
TYPE
RPOS_0
B2
O
RDATA_0
B2
RPOS_1
RDATA_1
RPOS_2
RDATA_2
RPOS_3
RDATA_3
RPOS_4
RDATA_4
RPOS_5
RDATA_5
RPOS_6
RDATA_6
RPOS_7
RDATA_7
G2
Receiver Positive Data Output for Channel _0 - Dual-Rail mode
This signal is the receive positive-rail output data sent to the Framer.
Receiver NRZ Data Output for Channel _0 - Single-Rail mode
This signal is the receive output data.
Receiver Positive Data Output for Channel _1
Receiver NRZ Data Output for Channel _1
Receiver Positive Data Output for Channel _2
Receiver NRZ Data Output for Channel _2
Receiver Positive Data Output for Channel _3
Receiver NRZ Data Output for Channel _3
Receiver Positive Data Output for Channel _4
Receiver NRZ Data Output for Channel _4
Receiver Positive Data Output for Channel _5
Receiver NRZ Data Output for Channel _5
Receiver Positive Data Output for Channel _6
Receiver NRZ Data Output for Channel 6
Receiver Positive Data Output for Channel _7
Receiver NRZ Data Output for Channel _7
I
Receiver Differential Tip Input for Channel _0
Positive differential receive input from the line
Receiver Differential Tip Input for Channel _1
Receiver Differential Tip Input for Channel _2
Receiver Differential Tip Input for Channel _3
Receiver Differential Tip Input for Channel _4
Receiver Differential Tip Input for Channel _5
Receiver Differential Tip Input for Channel _6
Receiver Differential Tip Input for Channel _7
I
Receiver Differential Ring Input for Channel _0
Negative differential receive input from the line
Receiver Differential Ring Input for Channel _1
Receiver Differential Ring Input for Channel _2
Receiver Differential Ring Input for Channel _3
Receiver Differential Ring Input for Channel _4
Receiver Differential Ring Input for Channel _5
Receiver Differential Ring Input for Channel _6
Receiver Differential Ring Input for Channel _7
I
Receive Data Muting
When a LOS condition occurs, the outputs RPOS_n/RNEG_n will be muted, (forced to
ground) to prevent data chattering.
Tie this pin “Low” to disable the muting function.
D15
B17
U2
M3
L17
T17
RTIP_0
C1
RTIP_1
RTIP_2
RTIP_3
RTIP_4
RTIP_5
RTIP_6
RTIP_7
G1
G18
C18
U1
L1
L18
T18
RRING_0
D1
RRING_1
RRING_2
RRING_3
RRING_4
RRING_5
RRING_6
RRING_7
F1
F18
D18
T1
M1
M18
R18
RXMUTE
T12
DESCRIPTION
NOTES:
1.
This pin is internally pulled “High” with a 50k resistor.
2.
In Hardware mode, all receive channels share the same RXMUTE control
function.
6
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL NAME
LEAD #
TYPE
RXRES1
RXRES0
R10
V10
I
DESCRIPTION
Receive External Resistor Control Pins - Hardware mode
Receive External Resistor Control Pin 1:
Receive External Resistor Control Pin 0:
These pins determine the value of the external Receive fixed resistor according to the
following table:
RXRES1
RXRES0
Required Fixed External
RX Resistor
0
0
No External Fixed Resistor
0
1
240 
1
0
210 
1
1
150 
NOTE: These pins are internally pulled “Low” with a 50k resistor.
RCLKE
J16
µPTS1
J16
I
Receive Clock Edge - Hardware mode
Set this pin “High” to sample RPOS_N/RNEG_n on the falling edge of RCLK_n. With
this pin tied “Low”, output data are updated on the rising edge of RCLK_n.
Microprocessor Type Select Input pin 1 - Host mode
This pin along with µPTS2 (pin 128) is used to select the microprocessor type.
SEE”MICROPROCESSOR TYPE SELECT INPUT PINS - HOST MODE:”
ON PAGE 12.
NOTE: This pin is internally pulled “Low” with a 50k resistor.
TRANSMITTER SECTIONS
SIGNAL NAME
LEAD #
TYPE
TCLKE
L15
I
µPTS2
L15
DESCRIPTION
Transmit Clock Edge - Hardware mode
Set this pin “High” to sample transmit input data on the rising edge of TCLK_n. With
this pin tied “Low”, input data are sampled on the falling edge of TCLK_n.
Microprocessor Type Select Input pin 2 - Host mode
This pin along with µPTS1 (pin 133) selects the microprocessor type. SEE”MICRO-
PROCESSOR TYPE SELECT INPUT PINS - HOST MODE:” ON PAGE 12.
NOTE: This pin is internally pulled “Low” with a 50k resistor.
TTIP_0
E3
TTIP_1
TTIP_2
TTIP_3
TTIP_4
TTIP_5
TTIP_6
TTIP_7
G4
F17
C16
R2
N2
N16
P16
O
Transmitter Tip Output for Channel _0
Positive differential transmit output to the line.
Transmitter Tip Output for Channel _1
Transmitter Tip Output for Channel _2
Transmitter Tip Output for Channel _3
Transmitter Tip Output for Channel _4
Transmitter Tip Output for Channel _5
Transmitter Tip Output for Channel _6
Transmitter Tip Output for Channel _7
7
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL NAME
LEAD #
TYPE
TRING_0
E2
O
TRING_1
TRING_2
TRING_3
TRING_4
TRING_5
TRING_6
TRING_7
F3
F15
E16
P2
N4
R15
P17
Transmitter Ring Output for Channel _0
Negative differential transmit output to the line.
Transmitter Ring Output for Channel _1
Transmitter Ring Output for Channel _2
Transmitter Ring Output for Channel _3
Transmitter Ring Output for Channel _4
Transmitter Ring Output for Channel _5
Transmitter Ring Output for Channel _6
Transmitter Ring Output for Channel _7
TPOS_0
C5
I
Transmitter Positive Data Input for Channel _0 - Dual-Rail mode
This signal is the positive-rail input data for transmitter 0.
Transmitter 0 Data Input - Single-Rail mode
This pin is used as the NRZ input data for transmitter 0.
Transmitter Positive Data Input for Channel _1
Transmitter 1 Data Input
Transmitter Positive Data Input for Channel _2
Transmitter 2 Data Input
Transmitter Positive Data Input for Channel _3
Transmitter 3 Data Input
Transmitter Positive Data Input for Channel _4
Transmitter 4 Data Input
Transmitter Positive Data Input for Channel _5
Transmitter 5 Data Input
Transmitter Positive Data Input for Channel _6
Transmitter 6 Data Input
Transmitter Positive Data Input for Channel _7
Transmitter 7 Data Input
TDATA_0
TPOS_1
TDATA_1
TPOS_2
TDATA_2
TPOS_3
TDATA_3
TPOS_4
TDATA_4
TPOS_5
TDATA_5
TPOS_6
TDATA_6
TPOS_7
TDATA_7
A4
B14
D14
V4
U5
V15
T14
DESCRIPTION
NOTE: Internally pulled “Low” with a 50k resistor for each channel.
8
REV. 1.0.0
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL NAME
LEAD #
TYPE
DESCRIPTION
TNEG_0
C4
I
CODES_0
C4
TNEG_1
CODES_1
TNEG_2
CODES_2
TNEG_3
CODES_3
TNEG_4
CODES_4
TNEG_5
CODES_5
TNEG_6
CODES_6
TNEG_7
CODES_7
B5
Transmitter Negative NRZ Data Input for Channel _0
Dual-Rail mode
This signal is the negative-rail input data for transmitter 0.
Single-Rail mode
This pin can be left unconnected.
Coding Select for Channel _0 - Hardware mode and Single-Rail mode
Connecting this pin “Low” enables HDB3 in E1 or B8ZS in T1 encoding and decoding
for Channel _0. Connecting this pin “High” selects AMI data format.
Transmitter Negative NRZ Data Input for Channel _1
Coding Select for Channel _1
Transmitter Negative NRZ Data Input for Channel _2
Coding Select for Channel _2
Transmitter Negative NRZ Data Input for Channel _3
Coding Select for Channel _3
Transmitter Negative NRZ Data Input for Channel _4
Coding Select for Channel _4
Transmitter Negative NRZ Data Input for Channel _5
Coding Select for Channel _5
Transmitter Negative NRZ Data Input for Channel _6
Coding Select for Channel _6
Transmitter Negative NRZ Data Input for Channel _7
Coding Select for Channel _7
D13
B15
U4
V5
U14
R14
NOTE: Internally pulled “Low” with a 50k resistor for each channel.
TCLK_0
B4
TCLK_1
TCLK_2
TCLK_3
TCLK_4
TCLK_5
TCLK_6
TCLK_7
A3
A15
C14
T3
T5
V16
U15
I
Transmitter Clock Input for Channel _0 - Host mode and Hardware mode
E1 rate at 2.048MHz ± 50ppm. T1 rate at 1.544MHz ± 32ppm.
During normal operation TCLK_0 is used for sampling input data at TPOS_0/
TDATA_0 and TNEG_0/CODES_0 while MCLK is used as the timing reference for the
transmit pulse shaping circuit.
Transmitter Clock Input for Channel _1
Transmitter Clock Input for Channel _2
Transmitter Clock Input for Channel _3
Transmitter Clock Input for Channel _4
Transmitter Clock Input for Channel _5
Transmitter Clock Input for Channel _6
Transmitter Clock Input for Channel _7
NOTE: Internally pulled “Low” with a 50k resistor for all channels.
9
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
SIGNAL NAME
LEAD #
TYPE
DESCRIPTION
TAOS_0
D6
I
TAOS_1
TAOS_2
TAOS_3
TAOS_4
TAOS_5
TAOS_6
TAOS_7
B6
A5
C6
T6
U6
V6
R6
Transmit All Ones for Channel _0 - Hardware mode
Setting this pin “High” enables the transmission of an “All Ones” Pattern from Channel
_0. A “Low” level stops the transmission of the “All Ones” Pattern.
Transmit All Ones for Channel _1
Transmit All Ones for Channel _2
Transmit All Ones for Channel _3
Transmit All Ones for Channel _4
Transmit All Ones for Channel _5
Transmit All Ones for Channel _6
Transmit All Ones for Channel _7
TXON_0
A13
TXON_1
TXON_2
TXON_3
TXON_4
TXON_5
TXON_6
TXON_7
D12
C12
B12
V13
U13
R12
R13
NOTE: Internally pulled “Low” with a 50k resistor for all channels.
I
Transmitter Turn On for Channel _0
Hardware mode
Setting this pin "High" turns on the Transmit and Receive Sections of Channel _0.
When TXON_0 = “0” then TTIP_0 and TRING_0 driver outputs will be tri-stated.
In Host mode
The TXON_n bits in the channel control registers turn each channel Transmit and
Receive section ON or OFF. However, control of the on/off function can be transferred
to the Hardware pins by setting the TXONCNTL bit (bit 7) to “1” in the register at
address hex 0x82.
Transmitter Turn On for Channel _1
Transmitter Turn On for Channel _2
Transmitter Turn On for Channel _3
Transmitter Turn On for Channel _4
Transmitter Turn On for Channel _5
Transmitter Turn On for Channel _6
Transmitter Turn On for Channel _7
NOTE: Internally pulled “Low” with a 50k resistor for all channels.
10
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MICROPROCESSOR INTERFACE
SIGNAL NAME
LEAD #
TYPE
DESCRIPTION
HW_HOST
T10
I
Mode Control Input
This pin selects Hardware or Host mode. Leave this pin unconnected or tie “High”
to select Hardware mode.
For Host mode, this pin must be tied “Low”.
NOTE: Internally pulled “High” with a 50k resistor.
WR_R/W
D7
EQC0
D7
I
Write Input (Read/Write) - Host mode:
Intel bus timing: A “Low” pulse on WR selects a write operation when CS pin is
“Low”.
Motorola bus timing: A “High” pulse on R/W selects a read operation and a “Low”
pulse on R/W selects a write operation when CS is “Low”.
Equalizer Control Input pin 0 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out. SEE”RECEIVE EQUALIZER CONTROL AND
TRANSMIT LINE BUILD-OUT SETTINGS” ON PAGE 30.
NOTE: Internally pulled “Low” with a 50k resistor.
RD_DS
C7
EQC1
C7
I
Read Input (Data Strobe) - Host mode
Intel bus timing: A “Low” pulse on RD selects a read operation when the CS pin is
“Low”.
Motorola bus timing: A “Low” pulse on DS indicates a read or write operation when
the CS pin is “Low”.
Equalizer Control Input pin 1 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out. SEE”RECEIVE EQUALIZER CONTROL AND
TRANSMIT LINE BUILD-OUT SETTINGS” ON PAGE 30.
NOTE: Internally pulled “Low” with a 50k resistor.
ALE_AS
A7
EQC2
A7
I
Address Latch Input (Address Strobe) - Host mode
Intel bus timing: The address inputs are latched into the internal register on the falling edge of ALE.
Motorola bus timing: The address inputs are latched into the internal register on
the falling edge of AS.
Equalizer Control Input pin 2 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out. SEE”RECEIVE EQUALIZER CONTROL AND
TRANSMIT LINE BUILD-OUT SETTINGS” ON PAGE 30.
NOTE: Internally pulled “Low” with a 50k resistor.
CS
B7
EQC3
B7
I
Chip Select Input - Host mode:
This signal must be “Low” in order to access the parallel port.
Equalizer Control Input pin 3 - Hardware mode:
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out. SEE”RECEIVE EQUALIZER CONTROL AND
TRANSMIT LINE BUILD-OUT SETTINGS” ON PAGE 30.
NOTE: Internally pulled “Low” with a 50k resistor.
11
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL NAME
LEAD #
TYPE
RDY_DTACK
A6
O
EQC4
A6
I
REV. 1.0.0
DESCRIPTION
Ready Output (Data Transfer Acknowledge Output) - Host mode
Intel bus timing: RDY is asserted “High” to indicate the device has completed a
read or write operation.
Motorola bus timing: DTACK is asserted “Low” to indicate the device has completed a read or write cycle.
Equalizer Control Input pin 4 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out. SEE”RECEIVE EQUALIZER CONTROL AND
TRANSMIT LINE BUILD-OUT SETTINGS” ON PAGE 30.
NOTE: Internally pulled “Low” with a 50k resistor.
µPTS1
µPTS2
RCLKE
J16
L15
I
J16
Microprocessor Type Select Input Pins - Host Mode:
Microprocessor Type Select Input Bit 1
Microprocessor Type Select Input Bit 2
PTS2
PTS1
P Type
0
0
Intel 8051 Asynchronous
0
1
Motorola Asynchronous
1
0
Power PC Synchronous
1
1
MPC8xx Motorola Synchronous
Receive Clock Edge - Hardware mode
SEE”RECEIVE CLOCK EDGE - HARDWARE MODE” ON PAGE 7.
Transmit Clock Edge - Hardware mode
TCLKE
L15
SEE”TRANSMIT CLOCK EDGE - HARDWARE MODE” ON PAGE 7.
NOTE: These pins are internally pulled “Low” with a 50k resistor.
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]/SDO
T7
U7
V7
V8
V9
U8
U9
R7
LOOP1_4
LOOP0_4
LOOP1_5
LOOP0_5
LOOP1_6
LOOP0_6
LOOP1_7
LOOP0_7
T7
U7
V7
V8
V9
U8
U9
R7
I/O
Microprocessor Read/Write Data Bus Pins - Host mode
Data Bus[7]
Data Bus[6]
Data Bus[5]
Data Bus[4]
Data Bus[3]
Data Bus[2]
Data Bus[1]
Data Bus[0] if SER_PAR = 0
or Serial Data Input if SER_PAR = 1
Loop-back Control Pins, Bits [1:0] Channel_[7:4] - Hardware Mode
Pins 67-74 and 173-180 control which Loop-Back mode is selected per channel.
SEE”LOOP-BACK CONTROL PINS, BITS [1:0] CHANNEL_[7:0]” ON
PAGE 17.
NOTE: Internally pulled “Low” with a 50k resistor for all channels.
12
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL NAME
LEAD #
TYPE
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]/SDI
A12
B11
C11
D11
A11
B10
A10
C10
I
LOOP1_3
LOOP0_3
LOOP1_2
LOOP0_2
LOOP1_1
LOOP0_1
LOOP1_0
LOOP0_0
A12
B11
C11
D11
A11
B10
A10
C10
µPCLK/SCLK
T13
DESCRIPTION
Microprocessor Interface Address Bus Pins - Host mode:
Microprocessor Interface Address Bus[7]
Microprocessor Interface Address Bus[6]
Microprocessor Interface Address Bus[5]
Microprocessor Interface Address Bus[4]
Microprocessor Interface Address Bus[3]
Microprocessor Interface Address Bus[2]
Microprocessor Interface Address Bus[1]
Microprocessor Interface Address Bus[0] if SER_PAR = 0
or Serial Data Input if SER_PAR = 1
Loop-back Control Pins, Bits [1:0] Channel_[3:0]
In Hardware mode, pins 67-74 and 173-180 control which Loop-Back mode is
selected per channel. SEE”LOOP-BACK CONTROL PINS, BITS [1:0]
CHANNEL_[7:0]” ON PAGE 17.
NOTE: These pins are internally pulled “Low” with a 50k resistor.
I
Microprocessor Clock Input - Host Mode:
µPCLK - Input clock for synchronous parrallel microprocessor operation. Maximum
clock rate is 54 MHz, SER_PAR = 0
SCLK - Input serial clock for SPI interface, SER_PAR = 1
NOTE: This pin is internally pulled “Low” with a 50k resistor for asynchronous
microprocessor interface when no clock is present.
ATAOS
Automatic Transmit “All Ones” - Hardware mode
T13
This pin functions as an Automatic Transmit “All Ones”. SEE”AUTOMATIC
TRANSMIT “ALL ONES” PATTERN - HARDWARE MODE” ON PAGE 16.
INT
L16
O
TRATIO
L16
I
Interrupt Output - Host mode
This pin goes “Low” to indicate an alarm condition has occurred within the device.
Interrupt generation can be globally disabled by setting the GIE bit to a “0” in the
command control register.
Transmitter Transformer Ratio Select - Hardware mode
TRATIO is Not Supported in the 83VL38. This pin is for INT only.
NOTE: This pin is an open drain output and requires an external 10k pull-up
resistor.
13
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
JITTER ATTENUATOR
SIGNAL
NAME
LEAD #
TYPE
JASEL0
JASEL1
A14
B13
I
DESCRIPTION
Jitter Attenuator Select Pins Hardware Mode
Jitter Attenuator select Bit 0
Jitter Attenuator select Bit 1
JASEL[1:0] pins are used to place the jitter attenuator in the transmit path, the receive
path or to disable it.
JASEL1
JASEL0
JA PATH
0
0
Disabled
0
1
Transmit Path
1
0
Receive Path
1
1
Rx & Tx Paths
NOTE: These pins are internally pulled “Low” with 50k resistors.
CLOCK SYNTHESIZER
SIGNAL
NAME
LEAD #
TYPE
DESCRIPTION
MCLKOUT
H1
O
Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1 or E1 rate
based upon the mode of operation.
MCLKT1
K1
I
T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with accuracy better than
±50ppm and duty cycle within 40% to 60%. MCLKT1 is used in the T1 mode.
NOTES:
1. All channels of the XRT83VL38 must be operated at the same clock rate,
either T1, E1 or J1.
2. See pin 26 description for further explanation for the usage of this pin.
3. Internally pulled “Low” with a 50k resistor.
MCLKE1
J1
I
E1 Master Clock Input
A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty cycle of 40%
to 60% can be provided at this pin.
In systems that have only one master clock source available (E1 or T1), that clock
should be connected to both MCLKE1 and MCLKT1 inputs for proper operation.
NOTES:
1. All channels of the XRT83VL38 must be operated at the same clock rate,
either T1, E1 or J1.
2. Internally pulled “Low” with a 50k resistor.
14
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
SIGNAL
NAME
LEAD #
TYPE
DESCRIPTION
CLKSEL0
CLKSEL1
CLKSEL2
A8
B8
C8
I
Clock Select inputs for Master Clock Synthesizer - Hardware mode
CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be
used to generate a master clock from an external accurate clock source according to
the table below.
In Hardware mode, the MCLKRATE control signal is generated from the state of
EQC[4:0] inputs.
In Host mode, the state of these pins are ignored and the master frequency PLL is controlled by the corresponding interface bits. See Table 34 register address 10000001
MCLKE1
kHz
MCLKT1
kHz
CLKSEL 2
CLKSEL1
CLKSEL0
MCLKRATE
CLKOUT
kHz
2048
2048
0
0
0
0
2048
2048
2048
0
0
0
1
1544
2048
1544
0
0
0
0
2048
1544
1544
0
0
1
1
1544
1544
1544
0
0
1
0
2048
2048
1544
0
0
1
1
1544
NOTE: These pins are internally pulled “Low” with a 50k resistor.
15
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
ALARM FUNCTIONS/REDUNDANCY SUPPORT
SIGNAL NAME
LEAD #
TYPE
GAUGE
J18
I
DESCRIPTION
Twisted Pair Cable Wire Gauge Select - Hardware Mode
Connect this pin “High” to select 26 Gauge wire. Connect this pin “Low” to select 22
and 24 gauge wire for all channels.
NOTE: Internally pulled “Low” with a 50k resistor.
DMO_0
D5
DMO_1
DMO_2
DMO_3
DMO_4
DMO_5
DMO_6
DMO_7
D4
C15
C13
R5
P4
U17
V14
ATAOS
T13
µPCLK/SCLK
T13
O
Driver Failure Monitor Channel _0:
This pin transitions “High” if a short circuit condition is detected in the transmit driver of
Channel _0, or no transmit output pulse is detected for more than 128 TCLK_0 cycles.
Driver Failure Monitor Channel _1
Driver Failure Monitor Channel _2
Driver Failure Monitor Channel _3
Driver Failure Monitor Channel _4
Driver Failure Monitor Channel _5
Driver Failure Monitor Channel _6
Driver Failure Monitor Channel _7
I
Automatic Transmit “All Ones” Pattern - Hardware Mode
A "High" level on this pin enables the automatic transmission of an "All Ones" AMI pattern from the transmitter of any channel that the receiver of that channel has detected
an LOS condition. A "Low" level on this pin disables this function.
Note: All channels share the same ATAOS control function.
Microprocessor Clock Input - Host mode
SEE”MICROPROCESSOR CLOCK INPUT - HOST MODE:” ON PAGE 13.
NOTE: This pin is internally pulled “Low” for asynchronous microprocessor interface
when no clock is present.
TRATIO
L16
I
Transmitter Transformer Ratio Select - Hardware mode
TRATIO is Not Supported in the 83VL38. This pin is for INT only..
Interrupt Output - Host mode
This pin is asserted “Low” to indicate an alarm condition. SEE”INTERRUPT OUT-
PUT - HOST MODE” ON PAGE 13.
NOTE: This pin is an open drain output and requires an external 10k pull-up resistor.
INT
L16
O
RESET
T8
I
Hardware Reset (Active “Low”):
When this pin is tied “Low” for more than 10µs, the device is put in the reset state.
Exar recommends initiating a Harware reset upon power up.
NOTE: This pin is internally pulled “High” with a 50k resistor.
SR/DR
K4
I
Single-Rail/Dual-Rail Data Format:
Connect this pin “Low” to select transmit and receive data format in Dual-Rail mode.
In this mode, HDB3 or B8ZS encoder and decoder are not available.
Connect this pin “High” to select single-rail data format.
NOTE: Internally pulled “Low” with a 50k resistor.
16
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL NAME
LEAD #
TYPE
LOOP1_0
LOOP0_0
LOOP1_1
LOOP0_1
LOOP1_2
LOOP0_2
LOOP1_3
LOOP0_3
LOOP1_4
LOOP0_4
LOOP1_5
LOOP0_5
LOOP1_6
LOOP0_6
LOOP1_7
LOOP0_7
A10
C10
A11
B10
C11
D11
A12
B11
T7
U7
V7
V8
V9
U8
U9
R7
I
A[1]
A[0]/SDI
A[3]
A[2]
A[5]
A[4]
A[7]
A[6]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]/SDO
A10
C10
A11
B10
C11
D11
A12
B11
T7
U7
V7
V8
V9
U8
U9
R7
DESCRIPTION
Loop-back Control Pins, Bits [1:0] Channel_[7:0]
Loop-back Control bit 1, Channel _0
Loop-back Control bit 0, Channel _0
Loop-back Control bit 1, Channel _1
Loop-back Control bit 0, Channel _1
Loop-back Control bit 1, Channel _2
Loop-back Control bit 0, Channel _2
Loop-back Control bit 1, Channel _3
Loop-back Control bit 0, Channel _3
Loop-back Control bit 1, Channel _4
Loop-back Control bit 0, Channel _4
Loop-back Control bit 1, Channel _5
Loop-back Control bit 0, Channel _5
Loop-back Control bit 1, Channel _6
Loop-back Control bit 0, Channel _6
Loop-back Control bit 1, Channel _7
Loop-back Control bit 0, Channel _7
In Hardware mode, these pins control the Loop-Back mode for each channel_n per
the following table.
LOOP1_n
LOOP0_n
MODE
0
0
Normal Mode No Loop-Back Channel_n
0
1
Local Loop-Back Channel_n
1
0
Remote Loop-Back Channel_n
1
1
Digital Loop-Back Channel_n
Microprocessor Address A[7:0] and Data Bus Pins D[7:0] - Host mode
These pins are microprocessor address and data bus pins. SEE”MICROPROCESSOR INTERFACE ADDRESS BUS PINS - HOST MODE:” ON PAGE 13. and
see “Microprocessor Read/Write Data Bus Pins - Host mode” on
page 12.
NOTE: These pins are internally pulled “Low” with a 50kresistor.
17
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
SIGNAL NAME
LEAD #
TYPE
DESCRIPTION
EQC4
A6
I
EQC3
EQC2
EQC1
EQC0
B7
A7
C7
D7
I
I
I
I
Equalizer Control Input 4 - Hardware mode
This pin together with pins EQC[3:0] is used to control the transmit pulse shaping,
transmit line build-out (LBO) and receive monitoring while operating at one of either
the T1, E1 or J1 clock rates/modes. SEE”RECEIVE EQUALIZER CONTROL
AND TRANSMIT LINE BUILD-OUT SETTINGS” ON PAGE 30. for description
of Transmit Equalizer Control bits.
Equalizer Control Input 3
Equalizer Control Input 2
Equalizer Control Input 1
Equalizer Control Input 0
RDY_DTACK
CS
ALE_AS
RD_DS
WR_R/W
A6
B7
A7
C7
D7
O
I
I
I
I
RXTSEL
U11
I
NOTES:
1. In Hardware mode all transmit channels share the same pulse setting
controls function.
2. All channels of an XRT83VL38 must operate at the same clock rate, either
the T1, E1 or J1 modes.
In Host mode, these pins perform various microprocessor functions. SEE”MICRO-
PROCESSOR INTERFACE” ON PAGE 11.
NOTE: Internally pulled “Low” with a 50k resistor.
Receiver Termination Select
In Hardware mode, when this pin is “Low” the receive line termination is determined
only by an external resistor. When “High”, the receive termination is realized by the
internal resistor or the combination of internal and external resistors. These conditions
are described in the table below.
NOTE: In Hardware mode all channels share the same RXTSEL control function.
RXTSEL
RX Termination
0
External
1
Internal
In Host mode, the RXTSEL_n bits in the channel control registers determine if the
receiver termination is external or internal. However, the function of RXTSEL can be
transferred to the Hardware pin by setting the TERCNTL bit (bit 6) to “1” in the register
address hex 0x82.
NOTE: This pin is internally pulled “Low” with a 50k resistor.
TXTSEL
V11
I
Transmit Termination Select - Hardware Mode
When this pin is “Low” the transmit line termination is determined only by an external
resistor. When “High”, the transmit termination is realized only by the internal resistor.
TXTSEL
TX Termination
0
External
1
Internal
NOTES:
1. This part does not support external termination in E1 operation.
2. This pin is internally pulled “Low” with a 50k resistor.
3. In Hardware mode all channels share the same TXTSEL control function.
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XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL NAME
LEAD #
TYPE
DESCRIPTION
TERSEL1
TERSEL0
T11
R11
I
Termination Impedance Select bit 1:
Termination Impedance Select bit 0:
In the Hardware mode and in the internal termination mode (TXTSEL=”1” and RXTSEL=”1”) TERSEL[1:0] control the transmit and receive termination impedance
according to the following table.
TERSEL1
TERSEL0
Termination
0
0
100
0
1
110
1
0
75
1
1
120
In the internal termination mode the receiver termination of each receiver is realized
completely by internal resistors or by the combination of internal and one fixed external
resistor (see description of RXRES[1:0] pins).
In the internal termination mode the transformer ratio of 1:2 and 1:1 is required for
transmitter and receiver respectively with the transmitter output AC coupled to the
transformer.
NOTES:
1. This pin is internally pulled “Low” with a 50k resistor.
2. In Hardware mode, all channels share the same TERSEL control function.
3. In the external termination mode a 1:2 transformer ratio must be used for the
transmitter.
TEST
U12
I
Manufacturing Test:
NOTE: For normal operation this pin must be tied to ground.
ICT
V12
I
In-Circuit Testing (Active “Low”):
When this pin is tied “Low”, all output pins are forced to a high impedance state for incircuit testing.
Pulling RESET and ICT pins “Low” simultaneously will put the chip in factory test
mode. This condition should not be permitted during normal operation.
NOTE: This pin is internally pulled “High” with a 50k resistor.
POWER AND GROUND
SIGNAL NAME
LEAD #
TYPE
TGND_0
TGND_1
TGND_2
TGND_3
TGND_4
TGND_5
TGND_6
TGND_7
D3
F2
E15
C17
R3
P3
T16
R16
****
DESCRIPTION
Transmitter Analog Ground for Channel _0
It is recomended that all ground pins form this device be tied together.
19
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
SIGNAL NAME
LEAD #
TYPE
DESCRIPTION
TVDD_0
TVDD_1
TVDD_2
TVDD_3
TVDD_4
TVDD_5
TVDD_6
TVDD_7
E4
F4
F16
E17
R4
P1
N15
P15
****
RVDD_0
RVDD_1
RVDD_2
RVDD_3
RVDD_4
RVDD_5
RVDD_6
RVDD_7
C2
E5
G16
D16
V2
N3
N17
U18
****
Receiver Analog Positive Supply (3.3V± 5%)
RVDD should not be shared with any other supply. It is recommended that RVDD
be isolated from the digital supply DVDD and the analog power supply TVDD. For
best results use an internal power plane for isolation. If an internal power plane is
not available, a ferite bead can be used. Each power supply pin should be
bypassed to ground with an external 0.1uf capcitor.
RGND_0
RGND_1
RGND_2
RGND_3
RGND_4
RGND_5
RGND_6
RGND_7
D2
G3
G17
D17
T2
M2
M17
R17
****
Receiver Analog Ground for Channel_0
It is recomended that all ground pins form this device be tied together.
AVDD
K17
J3
J2
****
Analog Positive Supply (1.8V± 5%)
AVDD should be isolated from other supplies. For best results use an internal
power plane for isolation. If an internal power plane is not available, a ferite bead
can be used. Each power supply pin should be bypassed to ground with at least
one 0.1uf capcitor
AGND
J17
K3
L4
****
Analog Ground
It is recomended that all ground pins form this device be tied together.
DVDD1v8
U10
K18
D10
A9
V1
DVDD3v3
R9
K15
J4
D9
A18
Transmitter Analog Power Supply (3.3V + 5%)
TVDD can be shared with DVDD. However, it is recommended that TVDD be isolated from the analog supply RVDD. For best results use an internal power plane
for isolation. If an internal power plane is not available, a ferite bead can be used.
Each power supply pin should be bypassed to ground with an external 0.1uf capcitor.
Digital Positive Supply (1.8V± 5%)
DVDD1v8 should be isolated from other analog supplies. For best results use an
internal power plane for isolation. If an internal power plane is not available, a ferite bead can be used. Every two DVDD1v8 power supply pins should be
bypassed to ground with at least one 0.1uf capcitor
****
Digital Positive Supply (3.3V± 5%)
DVDD3v3 should be isolated from other analog supplies. For best results use an
internal power plane for isolation. If an internal power plane is not available, a ferite bead can be used. Every two DVDD3v3 power supply pins should be
bypassed to ground with at least one 0.1uf capcitor
20
XRT83VL38
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OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL NAME
LEAD #
TYPE
DGND
R8
T9
H17
B9
D8
C9
G15
K2
****
NC12
B18
DESCRIPTION
Digital Ground
It is recomended that all ground pins form this device be tied together.
No Connect Pin
21
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
FUNCTIONAL DESCRIPTION
The XRT83VL38 is a fully integrated long-haul and short-haul transceiver intended for T1, J1 or E1 systems.
Simplified block diagrams of the chip are shown in Figure 1, Host mode and Figure 2, Hardware mode. The
XRT83VL38 can receive signals that have been attenuated from 0 to 36dB at 772kHz (0 to 6000 feet cable
loss) for T1 and from 0 to 43dB at 1024kHz for E1 systems.
In T1 applications, the XRT83VL38 can generate five transmit pulse shapes to meet the short-haul Digital
Cross-connect (DSX-1) template requirement as well as four CSU Line Build-Out (LBO) filters of 0dB, -7.5dB, 15dB and -22.5dB as required by FCC rules. It also provides programmable transmit output pulse generators
for each channel that can be used for output pulse shaping allowing performance improvement over a wide
variety of conditions (The arbitrary pulse generators are available for both T1 and E1, in short-haul
configuration). The operation and configuration of the XRT83VL38 can be controlled through a parallel
microprocessor Host interface or Hardware control.
MASTER CLOCK GENERATOR
Using a variety of external clock sources, the on-chip frequency synthesizer generates the T1 (1.544MHz) or
E1 (2.048MHz) master clocks necessary for the transmit pulse shaping and receive clock recovery circuit.
There are two master clock inputs MCLKE1 and MCLKT1. In systems where both T1 and E1 master clocks are
available these clocks can be connected to the respective pins. All channels of a given XRT83VL38 must be
operated at the same clock rate, either T1, E1 or J1 modes.
In systems that have only one master clock source available (E1 or T1), that clock should be connected to both
MCLKE1 and MCLKT1 inputs for proper operation. T1 or E1 master clocks can be generated from a single
1.544MHz or 2.048MHz external clock under the control of CLKSEL[2:0] inputs according to Table 1.
NOTE: EQC[4:0] determine the T1/E1 operating mode. See Table 5 for details.
FIGURE 4. TWO INPUT CLOCK SOURCE
Two Input Clock Sources
2.048MHz
+/-50ppm
MCLKE1
MCLKOUT
1.544MHz
+/-50ppm
MCLKT1
1.544MHz
or
2.048MHz
FIGURE 5. ONE INPUT CLOCK SOURCE
Input Clock Options
1.544MHz
or
2.048MHz
One Input Clock Source
MCLKE1
MCLKOUT
MCLKT1
22
1. 544MHz
or
2. 048MHz
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 1: MASTER CLOCK GENERATOR
MCLKE1
KHZ
MCLKT1
KHZ
CLKSEL2
CLKSEL1
CLKSEL0
MCLKRATE
MASTER CLOCK
KHZ
2048
2048
0
0
0
0
2048
2048
2048
0
0
0
1
1544
2048
1544
0
0
0
0
2048
1544
1544
0
0
1
1
1544
1544
1544
0
0
1
0
2048
2048
1544
0
0
1
1
1544
In Host mode the programming is achieved through the corresponding interface control bits, the state of the
CLKSEL[2:0] control bits and the state of the MCLKRATE interface control bit.
RECEIVER
RECEIVER INPUT
At the receiver input, a cable attenuated AMI signal can be coupled to the receiver through a capacitor or a 1:1
transformer. The input signal is first applied to a selective equalizer for signal conditioning. The maximum
equalizer gain is up to 36dB for T1 and 43dB for E1 modes. The equalized signal is subsequently applied to a
peak detector which in turn controls the equalizer settings and the data slicer. The slicer threshold for both E1
and T1 is typically set at 50% of the peak amplitude at the equalizer output. After the slicers, the digital
representation of the AMI signals are applied to the clock and data recovery circuit. The recovered data
subsequently goes through the jitter attenuator and decoder (if selected) for HDB3 or B8ZS decoding before
being applied to the RPOS_n/RDATA_n and RNEG_n/LCV_n pins. Clock recovery is accomplished by a digital
phase-locked loop (DPLL) which does not require any external components and can tolerate high levels of
input jitter that meets or exceeds the ITU-G.823 and TR-TSY000499 standards.
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XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
RECEIVE MONITOR MODE
In applications where Monitor mode is desired, the equalizer can be configured in a gain mode which handles
input signals attenuated resistively up to 29dB, along with 0 to 6dB cable attenuation for both T1 and E1
applications, refer to Table 5 for details. This feature is available in both Hardware and Host modes.
RECEIVER LOSS OF SIGNAL (RLOS)
For compatibility with ITU G.775 requirements, the RLOS monitoring function is implemented using both
analog and digital detection schemes. If the analog RLOS condition occurs, a digital detector is activated to
count for 32 consecutive zeros in E1 (4096 bits in Extended Los mode, EXLOS = “1”) or 175 consecutive zeros
in T1 before RLOS is asserted. RLOS is cleared when the input signal rises +3dB (built in hysteresis) above
the point at which it was declared and meets 12.5% ones density of 4 ones in a 32 bit window, with no more
than 16 consecutive zeros for E1. In T1 mode, RLOS is cleared when the input signal rises +3dB (built in
hysteresis) above the point at which it was declared and contains 16 ones in a 128 bit window with no more
than 100 consecutive zeros in the data stream. When loss of signal occurs, RLOS register indication and
register status will change. If the RLOS register enable is set high (enabled), the alarm will trigger an interrupt
causing the interrupt pin (INT) to go low. Once the alarm status register has been read, it will automatically
reset upon read (RUR), and the INT pin will return high.
Analog RLOS
Setting the Receiver Inputs to -15dB T1/E1 Short Haul Mode
By setting the receiver inputs to -15dB T1/E1 short haul mode, the equalizer will detect the incoming amplitude
and make adjustments by adding gain up to a maximum of +15dB normalizing the T1/E1 input signal.
NOTE: This is the only setting that refers to cable loss (frequency), not flat loss (resistive).
Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+15dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is
typically -24dB (-15dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total cable attenuation of -21dB. See Figure 6 for a
simplified diagram.
FIGURE 6. SIMPLIFIED DIAGRAM OF -15dB T1/E1 SHORT HAUL MODE AND RLOS CONDITION
Norm alized up to +15dB Max
-9dB
Clear LOS
+3dB
Declare LOS
Declare LOS
+3dB
Clear LOS
-9dB
Norm alized up to +15dB Max
Setting the Receiver Inputs to -29dB T1/E1 Gain Mode
By setting the receiver inputs to -29dB T1/E1 gain mode, the equalizer will detect the incoming amplitude and
make adjustments by adding gain up to a maximum of +29dB normalizing the T1/E1 input signal.
NOTE: This is the only setting that refers to flat loss (resistive). All other modes refer to cable loss (frequency).
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XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+29dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is
typically -38dB (-29dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total flat loss of -35dB. See Figure 7 for a simplified diagram.
FIGURE 7. SIMPLIFIED DIAGRAM OF -29dB T1/E1 GAIN MODE AND RLOS CONDITION
Norm alized up to +29dB Max
-9dB
Clear LOS
+3dB
Declare LOS
Declare LOS
+3dB
Clear LOS
-9dB
Norm alized up to +29dB Max
Setting the Receiver Inputs to -36dB T1/E1 Long Haul Mode
By setting the receiver inputs to -36dB T1/E1 long haul mode, the equalizer will detect the incoming amplitude
and make adjustments by adding gain up to a maximum of +36dB normalizing the T1 input signal. This setting
refers to cable loss (frequency), not flat loss (resistive). Once the T1/E1 input signal has been normalized to
0dB by adding the maximum gain (+36dB), the receiver will declare RLOS if the signal is attenuated by an
additional -9dB. The total cable loss at RLOS declaration is typically -45dB (-36dB + -9dB). A 3dB hysteresis
was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a
total cable attenuation of -42dB. See Figure 8 for a simplified diagram.
FIGURE 8. SIMPLIFIED DIAGRAM OF -36dB T1/E1 LONG HAUL MODE AND RLOS CONDITION
Norm alized up to +36dB Max
-9dB
Clear LOS
+3dB
Declare LOS
Declare LOS
+3dB
Clear LOS
-9dB
Norm alized up to +36dB Max
E1 Extended RLOS
E1: Setting the Receiver Inputs to Extended RLOS
By setting the receiver inputs to extended RLOS, the equalizer will detect the incoming amplitude and make
adjustments by adding gain up to a maximum of +43dB normalizing the E1 input signal. This setting refers to
25
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
cable loss (frequency), not flat loss (resistive). Once the E1 input signal has been normalized to 0dB by adding
the maximum gain (+43dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB.
The total cable loss at RLOS declaration is typically -52dB (-43dB + -9dB). A 3dB hysteresis was designed so
that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable
attenuation of -49dB. See Figure 9 for a simplified diagram.
FIGURE 9. SIMPLIFIED DIAGRAM OF EXTENDED RLOS MODE (E1 ONLY)
Norm alized up to +45dB Max
-9dB
Clear LOS
+3dB
Declare LOS
Declare LOS
+3dB
Clear LOS
-9dB
Norm alized up to +45dB Max
RECEIVE HDB3/B8ZS DECODER
The Decoder function is available in both Hardware and Host modes on a per channel basis by controlling the
TNEG_n/CODES_n pin or the CODES_n interface bit. The decoder function is only active in single-rail Mode.
When selected, receive data in this mode will be decoded according to HDB3 rules for E1 and B8ZS for T1
systems. Bipolar violations that do not conform to the coding scheme will be reported as Line Code Violation at
the RNEG_n/LCV_n pin of each channel. The length of the LCV pulse is one RCLK cycle for each code
violation. In E1mode only, an excessive number of zeros in the receive data stream is also reported as an error
at the same output pin. If AMI decoding is selected in single rail mode, every bipolar violation in the receive
data stream will be reported as an error at the RNEG_n/LCV_n pin.
RECOVERED CLOCK (RCLK) SAMPLING EDGE
This feature is available in both Hardware and Host modes on a global basis. In Host mode, the sampling
edge of RCLK output can be changed through the interface control bit RCLKE. If a “1” is written in the RCLKE
interface bit, receive data output at RPOS_n/RDATA_n and RNEG_n/LCV_n are updated on the falling edge of
26
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
RCLK for all eight channels. Writing a “0” to the RCLKE register, updates the receive data on the rising edge of
RCLK. In Hardware mode the same feature is available under the control of the RCLKE pin.
FIGURE 10. RECEIVE CLOCK AND OUTPUT DATA TIMING
RCLKR
RDY
RCLKF
RCLK
RPOS
or
RNEG
RHO
JITTER ATTENUATOR
To reduce phase and frequency jitter in the recovered clock, the jitter attenuator can be placed in the receive
signal path. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth that can vary
between 2x32 and 2x64. The jitter attenuator can also be placed in the transmit signal path or disabled
altogether depending upon system requirements. The jitter attenuator, other than using the master clock as
reference, requires no external components. With the jitter attenuator selected, the typical throughput delay
from input to output is 16 bits for 32 bit FIFO size or 32 bits for 64 bit FIFO size. When the read and write
pointers of the FIFO in the jitter attenuator are within two bits of over-flowing or under-flowing, the bandwidth of
the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this
situation occurs, the jitter attenuator will not attenuate input jitter until the read/write pointer's position is outside
the two bits window. Under normal condition, the jitter transfer characteristic meets the narrow bandwidth
requirement as specified in ITU- G.736, ITU- I.431 and AT&T Pub 62411 standards.
In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz. In E1 mode, the bandwidth can be reduced
through the JABW control signal. When JABW is set “High” the bandwidth of the jitter attenuator is reduced
from 10Hz to 1.5Hz. Under this condition the FIFO length is automatically set to 64 bits and the 32 bits FIFO
length will not be available in this mode. Jitter attenuator controls are available on a per channel basis in the
Host mode and on a global basis in the Hardware mode.
GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH)
The XRT83VL38 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are removed
which can leave gaps in the incoming data stream. If the jitter attenuator is enabled in the transmit path, the
32-Bit or 64-Bit FIFO is used to smooth the gapped clock into a steady T1 or E1 output. The maximum gap
width of the 8-Channel LIU is shown in Table 2.
TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS
FIFO DEPTH
MAXIMUM GAP WIDTH
32-Bit
20 UI
64-Bit
50 UI
NOTE: If the LIU is used in a loop timing system, the jitter attenuator should be enabled in the receive path.
27
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
ARBITRARY PULSE GENERATOR FOR T1 AND E1
The arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit
binary word by programming the appropriate channel register. This allows the system designer to set the
overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit is
set to “1”, the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is set
to “0”, the segment will move in a negative direction relative to a flat line condition. A pulse with numbered
segments is shown in Figure 11.
FIGURE 11. ARBITRARY PULSE SEGMENT ASSIGNMENT
1
2
3
Segment
1
2
3
4
5
6
7
8
4
Register
0xn8
0xn9
0xna
0xnb
0xnc
0xnd
0xne
0xnf
8
7
6
5
NOTE: By default, the arbitrary segments are programmed to 0x00h. The transmitter outputs will result in an all zero pattern
to the line. For E1 arbitrary mode, see global register 0xC0h.
TRANSMITTER
DIGITAL DATA FORMAT
Both the transmitter and receiver can be configured to operate in dual or single-rail data formats. This feature is
available under both Hardware and Host control modes, on a global basis. The dual or single-rail data format
is determined by the state of the SR/DR pin in Hardware mode or SR/DR interface bit in the Host mode. In
single-rail mode, transmit clock and NRZ data are applied to TCLK_n and TPOS_n/TDATA_n pins respectively.
In single-rail and Hardware mode the TNEG_n/CODES_n input can be used as the CODES function. With
TNEG_n/CODES_n tied “Low”, HDB3 or B8ZS encoding and decoding are enabled for E1 and T1 modes
respectively. With TNEG_n/CODES_n tied “High”, the AMI coding scheme is selected. In both dual or singlerail modes of operations, the transmitter converts digital input data to a bipolar format before being transmitted
to the line.
TRANSMIT CLOCK (TCLK) SAMPLING EDGE
Serial transmit data at TPOS_n/TDATA_n and TNEG_n/CODES_n are clocked into the XRT83VL38 under the
synchronization of TCLK_n. With a “0” written to the TCLKE interface bit, or by pulling the TCLKE pin “Low”,
input data is sampled on the falling edge of TCLK_n. The sampling edge is inverted with a “1” written to TCLKE
interface bit, or by connecting the TCLKE pin “High”.
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OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
FIGURE 12. TRANSMIT CLOCK AND INPUT DATA TIMING
TCLKR
TCLKF
TCLK
TPOS/TDATA
or
TNEG
THO
TSU
TRANSMIT HDB3/B8ZS ENCODER
The Encoder function is available in both Hardware and Host modes on a per channel basis by controlling the
TNEG_n/CODES_n pin or CODES interface bit. The encoder is only available in single-rail mode. In E1 mode
and with HDB3 encoding selected, any sequence with four or more consecutive zeros in the input serial data
from TPOS_n/TDATA_n, will be removed and replaced with 000V or B00V, where “B” indicates a pulse
conforming with the bipolar rule and “V” representing a pulse violating the rule. An example of HDB3 Encoding
is shown in Table 3. In a T1 system, an input data sequence with eight or more consecutive zeros will be
removed and replaced using the B8ZS encoding rule. An example of Bipolar with 8 Zero Substitution (B8ZS)
encoding scheme is shown in Table 4. Writing a “1” into the CODES_n interface bit or connecting the TNEG_n/
CODES_n pin to a “High” level selects the AMI coding for both E1 or T1 systems.
TABLE 3: EXAMPLES OF HDB3 ENCODING
NUMBER OF PULSE BEFORE NEXT 4 ZEROS
Input
NEXT 4 BITS
0000
HDB3 (case1)
odd
000V
HDB3 (case2)
even
B00V
TABLE 4: EXAMPLES OF B8ZS ENCODING
CASE 1
PRECEDING PULSE
NEXT 8 BITS
Input
+
00000000
B8ZS
AMI Output
000VB0VB
+
000+ -0- +
-
00000000
CASE 2
Input
B8ZS
AMI Output
000VB0VB
-
29
000- +0+ -
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
DRIVER FAILURE MONITOR (DMO)
The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and TRING
outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the
transmit input. If the transmitter of a channel has no output for more than 128 clock cycles, the corresponding
DMO pin goes “High” and remains “High” until a valid transmit pulse is detected. In Host mode, the failure of
the transmit channel is reported in the corresponding interface bit. If the DMOIE bit is also enabled, any
transition on the DMO interface bit will generate an interrupt. The driver failure monitor is supported in both
Hardware and Host modes on a per channel basis.
TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT
The transmit pulse shaper circuit uses the high speed clock from the Master timing generator to control the
shape and width of the transmitted pulse. The internal high-speed timing generator eliminates the need for a
tightly controlled transmit clock (TCLK) duty cycle. With the jitter attenuator not in the transmit path, the
transmit output will generate no more than 0.025Unit Interval (UI) peak-to-peak jitter. In Hardware mode, the
state of the A[4:0]/EQC[4:0] pins determine the transmit pulse shape for all eight channels. In Host mode
transmit pulse shape can be controlled on a per channel basis using the interface bits EQC[4:0]. The chip
supports five fixed transmit pulse settings for T1 Short-haul applications plus a fully programmable waveform
generator for arbitrary transmit output pulse shapes (The arbitrary pulse generators are available for both T1
and E1). Transmit Line Build-Outs for T1 long-haul application are supported from 0dB to -22.5dB in three
7.5dB steps. The choice of the transmit pulse shape and LBO under the control of the interface bits are
summarized in Table 5. For CSU LBO transmit pulse design information, refer to ANSI T1.403-1993 Networkto-Customer Installation specification, Annex-E.
NOTE: EQC[4:0] determine the T1/E1 operating mode of the XRT83VL38. When EQC4 = “1” and EQC3 = “1”, the
XRT83VL38 is in the E1 mode, otherwise it is in the T1/J1 mode. For details on how to enable the E1 arbitrary
mode, see global register 0xC0h.
TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS
EQC4
EQC3
EQC2
EQC1
EQC0
E1/T1 MODE & RECEIVE
SENSITIVITY
TRANSMIT LBO
CABLE
CODING
0
0
0
0
0
T1 Long Haul/36dB
0dB
100/ TP
B8ZS
0
0
0
0
1
T1 Long Haul/36dB
-7.5dB
100/ TP
B8ZS
0
0
0
1
0
T1 Long Haul/36dB
-15dB
100/ TP
B8ZS
0
0
0
1
1
T1 Long Haul/36dB
-22.5dB
100/ TP
B8ZS
0
0
1
0
0
T1 Long Haul/45dB
0dB
100/ TP
B8ZS
0
0
1
0
1
T1 Long Haul/45dB
-7.5dB
100/ TP
B8ZS
0
0
1
1
0
T1 Long Haul/45dB
-15dB
100/ TP
B8ZS
0
0
1
1
1
T1 Long Haul/45dB
-22.5dB
100/ TP
B8ZS
0
1
0
0
0
T1 Short Haul/15dB
0-133 ft./ 0.6dB
100/ TP
B8ZS
0
1
0
0
1
T1 Short Haul/15dB
133-266 ft./ 1.2dB
100/ TP
B8ZS
0
1
0
1
0
T1 Short Haul/15dB
266-399 ft./ 1.8dB
100/ TP
B8ZS
0
1
0
1
1
T1 Short Haul/15dB
399-533 ft./ 2.4dB
100/ TP
B8ZS
0
1
1
0
0
T1 Short Haul/15dB
533-655 ft./ 3.0dB
100/ TP
B8ZS
30
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS
EQC4
EQC3
EQC2
EQC1
EQC0
E1/T1 MODE & RECEIVE
SENSITIVITY
TRANSMIT LBO
CABLE
CODING
0
1
1
0
1
T1 Short Haul/15dB
Arbitrary Pulse
100/ TP
B8ZS
0
1
1
1
0
T1 Gain Mode/29dB
0-133 ft./ 0.6dB
100/ TP
B8ZS
0
1
1
1
1
T1 Gain Mode/29dB
133-266 ft./ 1.2dB
100/ TP
B8ZS
1
0
0
0
0
T1 Gain Mode/29dB
266-399 ft./ 1.8dB
100/ TP
B8ZS
1
0
0
0
1
T1 Gain Mode/29dB
399-533 ft./ 2.4dB
100/ TP
B8ZS
1
0
0
1
0
T1 Gain Mode/29dB
533-655 ft./ 3.0dB
100/ TP
B8ZS
1
0
0
1
1
T1 Gain Mode/29dB
Arbitrary Pulse
100/ TP
B8ZS
1
0
1
0
0
T1 Gain Mode/29dB
0dB
100/ TP
B8ZS
1
0
1
0
1
T1 Gain Mode/29dB
-7.5dB
100/ TP
B8ZS
1
0
1
1
0
T1 Gain Mode/29dB
-15dB
100/ TP
B8ZS
1
0
1
1
1
T1 Gain Mode/29dB
-22.5dB
100/ TP
B8ZS
1
1
0
0
0
E1 Long Haul/36dB
ITU G.703/Arbitrary
75 Coax
HDB3
1
1
0
0
1
E1 Long Haul/36dB
ITU G.703/Arbitrary
120 TP
HDB3
1
1
0
1
0
E1 Long Haul/43dB
ITU G.703/Arbitrary
75 Coax
HDB3
1
1
0
1
1
E1 Long Haul/43dB
ITU G.703/Arbitrary
120 TP
HDB3
1
1
1
0
0
E1 Short Haul
ITU G.703/Arbitrary
75 Coax
HDB3
1
1
1
0
1
E1 Short Haul
ITU G.703/Arbitrary
120 TP
HDB3
1
1
1
1
0
E1 Gain Mode
ITU G.703/Arbitrary
75 Coax
HDB3
1
1
1
1
1
E1 Gain Mode
ITU G.703/Arbitrary
120 TP
HDB3
31
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TRANSMIT AND RECEIVE TERMINATIONS
The XRT83VL38 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide
applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the
use of existing components and/or designs.
RECEIVER (CHANNELS 0 - 7)
INTERNAL RECEIVE TERMINATION MODE
In Hardware mode, RXTSEL (Pin 83) can be tied “High” to select internal termination mode for all receive
channels or tied “Low” to select external termination mode. Individual channel control can only be done in Host
mode. By default the XRT83VL38 is set for external termination mode at power up or at Hardware reset.
TABLE 6: RECEIVE TERMINATION CONTROL
RXTSEL
RX TERMINATION
0
EXTERNAL
1
INTERNAL
In Host mode, bit 7 in the appropriate channel register, (Table 18, “Microprocessor Register #1, Bit
Description,” on page 52), is set “High” to select the internal termination mode for that specific receive
channel.
FIGURE 13. SIMPLIFIED DIAGRAM FOR THE INTERNAL RECEIVE AND TRANSMIT TERMINATION MODE
Channel _n
TTIP
TPO S
1
R int
T1
5
0.68  F
TTIP
TNEG
TCLK
75  , 100 
TX
Line Driver
110   or 120 
TRING
TRING
4
8
1:2
R int
RTIP
RPO S
5
T2
1
RNEG
RCLK
RX
Equalizer
RTIP
75  , 100 
R int
110   or 120 
RRING
8
4
1:1
RRING
If the internal termination mode (RXTSEL = “1”) is selected, the effective impedance for E1, T1 or J1 can be
achieved either with an internal resistor or a combination of internal and external resistors as shown in Table 7.
NOTE: In Hardware mode, pins RXRES[1:0] control all channels.
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XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 7: RECEIVE TERMINATIONS
RXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
Rext
Rint
MODE
0
x
x
x
x
Rext

T1/E1/J1
1
0
0
0
0

100
T1
1
0
1
0
0

110
J1
1
1
0
0
0

75
E1
1
1
1
0
0

120
E1
1
0
0
0
1
240
172
T1
1
0
1
0
1
240
204
J1
1
1
0
0
1
240
108
E1
1
1
1
0
1
240
240
E1
1
0
0
1
0
210
192
T1
1
0
1
1
0
210
232
J1
1
1
0
1
0
210
116
E1
1
1
1
1
0
210
280
E1
1
0
0
1
1
150
300
T1
1
0
1
1
1
150
412
J1
1
1
0
1
1
150
150
E1
1
1
1
1
1
150
600
E1
Figure 14 is a simplified diagram for T1 (100) in the external receive and transmit termination mode.
Figure 15 is a simplified diagram for E1 (75) in the external receive and internal transmit termination mode.
FIGURE 14. SIMPLIFIED DIAGRAM FOR T1 IN THE EXTERNAL TERMINATION MODE (RXTSEL= 0 & TXTSEL= 0)
XRT83VL 38 LIU
3.1  0.68uf
1:2
TTIP
100
3.1
TRING
RTIP
100
100
RRING
1:1
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XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
FIGURE 15. SIMPLIFIED DIAGRAM FOR E1 IN EXTERNAL RECEIVE TERMINATION MODE (RXTSEL= 0)
AND INTERNAL TRANSMIT TERMINATION MODE (TXTEL= 1)
XRT83VL 38 LIU
0.68uf
1:2
TTIP
75
TRING
RTIP
75
75
RRING
1:1
TRANSMITTER (CHANNELS 0 - 7)
TRANSMIT TERMINATION MODE
In Hardware mode, TXTSEL (Pin 84) can be tied “High” to select internal termination mode for all transmit
channels or tied “Low” for external termination. Individual channel control can be done only in Host mode. In
Host mode, bit 6 in the appropriate register for a given channel is set “High” to select the internal termination
mode for that specific transmit channel, see Table 18, “Microprocessor Register #1, Bit Description,” on
page 52.
In internal mode, no external resistors are used. An external capacitor of 0.68F is used for proper operation of
the internal termination circuitry, see Figure 13.
TABLE 8: TERMINATION SELECT CONTROL
TERSEL1
TERSEL0
TERMINATION
0
0
100
0
1
110
1
0
75
1
1
120
EXTERNAL TRANSMIT TERMINATION MODE
By default the XRT83VL38 is set for external termination mode at power up or at Hardware reset.
When external transmit termination mode is selected, the internal termination circuitry is disabled. The value of
the external resistors is chosen for a specific application. Figure 14 is a simplified block diagram for T1 (100)
in the external receive and transmit termination mode. Figure 15 is a simplified block diagram for E1 (75) in
the external receive termination and internal transmit termination mode.
Table 9 summarizes the transmit terminations.
34
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 9: TRANSMIT TERMINATIONS
TERSEL1
TERSEL0
Rint 
TXTSEL
0=EXTERNAL
SET BY
CONTROL
T1
100 
J1
110 
E1
75 
E1
120 
1=INTERNAL
BITS
n (turns Ratio)
Rext 
Cext
n, Rext, AND Cext ARE SUGGESTED
SETTINGS
0
0
0
0
2
3.1
0
0
0
1
12.5
2
0
0.68F
0
1
0
0
2
3.1
0
0
1
1
13.75
2
0
0.68F
1
0
0
E1 external Transmit termination not supported
1
0
1
1
1
0
1
1
1
9.4
2
0
0.68F
E1 external Transmit termination not supported
15
2
0
0.68F
REDUNDANCY APPLICATIONS
Telecommunication system design requires signal integrity and reliability. When a T1/E1 primary line card has
a failure, it must be swapped with a backup line card while maintaining connectivity to a backplane without
losing data. System designers can achieve this by implementing common redundancy schemes with the
XRT83VL38 Line Interface Unit (LIU). The XRT83VL38 offers features that are tailored to redundancy
applications while reducing the number of components and providing system designers with solid reference
designs. These features allow system designers to implement redundancy applications that ensure reliability.
The Internal Impedance mode eliminates the need for external relays when using the 1:1 and 1+1 redundancy
schemes.
35
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
PROGRAMMING CONSIDERATIONS
In many applications switching the control of the transmitter outputs and the receiver line impedance to
hardware control will provide faster transmitter ON/OFF switching.
In Host Mode, there are two bits in register 130 (82H) that control the transmitter outputs and the Rx line
impedance select, TXONCNTL (Bit 7) and TERCNTL (Bit 6).
Setting bit-7 (TXONCNTL) to a “1” transfers the control of the Transmit On/Off function to the TXON_n
Hardware control pins. (Pins 90 through 93 and pins 169 through 172). The TXON is used to tri-state the
transmit outputs when used in a redundancy application.
Setting bit-6 (TERCNTL) to a “1” transfers the control of the Rx line impedance select (RXTSEL) to the
RXTSEL Hardware control pin (pin 83).
Either mode works well with redundancy applications. The user can determine which mode has the fastest
switching time for a unique application.
TYPICAL REDUNDANCY SCHEMES
n
·1:1 One backup card for every primary card (Facility Protection)
n
·1+1 One backup card for every primary card (Line Protection)
n
·N+1One backup card for N primary cards
1:1 REDUNDANCY
A 1:1 facility protection redundancy scheme has one backup card for every primary card. When using 1:1
redundancy, the backup card has its transmitters tri-stated and its receivers in high impedance. This eliminates
the need for external relays and provides one bill of materials for all interface modes of operation. The transmit
and receive sections of the LIU device are described separately.
1+1 REDUNDANCY
A 1+1 line protection redundancy scheme has one backup card for every primary card, and the receivers on
the backup card are monitoring the receiver inputs. Therefore, the receivers on both cards need to be active.
The transmit outputs require no external resistors. The transmit and receive sections of the LIU device are
described separately.
TRANSMIT 1:1 & 1+1 REDUNDANCY
For 1:1 and 1+1 redundancy, the transmitters on the primary and backup card should be programmed for
Internal Impedance mode. The transmitters on the backup card should be tri-stated. Select the appropriate
impedance for the desired mode of operation, T1/E1/J1. A 0.68uF capacitor is used in series with TTIP for
blocking DC bias. See Figure 16 for a simplified block diagram of the transmit section for 1:1 and 1+1
redundancy scheme.
NOTE: For simplification, the over voltage protection circuitry was omitted.
36
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT SECTION FOR 1:1 & 1+1 REDUNDANCY
Backplane Interface
Primary Card
Line Interface Card
XRT83VL38
1:2
Tx
0.68F
T1/E1 Line
TxTSEL=1, Internal
Backup Card
XRT83VL38
Tx
0.68F
TxTSEL=1, Internal
RECEIVE 1:1 & 1+1 REDUNDANCY
For 1:1 and 1+1 redundancy, the receivers on the primary card should be programmed for Internal Impedance
mode. The receivers on the backup card should be programmed for External Impedance mode. Since there is
no external resistor in the circuit, the receivers on the backup card will be high impedance. This key design
feature eliminates the need for relays and provides one bill of materials for all interface modes of operation.
Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup
card to Internal Impedance mode, then the primary card to External Impedance mode. See Figure 17 for a
simplified block diagram of the receive section for a 1:1 and 1+1 redundancy scheme.
NOTE: For simplification, the over voltage protection circuitry was omitted.
FIGURE 17. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR 1:1 AND 1+1 REDUNDANCY
Backplane Interface
Primary Card
Line Interface Card
XRT83VL38
1:1
Rx
T1/E1 Line
RxTSEL=1, Internal
Backup Card
XRT83VL38
Rx
RxTSEL=0, External
37
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
N+1 REDUNDANCY
N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention,
external relays are necessary when using this redundancy scheme. The advantage of relays is that they create
complete isolation between the primary cards and the backup card. This allows all transmitters and receivers
on the primary cards to be configured in internal impedance mode, providing one bill of materials for all
interface modes of operation. The transmit and receive sections of the XRT83VL38 are described separately.
TRANSMIT
For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode
providing one bill of materials for T1/E1/J1. The transmitters on the backup card do not have to be tri-stated. To
swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. A
0.68F capacitor is used in series with TTIP for blocking DC bias. See Figure 18 for a simplified block diagram
of the transmit section for an N+1 redundancy scheme.
NOTE: For simplification, the over voltage protection circuitry was omitted.
FIGURE 18. SIMPLIFIED BLOCK DIAGRAM - TRANSMIT SECTION FOR N+1 REDUNDANCY
Backplane Interface
Primary Card
Line Interface Card
XRT83VL38
1:2
Tx
0.68F
T1/E1 Line
TxTSEL=1, Internal
Primary Card
XRT83VL38
1:2
Tx
T1/E1 Line
0.68F
TxTSEL=1, Internal
Primary Card
XRT83VL38
1:2
Tx
0.68F
T1/E1 Line
TxTSEL=1, Internal
Backup Card
XRT83VL38
Tx
0.68F
TxTSEL=1, Internal
38
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
RECEIVE
For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance mode.
The receivers on the backup card should be programmed for external impedance mode. Since there is no
external resistor in the circuit, the receivers on the backup card will be high impedance. Select the impedance
for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup card to internal
impedance mode, then the primary card to external impedance mode. See Figure 19. for a simplified block
diagram of the receive section for a N+1 redundancy scheme.
NOTE: For simplification, the over voltage protection circuitry was omitted.
FIGURE 19. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR N+1 REDUNDANCY
Backplane Interface
Primary Card
Line Interface Card
XRT83VL38
1:1
Rx
T1/E1 Line
RxTSEL=1, Internal
Primary Card
XRT83VL38
1:1
T1/E1 Line
Rx
RxTSEL=1, Internal
Primary Card
XRT83VL38
1:1
T1/E1 Line
Rx
RxTSEL=1, Internal
Backup Card
XRT83VL38
Rx
RxTSEL=1, External
39
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
PATTERN TRANSMIT AND DETECT FUNCTION
Several test and diagnostic patterns can be generated and detected by the chip. In Hardware mode each
channel can be independently programmed to transmit an All Ones pattern by applying a “High” level to the
corresponding TAOS_n pin. In Host mode, the three interface bits TXTEST[2:0] control the pattern generation
and detection independently for each channel according to Table 10.
TABLE 10: PATTERN TRANSMISSION CONTROL
TXTEST2
TXTEST1
TXTEST0
TEST PATTERN
0
x
x
None
1
0
0
TDQRSS
1
0
1
TAOS
1
1
0
TLUC
1
1
1
TLDC
TRANSMIT ALL ONES (TAOS)
This feature is available in both Hardware and Host modes. With the TAOS_n pin connected to a “High” level
or when interface bits TXTEST2=“1”, TXTEST1=“0” and TXTEST0=“1” the transmitter ignores input from
TPOS_n/TDATA_n and TNEG_n/CODES_n pins and sends a continuous AMI encoded all “Ones” signal to the
line, using TCLK_n clock as the reference. In addition, when the Hardware pin and interface bit ATAOS is
activated, the chip will automatically transmit the All “Ones” data from any channel that detects an RLOS
condition. This feature is not available on a per channel basis. TCLK_n must NOT be tied “Low”.
NETWORK LOOP CODE DETECTION AND TRANSMISSION
This feature is available in Host mode only. When the interface bits TXTEST2=”1”, TXTEST1=”1” and
TXTEST0=”0” the chip is enabled to transmit the “00001” Network Loop-Up Code from the selected channel
requesting a Loop-Back condition from the remote terminal. Simultaneously setting the interface bits
NLCDE1=”0” and NLCDE0=”1” enables the Network Loop-Up code detection in the receiver. If the “00001”
Network Loop-Up code is detected in the receive data for longer than 5 seconds, the NLCD bit in the interface
register is set indicating that the remote terminal has activated remote Loop-Back and the chip is receiving its
own transmitted data. When the interface bits TXTEST2=”1”, TXTEST1=”1” and TXTEST0=”1” the chip is
enabled to transmit the Network Loop-Down Code (TLDC) “001” from the selected channel requesting the
remote terminal the removal of the Loop-Back condition.
In the Host mode each channel is capable of monitoring the contents of the receive data for the presence of
Loop-Up or Loop-Down code from the remote terminal. In the Host mode the two interface bits NLCDE[1:0]
control the Loop-Code detection independently for each channel according to Table 11.
TABLE 11: LOOP-CODE DETECTION CONTROL
NLCDE1
NLCDE0
CONDITION
0
0
Disable Loop-Code Detection
0
1
Detect Loop-Up Code in Receive Data
1
0
Detect Loop-Down Code in Receive Data
1
1
Automatic Loop-Code detection and Remote Loop-Back Activation
Setting the interface bits to NLCDE1=”0” and NLCDE0=”1” activates the detection of the Loop-Up code in the
receive data. If the “00001” Network Loop-Up code is detected in the receive data for longer than 5 seconds,
the NLCD interface bit is set to “1” and stays in this state for as long as the receiver continues to receive the
40
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
Network Loop-Up Code. In this mode if the NLCD interrupt is enabled, the chip will initiate an interrupt on every
transition of NLCD. The host has the option to ignore the request from the remote terminal, or to respond to the
request and manually activate Remote Loop-Back. The host can subsequently activate the detection of the
Loop-Down Code by setting NLCDE1=”1” and NLCDE0=”0”. In this case, receiving the “001” Loop-Down Code
for longer than 5 seconds will set the NLCD bit to “1” and if the NLCD interrupt is enabled, the chip will initiate
an interrupt on every transition of NLCD. The host can respond to the request from the remote terminal and
remove Loop-Back condition. In the manual Network Loop-Up (NLCDE1=”0” and NLCDE0=”1”) and LoopDown (NLCDE1=”1” and NLCDE0=”0”) Code detection modes, the NLCD interface bit will be set to “1” upon
receiving the corresponding code in excess of 5 seconds in the receive data. The chip will initiate an interrupt
any time the status of the NLCD bit changes and the Network Loop-code interrupt is enabled.
In the Host mode, setting the interface bits NLCDE1=”1” and NLCDE0=”1” enables the automatic Loop-Code
detection and Remote Loop-Back activation mode if, TXTEST[2:0] is NOT equal to “110”. As this mode is
initiated, the state of the NLCD interface bit is reset to “0” and the chip is programmed to monitor the receive
input data for the Loop-Up Code. If the “00001” Network Loop-Up Code is detected in the receive data for
longer than 5 seconds in addition to the NLCD bit in the interface register being set, Remote Loop-Back is
automatically activated. The chip stays in remote Loop-Back even if it stops receiving the “00001” pattern. After
the chip detects the Loop-Up code, sets the NLCD bit and enters Remote Loop-Back, it automatically starts
monitoring the receive data for the Loop-Down code. In this mode however, the NLCD bit stays set even if the
receiver stops receiving the Loop-Up code, which is an indication to the host that the Remote Loop-Back is still
in effect. Remote Loop-Back is removed if the chip detects the “001” Loop-Down code for longer than 5
seconds. Detecting the “001” code also results in resetting the NLCD interface bit and initiating an interrupt.
The Remote Loop-Back can also be removed by taking the chip out of the Automatic detection mode by
programming it to operate in a different state. The chip will not respond to remote Loop-Back request if Local
Analog Loop-Back is activated locally. When programmed in Automatic detection mode the NLCD interface bit
stays “High” for the whole time the Remote Loop-Back is activated and initiates an interrupt any time the status
of the NLCD bit changes provided the Network Loop-code interrupt is enabled.
TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS)
Each channel of XRT83VL38 includes a QRSS pattern generation and detection block for diagnostic purposes
that can be activated only in the Host mode by setting the interface bits TXTEST2=”1”, TXTEST1=”0” and
TXTEST0=”0”. For T1 systems, the QRSS pattern is a 220-1pseudo-random bit sequence (PRBS) with no
more than 14 consecutive zeros. For E1 systems, the QRSS pattern is 215 -1 PRBS with an inverted output.
With QRSS and Analog Local Loop-Back enabled simultaneously, and by monitoring the status of the QRPD
interface bit, all main functional blocks within the transceiver can be verified.
When the receiver achieves QRSS synchronization with fewer than 4 errors in a 128 bits window, QRPD
changes from “Low” to “High”. After pattern synchronization, any bit error will cause QRPD to go “Low” for one
clock cycle. If the QRPDIE bit is enabled, any transition on the QRPD bit will generate an interrupt.
With TDQRSS activated, a bit error can be inserted in the transmitted QRSS pattern by transitioning the
INSBER interface bit from “0” to “1”. Bipolar violation can also be inserted either in the QRSS pattern, or input
data when operating in the single-rail mode by transitioning the INSBPV interface bit from “0” to “1”. The state
of INSBER and INSBPV bits are sampled on the rising edge of the TCLK_n. To insure the insertion of the bit
error or bipolar violation, a “0” should be written in these bit locations before writing a “1”.
41
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
LOOP-BACK MODES
The XRT83VL38 supports several Loop-Back modes under both Hardware and Host control. In Hardware
mode the two LOOP[1:0] pins control the Loop-Back functions for each channel independently according to
Table 12.
TABLE 12: LOOP-BACK CONTROL IN HARDWARE MODE
LOOP1
LOOP0
LOOP-BACK MODE
0
0
None
0
1
Analog
1
0
Remote
1
1
Digital
In Host mode the Loop-Back functions are controlled by the three LOOP[2:0] interface bits. Each channel can
be programmed independently according to Table 13.
TABLE 13: LOOP-BACK CONTROL IN HOST MODE
LOOP2
LOOP1
LOOP0
LOOP-BACK MODE
0
X
X
None
1
0
0
Dual
1
0
1
Analog
1
1
0
Remote
1
1
1
Digital
LOCAL ANALOG LOOP-BACK (ALOOP)
With Local Analog Loop-Back activated, the transmit data at TTIP and TRING are looped-back to the analog
input of the receiver. External inputs at RTIP/RRING in this mode are ignored while valid transmit data
continues to be sent to the line. Local Analog Loop-Back exercises most of the functional blocks of the
XRT83VL38 including the jitter attenuator which can be selected in either the transmit or receive paths. Local
Analog Loop-Back is shown in Figure 20.
FIGURE 20. LOCAL ANALOG LOOP-BACK SIGNAL FLOW
TPOS
TNEG
Encoder
TTIP
Timing
Control
JA
Tx
TRING
TCLK
RCLK
RPOS
Decoder
Data &
Clock
Recovery
RNEG
Rx
RTIP
RRING
In this mode, the jitter attenuator (if selected) can be placed in the transmit or receive path.
42
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REMOTE LOOP-BACK (RLOOP)
With Remote Loop-Back activated, receive data after the jitter attenuator (if selected in the receive path) is
looped back to the transmit path using RCLK as transmit timing. In this mode transmit clock and data are
ignored, while RCLK and receive data will continue to be available at their respective output pins. Remote
Loop-Back with jitter attenuator selected in the receive path is shown in Figure 21.
FIGURE 21. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN RECEIVE PATH
TPOS
TNEG
Timing
Control
Encoder
TTIP
Tx
TRING
TCLK
RCLK
RPOS
Decoder
Data &
Clock
Recovery
JA
RTIP
Rx
RRING
RNEG
In the Remote Loop-Back mode if the jitter attenuator is selected in the transmit path, the receive data from the
Clock and Data Recovery block is looped back to the transmit path and is applied to the jitter attenuator using
RCLK as transmit timing. In this mode the transmit clock and data are also ignored, while RCLK and received
data will continue to be available at their respective output pins. Remote Loop-Back with the jitter attenuator
selected in the transmit path is shown in Figure 22.
FIGURE 22. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH
TPOS
TNEG
Encoder
Timing
Control
JA
TTIP
Tx
TRING
TCLK
RCLK
RPOS
Clock &
Data
Recovery
Decoder
RNEG
43
RTIP
Rx
RRING
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
DIGITAL LOOP-BACK (DLOOP)
Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the
corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive
data and clock are ignored, but the transmit data will be sent to the line uninterrupted. This loop back feature
allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is
shown in Figure 23.
FIGURE 23. DIGITAL LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH
TPOS
TNEG
Encoder
Timing
Control
JA
TTIP
Tx
TRING
TCLK
RCLK
RPOS
Data &
Clock
Recovery
Decoder
RTIP
Rx
RRING
RNEG
DUAL LOOP-BACK
Figure 24 depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit
path will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the
recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without
passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator
to the RCLK and RPOS/RDATA and RNEG pins. For proper operation of Dual Loop-Back mode, TCLK must
be present.
FIGURE 24. SIGNAL FLOW IN DUAL LOOP-BACK MODE
TPOS
TNEG
Timing
Control
Encoder
TTIP
Tx
TRING
TCLK
JA
RCLK
RPOS
Data &
Clock
Recovery
Decoder
RNEG
44
RTIP
Rx
RRING
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MICROPROCESSOR PARALLEL INTERFACE
XRT83VL38 is equipped with a microprocessor interface for easy device configuration. The parallel port of the
XRT83VL38 is compatible with both Intel and Motorola address and data buses. The XRT83VL38 has an 8-bit
address A[7:0] input and 8-bit bi-directional data bus D[7:0]. The signals required for a generic microprocessor
to access the internal registers are described in Table 14.
TABLE 14: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION
D[7:0]
Data Input (Output): 8 bits bi-directional Read/Write data bus for register access.
A[7:0]
Address Input: 8 bit address to select internal register location.
PTS1
PTS2
Microprocessor Type Select:
PTS2
PTS1
P Type
0
0
Intel 8051 Asynchronous
0
1
Motorola Asynchronous
1
0
Power PC Synchronous
1
1
MPC8xx Motorola Synchronous
PCLK
Microprocessor Clock Input: Input clock for synchronous microprocessor operation. Maximum
clock speed is 54MHz. This pin is internally pulled “Low” for asynchronous microprocessor operation
when no clock is present.
ALE_AS
Address Latch Input (Address Strobe):
-Intel bus timing, the address inputs are latched into the internal register on the falling edge of ALE.
-Motorola bus timing, the address inputs are latched into the internal register on the falling edge of
AS.
CS
RD_DS
WR_R/W
Chip Select Input: This signal must be “Low” in order to access the parallel port.
Read Input (Data Strobe):
-Intel bus timing, a “Low” pulse on RD selects a read operation when CS pin is “Low”.
-Motorola bus timing, a “Low” pulse on DS indicates a read or write operation when CS pin is “Low”.
Write Input (Read/Write):
-Intel bus timing, a “Low” pulse on WR selects a write operation when CS pin is “Low”.
-Motorola bus timing, a “High” pulse on R/W selects a read operation and a “Low” pulse on R/W
selects a write operation when CS pin is “Low”.
RDY_DTACK
Ready Output (Data Transfer Acknowledge Output):
-Intel bus timing, RDY is asserted “High” to indicate the XRT83VL38 has completed a read or write
operation.
-Motorola bus timing, DTACK is asserted “Low” to indicate the XRT83VL38 has completed a read or
write operation.
INT
Interrupt Output: This pin is asserted “Low” to indicate an interrupt caused by an alarm condition in
the device status registers. The activation of this pin can be blocked by setting the GIE bit to “0” in the
Command Control register.
45
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
MICROPROCESSOR REGISTER TABLES
The microprocessor interface consists of 256 addressable locations. Each channel uses 16 dedicated 8 byte
registers for independent programming and control. There are four additional registers for global control of all
channels and two registers for device identification and revision numbers. The remaining registers are for
factory test and future expansion. The control register map and the function of the individual bits are
summarized in Table 15 and Table 16 respectively.
TABLE 15: MICROPROCESSOR REGISTER ADDRESS
REGISTER ADDRESS
REGISTER NUMBER
FUNCTION
HEX
BINARY
0 - 15
0x00 - 0x0F
00000000 - 00001111
Channel 0 Control Registers
16 - 31
0x10 -0x1F
00010000 - 00011111
Channel 1 Control Registers
32 - 47
0x20 - 0x2F
00100000 - 00101111
Channel 2 Control Registers
48 - 63
0x30 - 0x3F
00110000 - 00111111
Channel 3 Control Registers
64 - 79
0x40 - 0x4F
01000000 - 01001111
Channel 4 Control Registers
80 - 95
0x50 - 0x5F
01010000 - 01011111
Channel 5 Control Registers
96-111
0x60 - 0x6F
01100000 - 01101111
Channel 6 Control Registers
112 - 127
0x70 - 0x7F
01110000 - 01111111
Channel 7 Control Registers
128 - 131
0x80 - 0x83
10000000 - 10000011
Command Control registers for all 8 channels
132 -139
0x84 - 0x8B
10000100 - 10001011
R/W registers reserved for testing channels 0-3
140 - 191
0x8C - 0xBF
10001100 - 10111111
Reserved
192
0xC0
11000000
193 - 195
0xC1 - 0xC3
11000001 - 11000011
Reserved
196 - 203
0xC4 - 0xCB
11000100 - 11001011
R/W registers reserved for testing channels 4-7
204 - 253
0xCC - 0xFD
11001100 - 11111101
Reserved
254
0xFE
11111110
Device “ID”
255
0xFF
11111111
Device “Revision ID”
Command Control register for all 8 channels
TABLE 16: MICROPROCESSOR REGISTER BIT DESCRIPTION
REG. #
ADDRESS
REG.
TYPE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RXON_n
EQC4_n
EQC3_n
EQC2_n
EQC1_n
EQC0_n
Channel 0 Control Registers
0
00000000
Hex 0x00
R/W QRSS/PRBS PRBS_Rx/Tx
1
00000001
Hex 0x01
R/W
RXTSEL_n
TXTSEL_n
TERSEL1_n
TERSEL0_n
JASEL1_n
JASEL0_n
JABW_n
FIFOS_n
2
00000010
Hex 0x02
R/W
INVQRSS_n
TXTEST2_n
TXTEST1_n
TXTEST0_n
TXON_n
LOOP2_n
LOOP1_n
LOOP0_n
3
00000011
Hex 0x03
R/W
NLCDE1_n
NLCDE0_n
CODES_n
RXRES1_n
RXRES0_n
INSBPV_n
INSBER_n
Reserved
46
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 16: MICROPROCESSOR REGISTER BIT DESCRIPTION
REG.
TYPE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00000100
Hex 0x04
R/W
Reserved
DMOIE_n
FLSIE_n
LCVIE_n
NLCDIE_n
AISDIE_n
RLOSIE_n
QRPDIE_n
5
00000101
Hex 0x05
RO
Reserved
DMO_n
FLS_n
LCV_n
NLCD_n
AISD_n
RLOS_n
QRPD_n
6
00000110
Hex 0x06
RUR
Reserved
DMOIS_n
FLSIS_n
LCVIS_n
NLCDIS_n
AISDIS_n
RLOSIS_n
QRPDIS_n
7
00000111
Hex 0x07
RO
Reserved
Reserved
CLOS5_n
CLOS4_n
CLOS3_n
CLOS2_n
CLOS1_n
CLOS0_n
8
00001000
Hex 0x08
R/W
X
B6S1_n
B5S1_n
B4S1_n
B3S1_n
B2S1_n
B1S1_n
B0S1_n
9
00001001
Hex 0x09
R/W
X
B6S2_n
B5S2_n
B4S2_n
B3S2_n
B2S2_n
B1S2_n
B0S2_n
10
00001010
Hex 0x0A
R/W
X
B6S3_n
B5S3_n
B4S3_n
B3S3_n
B2S3_n
B1S3_n
B0S3_n
11
00001011
Hex 0x0B
R/W
X
B6S4_n
B5S4_n
B4S4_n
B3S4_n
B2S4_n
B1S4_n
B0S4_n
12
00001100
Hex 0x0C
R/W
X
B6S5_n
B5S5_n
B4S5_n
B3S5_n
B2S5_n
B1S5_n
B0S5_n
13
00001101
Hex 0x0D
R/W
X
B6S6_n
B5S6_n
B4S6_n
B3S6_n
B2S6_n
B1S6_n
B0S6_n
14
00001110
Hex 0x0E
R/W
X
B6S7_n
B5S7_n
B4S7_n
B3S7_n
B2S7_n
B1S7_n
B0S7_n
15
00001111
Hex 0x0F
R/W
X
B6S8_n
B5S8_n
B4S8_n
B3S8_n
B2S8_n
B1S8_n
B0S8_n
Reset = 0
Reset = 0
Reset = 0
Reset = 0
Reset = 0
Reset = 0
Reset = 0
Reset = 0
REG. #
ADDRESS
4
Command Control Global Registers for all 8 channels
16-31
0001xxxx
Hex 0x100x1F
R/W Channel 1Control Register (see Registers 0-15 for description)
32-47
0010xxxx
Hex 0x20ox2F
R/W Channel 2 Control Register (see Registers 0-15 for description)
48-63
0011xxxx
Hex 0x300x3F
R/W Channel 3 Control Register (see Registers 0-15 for description)
64-79
0100xxxx
Hex 0x400x4F
R/W Channel 4 Control Register (see Registers 0-15 for description)
80-95
0101xxxx
Hex 0x500x5F
R/W Channel 5 Control Register (see Registers 0-15 for description)
96-111
0110xxxx
Hex 0x600x6F
R/W Channel 6 Control Register (see Registers 0-15 for description)
112-127
0111xxxx
Hex 0x700x7F
R/W Channel 7 Control Register (see Registers 0-15 for description)
Command Control Registers for All 8 Channels
47
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 16: MICROPROCESSOR REGISTER BIT DESCRIPTION
REG.
TYPE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
10000000
Hex 0x80
R/W
SR/DR
ATAOS
RCLKE
TCLKE
DATAP
Reserved
GIE
SRESET
129
10000001
Hex 0x81
R/W
Reserved
CLKSEL2
CLKSEL1
CLKSEL0
MCLKRATE
RXMUTE
EXLOS
ICT
130
10000010
Hex 0x82
R/W
TXONCNTL
TERCNTL
Reserved
Reserved
131
10000011
Hex 0x83
R/W
GAUGE1
GAUGE0
Reserved
Reserved
SL_1
SL_0
EQG_1
EQG_0
Reserved
Reserved
Reserved
Reserved
Reserved
E1Arben
REG. #
ADDRESS
128
Reserved
Test Registers for channels 0 - 3
132
10000100
R/W Test byte 0
133
10000101
R/W Test byte 1
134
10000110
R/W Test byte 2
135
10000111
R/W Test byte 3
136
10001000
R/W Test byte 4
137
10001001
R/W Test byte 5
138
10001010
R/W Test byte 6
139
10001011
R/W Test byte 7
Unused Registers
140-191
100011xx
Command Control Register for All 8 Channels
192
11000000
Hex 0xC0
R/W
Reserved
Reserved
Unused Registers
193-195
110000xx
Test Registers for channels 4 - 7
196
11000100
R/W Test byte 0
197
11000101
R/W Test byte 0
198
11000110
R/W Test byte 0
199
11000111
R/W Test byte 0
200
11001000
R/W Test byte 0
201
11001001
R/W Test byte 0
202
11001010
R/W Test byte 0
203
11001011
R/W Test byte 0
Unused Registers
204
11001100
….
253
11111101
ID Registers
48
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 16: MICROPROCESSOR REGISTER BIT DESCRIPTION
REG.
TYPE
REG. #
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
254
11111110
Hex 0xFE
RO
DEVICE ID hex: FD - Binary 11101010 (0xEA)
255
11111111
Hex 0xFF
RO
DEVICE “Revision ID”
49
BIT 3
BIT 2
BIT 1
BIT 0
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
MICROPROCESSOR REGISTER DESCRIPTIONS
TABLE 17: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION
REGISTER ADDRESS
00000000
00010000
00100000
00110000
01000000
01010000
01100000
01110000
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
0
D7
QRSS/PRBS QRSS/PRBS Select Bit
This bit selects between QRSS and PRBS.
1 = QRSS
0 = PRBS
R/W
D6
PRBS_Rx/Tx PRBS Receive/Transmit Select:
This bit is used to select where the output of the PRBS Generator is directed if PRBS generation is enabled.
0 = Normal Operation - PRBS generator is output on TTIP and
TRING if PRBS generation is enabled.
1 = PRBS Generator is output on RPOS; RNEG is internally
grounded, if PRBS generation is enabled.
R/W
NOTE: If PRBS generation is disabled (see TxTEST[2:0]), user
should set this bit to ’0’ for normal operation.
D5
RXON_n
Receiver ON: Writing a “1” into this bit location turns on the
Receive Section of channel n. Writing a “0” shuts off the
Receiver Section of channel n.
R/W
0
R/W
0
NOTES:
1. This bit provides independent turn-off or turn-on
control of each receiver channel.
2. In Hardware mode all receiver channels are always
on in the TQFP package. In the BGA packace all
receiver channels can be turned on or off together by
applying the appropriate signal to the RXON pin (#
K16).
D4
EQC4_n
Equalizer Control bit 4: This bit together with EQC[3:0] are
used for controlling transmit pulse shaping, transmit line buildout (LBO) and receive monitoring for either T1 or E1 Modes of
operation.
See Table 5 for description of Equalizer Control bits.
D3
EQC3_n
Equalizer Control bit 3: See bit D4 description for function of
this bit
R/W
0
D2
EQC2_n
Equalizer Control bit 2: See bit D4 description for function of
this bit
R/W
0
50
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 17: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION
D1
EQC1_n
Equalizer Control bit 1: See bit D4 description for function of
this bit
R/W
0
D0
EQC0_n
Equalizer Control bit 0: See bit D4 description for function of
this bit
R/W
0
51
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 18: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION
REGISTER ADDRESS
00000001
00010001
00100001
00110001
01000001
01010001
01100001
01110001
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
RXTSEL_n
D6
D5
TXTSEL_n
FUNCTION
Receiver Termination Select: In Host mode, this bit is used
to select between the internal and external line termination
modes for the receiver according to the following table;
RXTSEL
RX Termination
0
External
1
Internal
Transmit Termination Select: In Host mode, this bit is used
to select between the internal and external line termination
modes for the transmitter according to the following table;
TXTSEL
TX Termination
0
External
1
Internal
TERSEL1_n Termination Impedance Select1:
In Host mode and in internal termination mode, (TXTSEL = “1”
and RXTSEL = “1”) TERSEL[1:0] control the transmit and
receive termination impedance according to the following
table;
TERSEL1 TERSEL0
REGISTER
TYPE
RESET
VALUE
R/W
0
R/W
0
R/W
0
R/W
0
Termination
0
0
100
0
1
110
1
0
75
1
1
120
In the internal termination mode, the receiver termination of
each receiver is realized completely by internal resistors or by
the combination of internal and one fixed external resistor.
In the internal termination mode, the transmitter output should
be AC coupled to the transformer.
D4
TERSEL0_n Termination Impedance Select bit 0:
52
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 18: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION
D3
JASEL1_n
Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits
are used to disable or place the jitter attenuator of each channel independently in the transmit or receive path.
JASEL1
bit D3
JASEL0
bit D2
0
0
JA Disabled
0
1
JA in Transmit Path
1
0
JA in Receive Path
1
1
JA in Receive Path
R/W
0
JA Path
D2
JASEL0_n
Jitter Attenuator select bit 0: See description of bit D3 for the
function of this bit.
R/W
0
D1
JABW_n
Jitter Attenuator Bandwidth Select: In E1 mode, set this bit
to “1” to select a 1.5Hz Bandwidth for the Jitter Attenuator. The
FIFO length will be automatically set to 64 bits. Set this bit to
“0” to select 10Hz Bandwidth for the Jitter Attenuator in E1
mode. In T1 mode the Jitter Attenuator Bandwidth is permanently set to 3Hz, and the state of this bit has no effect on the
Bandwidth.
R/W
0
R/W
0
D0
FIFOS_n
Mode
JABW
bit D1
FIFOS_n
bit D0
JA B-W
Hz
FIFO
Size
T1
0
0
3
32
T1
0
1
3
64
T1
1
0
3
32
T1
1
1
3
64
E1
0
0
10
32
E1
0
1
10
64
E1
1
0
1.5
64
E1
1
1
1.5
64
FIFO Size Select: See table of bit D1 above for the function of
this bit.
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TABLE 19: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION
REGISTER ADDRESS
00000010
00010010
00100010
00110010
01000010
01010010
01100010
01110010
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
D7
INVQRSS_n Invert QRSS Pattern: When TQRSS is active, Writing a “1” to
this bit inverts the polarity of transmitted QRSS pattern. Writing
a “0” sends the QRSS pattern with no inversion.
R/W
0
D6
TXTEST2_n Transmit Test Pattern bit 2: This bit together with TXTEST1
and TXTEST0 are used to generate and transmit test patterns
according to the following table:
R/W
0
R/W
0
TXTEST2
TXTEST1
TXTEST0
Test Pattern
0
X
X
No Pattern
1
0
0
TDQRSS
1
0
1
TAOS
1
1
0
TLUC
1
1
1
TLDC
TDQRSS (Transmit/Detect Quasi-Random Signal): This
condition when activated enables Quasi-Random Signal
Source generation and detection for the selected channel
number n. In a T1 system QRSS pattern is a 220-1 pseudorandom bit sequence (PRBS) with no more than 14 consecutive zeros. In a E1 system, QRSS is a 215-1 PRBS pattern.
TAOS (Transmit All Ones): Activating this condition enables
the transmission of an All Ones Pattern from the selected
channel number n.
TLUC (Transmit Network Loop-Up Code): Activating this
condition enables the Network Loop-Up Code of “00001” to be
transmitted to the line for the selected channel number n.
When Network Loop-Up code is being transmitted, the
XRT83VL38 will ignore the Automatic Loop-Code detection
and Remote Loop-Back activation (NLCDE1 =“1”, NLCDE0
=“1”, if activated) in order to avoid activating Remote Digital
Loop-Back automatically when the remote terminal responds
to the Loop-Back request.
TLDC (Transmit Network Loop-Down Code): Activating this
condition enables the network Loop-Down Code of “001” to be
transmitted to the line for the selected channel number n.
D5
TXTEST1_n Transmit Test pattern bit 1: See description of bit D6 for the
function of this bit.
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TABLE 19: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION
D4
TXTEST0_n Transmit Test Pattern bit 0: See description of bit D6 for the
function of this bit.
D3
TXON_n
Transmitter ON: Writing a “1” into this bit location turns on the
Transmit and Receive Sections of channel n. Writing a “0”
shuts off the Transmit Section of channel n. In this mode,
TTIP_n and TRING_n driver outputs will be tri-stated for power
reduction or redundancy applications.
D2
LOOP2_n
Loop-Back control bit 2: This bit together with the LOOP1
and LOOP0 bits control the Loop-Back modes of the chip
according to the following table:
LOOP2
LOOP1
LOOP0
0
X
X
No Loop-Back
1
0
0
Dual Loop-Back
1
0
1
Analog Loop-Back
1
1
0
Remote Loop-Back
1
1
1
Digital Loop-Back
R/W
0
R/W
0
Loop-Back Mode
D1
LOOP1_n
Loop-Back control bit 1: See description of bit D2 for the
function of this bit.
R/W
0
D0
LOOP0_n
Loop-Back control bit 0: See description of bit D2 for the
function of this bit.
R/W
0
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TABLE 20: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION
REGISTER ADDRESS
00000011
00010011
00100011
00110011
01000011
01010011
01100011
01110011
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
NLCDE1_n
FUNCTION
Network Loop Code Detection Enable Bit 1:
This bit together with NLCDE0_n control the Loop-Code detection of each channel.
NLCDE1
NLCDE0
0
0
0
1
1
0
1
1
REGISTER
TYPE
RESET
VALUE
R/W
0
Function
Disable Loop-code
detection
Detect Loop-Up code
in receive data
Detect Loop-Down
code in receive data
Automatic Loop-Code
detection
When NLCDE1 =”0” and NLCDE0 = “1” or NLCDE1 = “1” and
NLCDE0 = “0”, the chip is manually programmed to monitor
the receive data for the Loop-Up or Loop-Down code respectively.When the presence of the “00001” or “001” pattern is
detected for more than 5 seconds, the status of the NLCD bit is
set to “1” and if the NLCD interrupt is enabled, an interrupt is
initiated.The Host has the option to control the Loop-Back
function manually.
Setting the NLCDE1 = “1” and NLCDE0 = “1” enables the
Automatic Loop-Code detection and Remote Loop-Back activation mode. As this mode is initiated, the state of the NLCD
interface bit is reset to “0” and the chip is programmed to monitor the receive data for the Loop-Up code. If the “00001” pattern is detected for longer than 5 seconds, the NLCD bit is set
“1”, Remote Loop-Back is activated and the chip is automatically programmed to monitor the receive data for the LoopDown code. The NLCD bit stays set even after the chip stops
receiving the Loop-Up code. The Remote Loop-Back condition
is removed when the chip receives the Loop-Down code for
more than 5 seconds or if the Automatic Loop-Code detection
mode is terminated.
D6
NLCDE0_n
Network Loop Code Detection Enable Bit 0:
See description of D7 for function of this bit.
R/W
0
D5
CODES_n
Encoding and Decoding Select:
Writing a “0” to this bits selects HDB3 or B8ZS encoding and
decoding for channel number n. Writing “1” selects an AMI
coding scheme. This bit is only active when single rail mode is
selected.
R/W
0
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TABLE 20: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION
D4
RXRES1_n
Receive External Resistor Control Pin 1: In Host mode, this bit
along with the RXRES0_n bit selects the value of the external
Receive fixed resistor according to the following table;
RX RES 1_n
RX RES 0_n
R equired Fixed E xternal
RX Resistor
0
0
No external Fixed
Resistor
0
1
240 
1
0
210 
1
1
150 
R/W
0
D3
RXRES0_n
Receive External Resistor Control Pin 0: For function of this
bit see description of D4 the RXRES1_n bit.
R/W
0
D2
INSBPV_n
Insert Bipolar Violation: When this bit transitions from “0” to
“1”, a bipolar violation is inserted in the transmitted data
stream of the selected channel number n. Bipolar violation can
be inserted either in the QRSS pattern, or input data when
operating in single-rail mode. The state of this bit is sampled
on the rising edge of the respective TCLK_n.
R/W
0
R/W
0
R/W
0
REGISTER
TYPE
RESET
VALUE
RO
0
R/W
0
NOTE: To ensure the insertion of a bipolar violation, a “0”
should be written in this bit location before writing a
“1”.
D1
INSBER_n
Insert Bit Error: With TDQRSS enabled, when this bit transitions from “0” to “1”, a bit error will be inserted in the transmitted QRSS pattern of the selected channel number n. The state
of this bit is sampled on the rising edge of the respective
TCLK_n.
NOTE: To ensure the insertion of bit error, a “0” should be
written in this bit location before writing a “1”.
D0
Reserved
Reserved
TABLE 21: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION
REGISTER ADDRESS
00000100
00010100
00100100
00110100
01000100
01010100
01100100
01110100
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
Reserved
D6
DMOIE_n
FUNCTION
DMO Interrupt Enable: Writing a “1” to this bit enables DMO
interrupt generation, writing a “0” masks it.
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TABLE 21: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION
D5
FLSIE_n
FIFO Limit Status Interrupt Enable: Writing a “1” to this bit
enables interrupt generation when the FIFO limit is within to 3
bits, writing a “0” to masks it.
R/W
0
D4
LCVIE_n
Line Code Violation Interrupt Enable: Writing a “1” to this bit
enables Line Code Violation interrupt generation, writing a “0”
masks it.
R/W
0
D3
NLCDIE_n
Network Loop-Code Detection Interrupt Enable: Writing a
“1” to this bit enables Network Loop-code detection interrupt
generation, writing a “0” masks it.
R/W
0
D2
AISDIE_n
AIS Interrupt Enable: Writing a “1” to this bit enables Alarm
Indication Signal detection interrupt generation, writing a “0”
masks it.
R/W
0
D1
RLOSIE_n
Receive Loss of Signal Interrupt Enable: Writing a “1” to this
bit enables Loss of Receive Signal interrupt generation, writing
a “0” masks it.
R/W
0
D0
QRPDIE_n
QRSS Pattern Detection Interrupt Enable: Writing a “1” to
this bit enables QRSS pattern detection interrupt generation,
writing a “0” masks it.
R/W
0
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TABLE 22: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION
REGISTER ADDRESS
00000101
00010101
00100101
00110101
01000101
01010101
01100101
01110101
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
Reserved
D6
DMO_n
D5
D4
REGISTER
TYPE
RESET
VALUE
RO
0
Driver Monitor Output: This bit is set to a “1” to indicate
transmit driver failure is detected. The value of this bit is based
on the current status of DMO for the corresponding channel. If
the DMOIE bit is enabled, any transition on this bit will generate an Interrupt.
RO
0
FLS_n
FIFO Limit Status: This bit is set to a “1” to indicate that the jitter attenuator read/write FIFO pointers are within +/- 3 bits. If
the FLSIE bit is enabled, any transition on this bit will generate
an Interrupt.
RO
0
LCV_n
Line Code Violation: This bit is set to a “1” to indicate that the
receiver of channel n is currently detecting a Line Code Violation or an excessive number of zeros in the B8ZS or HDB3
modes. If the LCVIE bit is enabled, any transition on this bit will
generate an Interrupt.
RO
0
FUNCTION
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TABLE 22: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION
D3
NLCD_n
Network Loop-Code Detection:
This bit operates differently in the Manual or the Automatic
Network Loop-Code detection modes.
In the Manual Loop-Code detection mode, (NLCDE1 = “0”
and NLCDE0 = “1” or NLCDE1 = “1” and NLCDE0 = “0”) this
bit gets set to “1” as soon as the Loop-Up (“00001”) or LoopDown (“001”) code is detected in the receive data for longer
than 5 seconds. The NLCD bit stays in the “1” state for as long
as the chip detects the presence of the Loop-code in the
receive data and it is reset to “0” as soon as it stops receiving
it. In this mode, if the NLCD interrupt is enabled, the chip will
initiate an interrupt on every transition of the NLCD.
When the Automatic Loop-code detection mode, (NLCDE1
= “1” and NLCDE0 =”1”) is initiated, the state of the NLCD
interface bit is reset to “0” and the chip is programmed to monitor the receive input data for the Loop-Up code. This bit is set
to a “1” to indicate that the Network Loop Code is detected for
more than 5 seconds. Simultaneously the Remote Loop-Back
condition is automatically activated and the chip is programmed to monitor the receive data for the Network Loop
Down code. The NLCD bit stays in the “1” state for as long as
the Remote Loop-Back condition is in effect even if the chip
stops receiving the Loop-Up code. Remote Loop-Back is
removed if the chip detects the “001” pattern for longer than 5
seconds in the receive data.Detecting the “001” pattern also
results in resetting the NLCD interface bit and initiating an
interrupt provided the NLCD interrupt enable bit is active.
When programmed in Automatic detection mode, the
NLCD interface bit stays “High” for the entire time the Remote
Loop-Back is active and initiate an interrupt anytime the status
of the NLCD bit changes. In this mode, the Host can monitor
the state of the NLCD bit to determine if the Remote LoopBack is activated.
RO
0
D2
AISD_n
Alarm Indication Signal Detect: This bit is set to a “1” to indicate All Ones Signal is detected by the receiver. The value of
this bit is based on the current status of Alarm Indication Signal
detector of channel n. If the AISDIE bit is enabled, any transition on this bit will generate an Interrupt.
RO
0
D1
RLOS_n
Receive Loss of Signal: This bit is set to a “1” to indicate that
the receive input signal is lost. The value of this bit is based on
the current status of the receive input signal of channel n. If the
RLOSIE bit is enabled, any transition on this bit will generate
an Interrupt.
RO
0
D0
QRPD_n
Quasi-random Pattern Detection: This bit is set to a “1” to
indicate the receiver is currently in synchronization with QRSS
pattern. The value of this bit is based on the current status of
Quasi-random pattern detector of channel n. If the QRPDIE bit
is enabled, any transition on this bit will generate an Interrupt.
RO
0
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TABLE 23: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION
REGISTER ADDRESS
00000110
00010110
00100110
00110110
01000110
01010110
01100110
01110110
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
Reserved
D6
DMOIS_n
FUNCTION
Driver Monitor Output Interrupt Status: This bit is set to a
“1” every time the DMO status has changed since last read.
REGISTER
TYPE
RESET
VALUE
RO
0
RUR
0
RUR
0
RUR
0
RUR
0
RUR
0
RUR
0
RUR
0
NOTE: This bit is reset upon read.
D5
FLSIS_n
FIFO Limit Interrupt Status: This bit is set to a “1” every time
when FIFO Limit (Read/Write pointer with +/- 3 bits apart) status has changed since last read.
NOTE: This bit is reset upon read.
D4
LCVIS_n
Line Code Violation Interrupt Status: This bit is set to a “1”
every time when LCV status has changed since last read.
NOTE: This bit is reset upon read.
D3
NLCDIS_n
Network Loop-Code Detection Interrupt Status: This bit is
set to a “1” every time when NLCD status has changed since
last read.
NOTE: This bit is reset upon read.
D2
AISDIS_n
AIS Detection Interrupt Status: This bit is set to a “1” every
time when AISD status has changed since last read.
NOTE: This bit is reset upon read.
D1
RLOSIS_n
Receive Loss of Signal Interrupt Status: This bit is set to a
“1” every time RLOS status has changed since last read.
NOTE: This bit is reset upon read.
D0
QRPDIS_n
Quasi-Random Pattern Detection Interrupt Status: This bit
is set to a “1” every time when QRPD status has changed
since last read.
NOTE: This bit is reset upon read.
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TABLE 24: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION
REGISTER ADDRESS
00000111
00010111
00100111
00110111
01000111
01010111
01100111
01110111
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
REGISTER
TYPE
RESET
VALUE
Reserved
RO
0
D6
Reserved
RO
0
D5
CLOS5_n
Cable Loss bit 5: CLOS[5:0]_n are the six bit receive selective equalizer setting which is also a binary word that represents the cable attenuation indication within ±1dB. CLOS5_n
is the most significant bit (MSB) and CLOS0_n is the least significant bit (LSB).
RO
0
D4
CLOS4_n
Cable Loss bit 4: See description of D5 for function of this bit.
RO
0
D3
CLOS3_n
Cable Loss bit 3: See description of D5 for function of this bit.
RO
0
D2
CLOS2_n
Cable Loss bit 2: See description of D5 for function of this bit.
RO
0
D1
CLOS1_n
Cable Loss bit 1: See description of D5 for function of this bit.
RO
0
D0
CLOS0_n
Cable Loss bit 0: See description of D5 for function of this bit.
RO
0
FUNCTION
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TABLE 25: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION
REGISTER ADDRESS
00001000
00011000
00101000
00111000
01001000
01011000
01101000
01111000
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
Reserved
D6-D0
B6S1_n B0S1_n
FUNCTION
Arbitrary Transmit Pulse Shape, Segment 1:The shape of
each channel's transmitted pulse can be made independently
user programmable by selecting “Arbitrary Pulse” mode in
Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of
MCLK.
This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the first time segment. B6S1_nB0S1_n is in signed magnitude format with B6S1_n as the
sign bit and B0S1_n as the least significant bit (LSB).
REGISTER
TYPE
RESET
VALUE
R/W
0
R/W
0
REGISTER
TYPE
RESET
VALUE
R/W
0
R/W
0
TABLE 26: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION
REGISTER ADDRESS
00001001
00011001
00101001
00111001
01001001
01011001
01101001
01111001
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
Reserved
D6-D0
B6S2_n B0S2_n
FUNCTION
Arbitrary Transmit Pulse Shape, Segment 2
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the second time segment. B6S2_nB0S2_n is in signed magnitude format with B6S2_n as the
sign bit and B0S2_n as the least significant bit (LSB).
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TABLE 27: MICROPROCESSOR REGISTER #10, BIT DESCRIPTION
REGISTER ADDRESS
00001010
00011010
00101010
00111010
01001010
01011010
01101010
01111010
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
Reserved
D6-D0
B6S3_n B0S3_n
FUNCTION
Arbitrary Transmit Pulse Shape, Segment 3
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the third time segment. B6S3_nB0S3_n is in signed magnitude format with B6S3_n as the
sign bit and B0S3_n as the least significant bit (LSB).
REGISTER
TYPE
RESET
VALUE
R/W
0
R/W
0
REGISTER
TYPE
RESET
VALUE
R/W
0
R/W
0
TABLE 28: MICROPROCESSOR REGISTER #11, BIT DESCRIPTION
REGISTER ADDRESS
00001011
00011011
00101011
00111011
01001011
01011011
01101011
01111011
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
Reserved
D6-D0
B6S4_n B0S4_n
FUNCTION
Arbitrary Transmit Pulse Shape, Segment 4
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the fourth time segment. B6S4_nB0S4_n is in signed magnitude format with B6S4_n as the
sign bit and B0S4_n as the least significant bit (LSB).
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TABLE 29: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION
REGISTER ADDRESS
00001100
00011100
00101100
00111100
01001100
01011100
01101100
01111100
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
Reserved
D6-D0
B6S5_n B0S5_n
FUNCTION
Arbitrary Transmit Pulse Shape, Segment 5
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the fifth time segment. B6S5_nB0S5_n is in signed magnitude format with B6S5_n as the
sign bit and B0S5_n as the least significant bit (LSB).
REGISTER
TYPE
RESET
VALUE
R/W
0
R/W
0
REGISTER
TYPE
RESET
VALUE
R/W
0
R/W
0
TABLE 30: MICROPROCESSOR REGISTER #13, BIT DESCRIPTION
REGISTER ADDRESS
00001101
00011101
00101101
00111101
01001101
01011101
01101101
01111101
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
Reserved
D6-D0
B6S6_n B0S6_n
FUNCTION
Arbitrary Transmit Pulse Shape, Segment 6
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the sixth time segment. B6S6_nB0S6_n is in signed magnitude format with B6S6_n as the
sign bit and B0S6_n as the least significant bit (LSB).
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TABLE 31: MICROPROCESSOR REGISTER #14, BIT DESCRIPTION
REGISTER ADDRESS
00001110
00011110
00101110
00111110
01001110
01011110
01101110
01111110
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
Reserved
D6-D0
B6S7_n B0S7_n
FUNCTION
Arbitrary Transmit Pulse Shape, Segment 7
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the seventh time segment.
B6S7_n-B0S7_n is in signed magnitude format with B6S7_n
as the sign bit and B0S7_n as the least significant bit (LSB).
REGISTER
TYPE
RESET
VALUE
R/W
0
R/W
0
REGISTER
TYPE
RESET
VALUE
R/W
0
R/W
0
TABLE 32: MICROPROCESSOR REGISTER #15, BIT DESCRIPTION
REGISTER ADDRESS
00001111
00011111
00101111
00111111
01001111
01011111
01101111
01111111
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
BIT #
NAME
D7
Reserved
D6-D0
B6S8_n B0S8_n
FUNCTION
Arbitrary Transmit Pulse Shape, Segment 8
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the eighth time segment. B6S8_nB0S8_n is in signed magnitude format with B6S8_n as the
sign bit and B0S8_n as the least significant bit (LSB).
66
XRT83VL38
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OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 33: MICROPROCESSOR REGISTER #128, BIT DESCRIPTION
REGISTER ADDRESS
10000000
REGISTER
TYPE
RESET
VALUE
Single-rail/Dual-rail Select: Writing a “1” to this bit configures
all 8 channels in the XRT83VL38 to operate in the Single-rail
mode.
Writing a “0” configures the XRT83VL38 to operate in Dual-rail
mode.
R/W
0
ATAOS
Automatic Transmit All Ones Upon RLOS: Writing a “1” to
this bit enables the automatic transmission of All "Ones" data
to the line for the channel that detects an RLOS condition.
Writing a “0” disables this feature.
R/W
0
D5
RCLKE
Receive Clock Edge: Writing a “1” to this bit selects receive
output data of all channels to be updated on the negative edge
of RCLK.
Wring a “0” selects data to be updated on the positive edge of
RCLK.
R/W
0
D4
TCLKE
Transmit Clock Edge: Writing a “0” to this bit selects transmit
data at TPOS_n/TDATA_n and TNEG_n/CODES_n of all
channels to be sampled on the falling edge of TCLK_n.
Writing a “1” selects the rising edge of the TCLK_n for sampling.
R/W
0
D3
DATAP
DATA Polarity: Writing a “0” to this bit selects transmit input
and receive output data of all channels to be active “High”.
Writing a “1” selects an active “Low” state.
R/W
0
D2
Reserved
D1
GIE
D0
SRESET
NAME
FUNCTION
D7
SR/DR
D6
BIT #
0
Global Interrupt Enable: Writing a “1” to this bit globally
enables interrupt generation for all channels.
Writing a “0” disables interrupt generation.
R/W
0
Software Reset P Registers: Writing a “1” to this bit longer
than 10µs initiates a device reset through the microprocessor
interface. All internal circuits are placed in the reset state with
this bit set to a “1” except the microprocessor register bits.
R/W
0
67
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OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
CLOCK SELECT REGISTER
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits and
the Master Clock Rate in register 0x81h. Therefore, if the clock selection bits or the MCLRATE bit are being
programmed, the frequency of the PLL output will be adjusted accordingly. During this adjustment, it is
important to "Not" write to any other bit location within the same register while selecting the input/output clock
frequency. For best results, register 0x81h can be broken down into two sub-registers with the MSB being bits
D[7:3] and the LSB being bits D[2:0] as shown in Figure 25. Note: Bit D[7] is a reserved bit.
FIGURE 25. REGISTER 0X81H SUB REGISTERS
MSB
D7
D6
D5
LSB
D4
D3
Clock Selection Bits
D2
D1
D0
ExLOS, ICT
Programming Examples:
Example 1: Changing bits D[7:3]
If bits D[7:3] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 2: Changing bits D[2:0]
If bits D[2:0] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 3: Changing bits within the MSB and LSB
In this scenario, one must initiate TWO write operations such that the MSB and LSB do not change within ONE
write cycle. It is recommended that the MSB and LSB be treated as two independent sub-registers. One can
either change the clock selection (MSB) and then change bits D[2:0] (LSB) on the SECOND write, or viceversa. No order or sequence is necessary.
TABLE 34: MICROPROCESSOR REGISTER #129, BIT DESCRIPTION
REGISTER ADDRESS
10000001
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
R/W
0
BIT #
D7
Reserved
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OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 34: MICROPROCESSOR REGISTER #129, BIT DESCRIPTION
D6
CLKSEL2
Clock Select Inputs for Master Clock Synthesizer bit 2:
In Host mode, CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be used to generate a master clock from an external accurate clock source according to
the following table;
MCLKE1
kHz
MCLKT1
kHz
CLKSEL 2
CLKSEL1
CLKSEL0
MCLKRATE
R/W
0
CLKOUT
kHz
2048
2048
0
0
0
0
2048
2048
2048
0
0
0
1
1544
2048
1544
0
0
0
0
2048
1544
1544
0
0
1
1
1544
1544
1544
0
0
1
0
2048
2048
1544
0
0
1
1
1544
In Hardware mode, the state of these signals are ignored and
the master frequency PLL is controlled by the corresponding
Hardware pins.
D5
CLKSEL1
Clock Select inputs for Master Clock Synthesizer bit 1:
See description of bit D6 for function of this bit.
R/W
0
D4
CLKSEL0
Clock Select inputs for Master Clock Synthesizer bit 0:
See description of bit D6 for function of this bit.
R/W
0
D3
MCLKRATE
Master clock Rate Select: The state of this bit programs the
Master Clock Synthesizer to generate the T1/J1 or E1 clock.
The Master Clock Synthesizer will generate the E1 clock when
MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE =
“1”.
R/W
0
D2
RXMUTE
Receive Output Mute: Writing a “1” to this bit, mutes receive
outputs at RPOS/RDATA and RNEG/LCV pins to a “0” state for
any channel that detects an RLOS condition.
R/W
0
NOTE: RCLK is not muted.
D1
EXLOS
Extended LOS: Writing a “1” to this bit extends the number of
zeros at the receive input of each channel before RLOS is
declared to 4096 bits. Writing a “0” reverts to the normal mode
(175+75 bits for T1 and 32 bits for E1).
R/W
0
D0
ICT
In-Circuit-Testing: Writing a “1” to this bit configures all the
output pins of the chip in high impedance mode for In-CircuitTesting. Setting the ICT bit to “1” is equivalent to connecting
the Hardware ICT pin 88 to ground.
R/W
0
REGISTER
TYPE
RESET
VALUE
R/W
0
TABLE 35: MICROPROCESSOR REGISTER #130, BIT DESCRIPTION
REGISTER ADDRESS
10000010
NAME
FUNCTION
TXONCNTL
Transmit On Control:
In Host mode, setting this bit to “1” transfers the control of the
Transmit On/Off function to the TXON_n Hardware control
pins.
BIT #
D7
NOTE: This provides a faster On/Off capability for redundancy
application.
69
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 35: MICROPROCESSOR REGISTER #130, BIT DESCRIPTION
D6
TERCNTL
Termination Control.
In Host mode, setting this bit to “1” transfers the control of the
RXTSEL to the RXTSEL Hardware control pin.
R/W
0
REGISTER
TYPE
RESET
VALUE
R/W
0
R/W
0
NOTE: This provides a faster On/Off capability for redundancy
application.
D5-D0
Reserved
TABLE 36: MICROPROCESSOR REGISTER #131, BIT DESCRIPTION
REGISTER ADDRESS
10000011
NAME
FUNCTION
GAUGE1
Wire Gauge Selector Bit 1:
This bit together with bit D6 are used to select wire gauge size
as shown in the table below.
BIT #
D7
D6
GAUGE0
GAUGE1
GAUGE0
Wire Size
0
0
22 and 24 Gauge
0
1
22 Gauge
1
0
24 Gauge
1
1
26 Gauge
Wire Gauge Selector Bit 0:
See bit D7.
D5
TxSYNC(Sect G.703 Section 13 Transmit Pulse
13)
When this bit is set to ’1’, the LIU transmitter will send the E1
synchrnonous waveform as described in Section 13 of ITU-T
G.703. This register bit takes priority over every other LIU setting on the transmit path.
0 = Normal E1 pulse
1 = Section 13 Synchronous Pulse
R/W
0
D4
RxSYNC(Sect G.703 Section 13 Receiver
13)
When this bit is set to ’1’, the CDR block of the receiver is configured to accept a waveform as described in Section 13 of
ITU-T G.703.
0 = Normal E1 (Equalizer Bit Settings - EQC[4:0])
1 = Section 13 Synchronous Pulse
R/W
0
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XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 36: MICROPROCESSOR REGISTER #131, BIT DESCRIPTION
D3
SL_1
D2
SL_0
D1
EQG_1
D0
EQG_0
Slicer Level Control bit 1: This bit and bit D2 control the slicing level for the slicer per the following table.
R/W
0
Slicer Level Control bit 0: See description bit D3.
R/W
0
Equalizer Gain Control bit 1: This bit together with bit D0
control the gain of the equalizer as shown in the table below.
R/W
0
R/W
0
REGISTER
TYPE
RESET
VALUE
SL_1
SL_0
Slicer Mode
0
0
Normal
0
1
Decrease by 5% from Normal
1
0
Increase by 5% from Normal
1
1
Normal
EQG_1
EQG_0
Equalizer Gain
0
0
Normal
0
1
Reduce Gain by 1 dB
1
0
Reduce Gain by 3 dB
1
1
Normal
Equalizer Gain Control bit 0: See description of bit D1
TABLE 37: MICROPROCESSOR REGISTER #192, BIT DESCRIPTION
REGISTER ADDRESS
11000000
NAME
FUNCTION
BIT #
D[7:1]
Reserved
These register bits are not used.
R/W
0
D0
E1Arben
E1 Arbitrary Pulse Enable
This bit is used to enable the Arbitrary Pulse Generators for
shaping the transmit pulse shape when E1 mode is selected.
If this bit is set to "1", all 8 channels will be configured for the
Arbitrary Mode. However, each channel is individually controlled by programming the channel registers 0xn8 through
0xnF, where n is the number of the channel.
"0" = Disabled (Normal E1 Pulse Shape ITU G.703)
"1" = Arbitrary Pulse Enabled
R/W
0
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OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
ELECTRICAL CHARACTERISTICS
TABLE 38: ABSOLUTE MAXIMUM RATINGS
Storage Temperature...................-65°C to + 150°C
Operating Temperature.............-40°C to + 85°C
Supply Voltage..........................-0.5V to + 3.8V
VIn.................................................-0.5V to + 5.5V
Maximum Junction Temperature..................................125ºC
Theta JA......................................................................24ºC/W
Theta JC......................................................................10ºC/W
TABLE 39: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS
VDD=3.3V±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
Power Supply Voltage
VDD
3.13
3.3
3.46
V
Power Supply Current
IDD
325
400
475
mA
Input High Voltage
VIH
2.0
-
5.0
V
Input Low Voltage
VIL
-0.5
-
0.8
V
Output High Voltage @ IOH = 2.0mA
VOH
2.4
-
-
V
Output Low Voltage @IOL = 2mA.
VOL
-
-
0.4
V
Input Leakage Current (except Input pins
with Pull-up or Pull- down resistor).
IL
-
-
±10
A
Input Capacitance
CI
-
5.0
-
pF
Output Load Capacitance
CL
-
-
25
pF
TABLE 40: XRT83VL38 POWER CONSUMPTION
VDD=3.3V±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
TERMINATION
TRANSFORMER RATIO
RESISTOR
RECEIVER TRANSMITTER
SUPPLY
VOLTAGE
IMPEDANCE
E1
3.3V
75
Internal
1:1
E1
3.3V
120
Internal
T1
3.3V
100
---
3.3V
---
MODE
TEST
CONDITIONS
TYP.
MAX.
UNIT
1:2
1.96
2.16
W
100% “1’s”
1:1
1:2
1.85
2.04
W
100% “1’s”
Internal
1:1
1:2
1.95
2.15
W
100% “1’s”
External
---
---
429
472
mW
72
All transmitters off
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 41: E1 RECEIVER ELECTRICAL CHARACTERISTICS
VDD=3.3V±5%, TA= -40° TO 85°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
MIN.
TYP.
MAX.
UNIT
Cable attenuation @1024kHz
Receiver loss of signal:
Number of consecutive zeros before
RLOS is set
10
175
Input signal level at RLOS
15
20
RLOS De-asserted
Receiver Sensitivity
(Short Haul with cable loss)
Receiver Sensitivity
(Long Haul with cable loss)
Nominal
Extended
255
dB
12.5
dB
11
dB
0
0
36
43
dB
dB
ITU-G.775, ETSI 300 233
With nominal pulse amplitude of 3.0V
for 120 and 2.37V for 75 application. With -18dB interference signal
added.
With nominal pulse amplitude of 3.0V
for 120 and 2.37V for 75 application. With -18dB interference signal
added.
k
13
Input Impedance
Input Jitter Tolerance:
1 Hz
10kHz-100kHz
TEST CONDITIONS
37
0.2
UIpp
UIpp
ITU G.823
kHz
dB
ITU G.736
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude
-
Jitter Attenuator Corner Frequency (-3dB curve) (JABW=0)
(JABW=1)
-
10
1.5
-
Hz
Hz
ITU G.736
14
20
16
-
-
dB
dB
dB
ITU-G.703
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
36
-0.5
73
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 42: T1 RECEIVER ELECTRICAL CHARACTERISTICS
VDD=3.3V±5%, TA=-40° TO 85°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
Receiver loss of signal:
Number of consecutive zeros before
RLOS is set
100
175
250
Input signal level at RLOS
15
20
-
dB
12.5
-
-
% ones
12
-
RLOS Clear
Receiver Sensitivity
(Short Haul with cable loss)
Receiver Sensitivity
(Long Haul with cable loss)
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude
Jitter Attenuator Corner Frequency
(-3dB curve)
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
ITU-G.775, ETSI 300 233
dB
With nominal pulse amplitude of 3.0V
for 100 termination
36
dB
With nominal pulse amplitude of 3.0V
for 100 termination
13
-
k
138
0.4
-
-
UIpp
AT&T Pub 62411
-
9.8
0.1
KHz
dB
TR-TSY-000499
-
6
-Hz
AT&T Pub 62411
-
20
25
25
0
Input Impedance
Jitter Tolerance:
1Hz
10kHz - 100kHz
Cable attenuation @772kHz
-
dB
dB
dB
TABLE 43: E1 TRANSMIT RETURN LOSS REQUIREMENT
RETURN LOSS
FREQUENCY
G.703/CH-PTT
ETS 300166
51-102kHz
8dB
6dB
102-2048kHz
14dB
8dB
2048-3072kHz
10dB
8dB
74
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 44: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDD=3.3V±5%, TA=-40° TO 85°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
MIN.
TYP.
MAX.
UNIT
AMI Output Pulse Amplitude:
75 Application
TEST CONDITIONS
Transformer with 1:2 ratio and internal
termination.
2.185
2.76
2.37
3.00
2.555
3.24
V
V
Output Pulse Width
224
244
264
ns
Output Pulse Width Ratio
0.95
-
1.05
-
ITU-G.703
Output Pulse Amplitude Ratio
0.95
-
1.05
-
ITU-G.703
-
0.025
0.05
UIpp
8
14
10
-
-
dB
dB
dB
120 Application
Jitter Added by the Transmitter Output
Output Return Loss:
51kHz -102kHz
102kHz-2048kHz
2048kHz-3072kHz
Broad Band with jitter free TCLK
applied to the input.
ETSI 300 166, CHPTT
TABLE 45: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDD=3.3V±5%, TA=-40° TO 85°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
MIN.
TYP.
MAX.
UNIT
AMI Output Pulse Amplitude:
2.5
3.0
3.50
V
Transformer with 1:2 ratio and and
Internal Termination.
Output Pulse Width
338
350
362
ns
ANSI T1.102
Output Pulse Width Imbalance
-
-
20
-
ANSI T1.102
Output Pulse Amplitude Imbalance
-
-
+200
mV
ANSI T1.102
Jitter Added by the Transmitter Output
-
0.025
0.05
UIpp
-
15
15
15
-
dB
dB
dB
Output Return Loss:
51kHz -102kHz
102kHz-2048kHz
2048kHz-3072kHz
75
TEST CONDITIONS
Broad Band with jitter free TCLK
applied to the input.
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
FIGURE 26. ITU G.703 PULSE TEMPLATE
10%
20%
269 ns
(244 + 25)
194 ns
(244 – 50)
20%
10%
V = 100%
Nominal pulse
50%
20%
10%
0%
10%
10%
219 ns
(244 – 25)
10%
244 ns
488 ns
(244 + 244)
Note – V corresponds to the nominal peak value.
TABLE 46: TRANSMIT PULSE MASK SPECIFICATION
Test Load Impedance
75 Resistive (Coax)
120 Resistive (twisted Pair)
2.37V
3.0V
0 + 0.237V
0 + 0.3V
244ns
244ns
0.95 to 1.05
0.95 to 1.05
Nominal Peak Voltage of a Mark
Peak voltage of a Space (no Mark)
Nominal Pulse width
Ratio of Positive and Negative Pulses Imbalance
76
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OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
FIGURE 27. ITU G.703 SECTION 13 SYNCHRONOUS INTERFACE PULSE TEMPLATE
T T
30 30
T T
30 30
T T
30 30
+V
+V1
0
–V1
T
4
T
4
T
4
T
4
T
Shaded area in which
signal should be
monotonic
–V
T1818900-92
T Average period of
synchronizing signal
TABLE 47: E1 SYNCHRONOUS INTERFACE TRANSMIT PULSE MASK SPECIFICATION
75 Resistive (Coax)
120 Resistive (twisted Pair)
Maximum Peak Voltage of a Mark
1.5V
1.9V
Minimum Peak Voltage of a Mark
0.75V
1.0V
Nominal Pulse width
244ns
244ns
Test Load Impedance
77
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
FIGURE 28. DSX-1 PULSE TEMPLATE (NORMALIZED AMPLITUDE)
TABLE 48: DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS
MINIMUM CURVE
MAXIMUM CURVE
TIME (UI)
NORMALIZED AMPLITUDE
TIME (UI)
NORMALIZED AMPLITUDE
-0.77
-.05V
-0.77
.05V
-0.23
-.05V
-0.39
.05V
-0.23
0.5V
-0.27
.8V
-0.15
0.95V
-0.27
1.15V
0.0
0.95V
-0.12
1.15V
0.15
0.9V
0.0
1.05V
0.23
0.5V
0.27
1.05V
0.23
-0.45V
0.35
-0.07V
0.46
-0.45V
0.93
0.05V
0.66
-0.2V
1.16
0.05V
0.93
-0.05V
1.16
-0.05V
78
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 49: AC ELECTRICAL CHARACTERISTICS
VDD=3.3V±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
SYMBOL
MIN.
TYP.
E1 MCLK Clock Frequency
-
2.048
MHz
T1 MCLK Clock Frequency
-
1.544
MHz
MCLK Clock Duty Cycle
40
-
60
%
MCLK Clock Tolerance
-
±50
-
ppm
TCDU
30
50
70
%
Transmit Data Setup Time
TSU
50
-
-
ns
Transmit Data Hold Time
THO
30
-
-
ns
TCLK Rise Time(10%/90%)
TCLKR
-
-
40
ns
TCLK Fall Time(90%/10%)
TCLKF
-
-
40
ns
RCLK Duty Cycle
RCDU
45
50
55
%
Receive Data Setup Time
RSU
150
-
-
ns
Receive Data Hold Time
RHO
150
-
-
ns
RCLK to Data Delay
RDY
-
-
40
ns
RCLK Rise Time(10% to 90%) with
25pF Loading.
RCLKR
-
-
40
ns
RCLK Fall Time(90% to 10%) with
25pF Loading.
RCLKF
40
ns
TCLK Duty Cycle
MAX.
UNITS
FIGURE 29. TRANSMIT CLOCK AND INPUT DATA TIMING
TCLKR
TCLK
TPOS/TDATA
or
TNEG
TSU
THO
79
TCLKF
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
FIGURE 30. RECEIVE CLOCK AND OUTPUT DATA TIMING
RCLKR
RDY
RCLKF
RCLK
RPOS
or
RNEG
RHO
MICROPROCESSOR INTERFACE I/O TIMING
INTEL INTERFACE TIMING - ASYNCHRONOUS
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum external glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency,
and with the timings of x86 or i960 family or microprocessors. The interface timing shown in Figure 31 and
Figure 33 is described in Table 50.
FIGURE 31. INTEL ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING
READ OPERATION
W RITE OPERATION
ALE_AS
t0
t0
ADDR[6:0]
Valid Address
Valid Address
t5
t5
CS
DATA[7:0]
Valid Data for Readback
Data Available to W rite Into the LIU
t1
RD_DS
t3
W R_R/W
t2
t4
RDY_DTACK
80
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 50: ASYNCHRONOUS MODE 1 - INTEL 8051 AND 80188 INTERFACE TIMING
SYMBOL
PARAMETER
MIN
MAX
UNITS
t0
Valid Address to CS Falling Edge
0
-
ns
t1
CS Falling Edge to RD Assert
20
-
ns
t2
RD Assert to RDY Assert
-
135
ns
RD Pulse Width (t2)
135
-
ns
t3
CS Falling Edge to WR Assert
20
-
ns
t4
WR Assert to RDY Assert
-
135
ns
135
-
ns
0
-
ns
NA
NA
t5
WR Pulse Width (t2)
CS Falling Edge to AS Falling Edge
Reset pulse width - both Motorola and Intel Operations (see Figure 33)
t9
Reset pulse width
10
81
µs
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
MOTOROLA ASYCHRONOUS INTERFACE TIMING
The signals used in the Motorola microprocessor interface mode are: Address Strobe (AS), Data Strobe (DS),
Read/Write Enable (R/W), Chip Select (CS), Address and Data bits. The interface is compatible with the timing
of a Motorola 68000 microprocessor family with up to 16.67 MHz clock frequency. The interface timing is
shown in Figure 32 and Figure 33. The I/O specifications are shown in Table 51.
FIGURE 32. MOTOROLA 68K ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING
READ OPERATION
W RITE OPERATION
ALE_AS
t0
t0
Valid Address
ADDR[6:0]
Valid Address
t3
t3
CS
Valid Data for Readback
DATA[7:0]
Data Available to W rite Into the LIU
t1
t1
RD_DS
W R_R/W
t2
RDY_DTACK
t2
TABLE 51: ASYNCHRONOUS - MOTOROLA 68K - INTERFACE TIMING SPECIFICATION
SYMBOL
PARAMETER
MIN
MAX
UNITS
t0
Valid Address to CS Falling Edge
0
-
ns
t1
CS Falling Edge to DS Assert
20
-
ns
t2
DS Assert to DTACK Assert
-
135
ns
135
-
ns
0
-
ns
NA
t3
DS Pulse Width (t2)
CS Falling Edge to AS Falling Edge
Reset pulse width - both Motorola and Intel Operations (see Figure 33)
t9
Reset pulse width
10
FIGURE 33. MICROPROCESSOR INTERFACE TIMING - RESET PULSE WIDTH
t9
Reset
82
µs
XRT83VL38
REV. 1.0.0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PACKAGE DIMENSIONS
225 BALL PLASTIC BALL GRID ARRAY (BOTTOM VIEW)
(19.0 X 19.0 X 1.0mm)
18
16
17
14
15
12
13
10
11
8
9
6
7
4
5
2
3
A1
Feature / Mark
1
A
B
C
D
E
F
G
H
D
J
D1
K
L
M
N
P
R
T
U
V
D1
D
(A1 corner feature is mfger option)
D2
A2
Seating Plane
b
A
e
A1
Note: The control dimension is in millimeter.
INCHES
MILLIMETERS
SYMBOL
A
A1
A2
A3
D
D1
D2
b
e
MIN
MAX
0.049
0.096
0.016
0.024
0.013
0.024
0.020
0.048
0.740
0.756
0.669 BSC
0.665
0.669
0.020
0.028
0.039 BSC
83
MIN
MAX
1.24
2.45
0.40
0.60
0.32
0.60
0.52
1.22
18.80
19.20
17.00 BSC
16.90
17.00
0.50
0.70
1.00 BSC
A3
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT83VL38IB
225 Ball BGA
-40°C to +85°C
REVISIONS
REVISION #
DATE
1.0.0
6/15/09
DESCRIPTION
First Release of the Released Datasheet
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2009 EXAR Corporation
Datasheet June 2009.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
84