TI HD3SS6126

HD3SS6126
www.ti.com
SLAS975 – NOVEMBER 2013
USB 3.0 and USB 2.0 Differential Switch 2:1/1:2 MUX/DEMUX
Check for Samples: HD3SS6126
FEATURES
DESCRIPTION
•
The HD3SS6126 is a high speed passive switch that
is designed for USB applications to route both
SuperSpeed USB RX and TX and USB 2.0 DP/DM
signals from a source to two destination or viceversa. It can also be used for DisplayPort, PCI
Express, SATA, SAS, and XAUI applications. The
HD3SS6126 can be used in either sink side or source
side applications.
•
•
•
•
•
•
•
spacer
spacer
spacer
NoteBook
USB 3 Rx
USB 3 Tx
USB 2
DP / DM
HD3SS6126
•
Ideal for USB Applications
– Signal Switch for USB 3.0 (SuperSpeed
USB and USB 2.0 HS/FS/LS)
Three Bi-directional Differential Pair Channel
MUX/DEMUX Switch Also Suitable for
DisplayPort, PCIe Gen1/2/3, SATA 1.5/3/6G,
SAS 1.5/3/6G and XAUI Applications
Supports Data Rates up to 10 Gbps on Highbandwidth Path (SS)
VCC Operating Range 3.3V ± 10%
Wide –3dB Differential BW of Over 10 GHz on
High-bandwidth Path (SS)
Utilizes a unique adaptation method to
maintain a constant channel impedance over
the supported common mode voltage range
Excellent High-bandwidth Path Dynamic
Characteristics (at 2.5 GHz)
– Crosstalk = –35 dB
– Isolation = –23 dB
– Insertion Loss = –1.1 dB
– Return Loss = –11 dB
Small 3.5mm x 9 mm, 42-Pin WQFN Package
(RUA)
Active Mode Power = 8 mW
USB HOST
1
USB
Connector
Connector
APPLICATIONS
•
•
•
•
•
•
Desktop PCs
Notebook PCs
Tablets
Docking Station
Telecommunications
Televisions
USB
Dock Station
Connector
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
HD3SS6126
SLAS975 – NOVEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
FUNCTIONAL DIAGRAM
NC
NC
NC
NC
39
40
41
42
NC
NC
NC
NC
NC
HS_OE
HSA(n)
HSA(p)
SEL
GND
SSA0(p)
SSA0(n)
VDD
GND
SSA1(p)
SSA1(n)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
NC
NC
NC
NC
HSC(n)
HSC(p)
HSB(n)
HSB(p)
VDD
SSB0(p)
SSB0(n)
SSB1(p)
SSB1(n)
SSC0(p)
SSC0(n)
SSC1(p)
SSC1(n)
21
20
19
18
GND
VDD
GND
NC
2
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SLAS975 – NOVEMBER 2013
TRUTH TABLE USB 3.0 SuperSpeed USB
USB 3.0 Port Selection
SEL
SSA0/1
SSB0/1
0
To/From SSB0/1
To/From SSA0/1
SSC0/1
Off
1
To/From SSC0/1
Off
To/From SSA0/1
spacer
TRUTH TABLE USB 2.0 High-speed/Full-speed/Low-speed Path
HS_OE
SEL
0
0
1
USB 2.0 Port Selection
HSA
HSB
HSC
0
To/From HSB
To/From HSA
Off
1
To/From HSC
Off
To/From HSA
X
Off
Off
Off
PINOUT
TOP VIEW
NC
NC
NC
NC
39
40
41
42
NC
NC
NC
NC
NC
HS_OE
HSA(n)
HSA(p)
SEL
GND
SSA0(p)
SSA0(n)
VDD
GND
SSA1(p)
SSA1(n)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
TQFN
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
NC
NC
NC
NC
HSC(n)
HSC(p)
HSB(n)
HSB(p)
VDD
SSB0(p)
SSB0(n)
SSB1(p)
SSB1(n)
SSC0(p)
SSC0(n)
SSC1(p)
SSC1(n)
21
20
19
18
GND
VDD
GND
NC
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PIN FUNCTIONS
PIN
NAME
NO.
GND
10, 14, 17,
19, 21
Supply
8
I/O
HSA(p)
HSA(n)
7
HSB(p)
31
HSB(n)
32
HSC(p)
33
HSC(n)
34
HS_OE
6
NC
I/O
Ground
Port A USB 2.0 positive signal
Port A USB 2.0 negative signal
I/O
I/O
Port C USB 2.0 positive signal
Port C USB 2.0 negative signal
I (Control)
Output Enable
H = Power Down
L = Normal Operation
Electrically No Connection
SEL
9
I (Control)
SSA0(p)
11
I/O
SSA0(n)
12
SSA1(p)
15
SSA1(n)
16
SSB0(p)
29
SSB0(n)
28
SSB1(p)
27
SSB1(n)
26
SSC0(p)
25
SSC0(n)
24
SSC1(p)
23
SSC1(n)
22
13, 20, 30
Port B USB 2.0 positive signal
Port B USB 2.0 negative signal
1, 2, 3, 4, 5,
18, 35, 36,
37, 38, 39,
40, 41, 42
VDD
DESCRIPTION
USB 3.0/2.0 Port Selection Control Pins
Port A, Channel 0, USB 3.0 Positive Signal
Port A, Channel 0, USB 3.0 Negative Signal
I/O
Port A, Channel 1, USB 3.0 Positive Signal
Port A, Channel 1, USB 3.0 Negative Signal
I/O
Port B, Channel 0, USB 3.0 Positive Signal
Port B, Channel 0, USB 3.0 Negative Signal
I/O
Port B, Channel 1, USB 3.0 Positive Signal
Port B, Channel 1, USB 3.0 Negative Signal
I/O
Port C, Channel 0, USB 3.0 Positive Signal
Port C, Channel 0, USB 3.0 Negative Signal
I/O
Port C, Channel 1, USB 3.0 Positive Signal
Port C, Channel 1, USB 3.0 Negative Signal
Supply
3.3V power supply voltage
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage range
(1)
(2)
, VDD
Voltage range
Electrostatic discharge
(2)
(3)
(4)
(5)
4
MAX
–0.3
4
Differential I/O, High-bandwidth signal path: SSA0/1(p/n), SSB0/1(p/n),
SSC0/1(p/n)
–0.5
4
Differential I/O, Low-bandwidth signal path: HSAp/n), HSB(p/n),
HSC(p/n)
-0.5
7
Control pin and single ended I/O
–0.3
VDD + 0.3
Human body model (3) (4)
Charged-device model
(5)
Continuous power dissipation
(1)
MIN
±2,000
±500
UNIT
V
V
V
See Thermal Information Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B
Tested in accordance with JEDEC Standard 22, Test Method C101-A
Tested in accordance with JEDEC Standard 22, Test Method A115-A
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SLAS975 – NOVEMBER 2013
THERMAL INFORMATION
PARAMETER
TEST CONDITIONS
MIN
TYP
θJA
Junction-to-ambient thermal resistance
53.8
θJB
Junction-to-board thermal resistance
27.4
θJCT
Junction-to-case-Top thermal resistance
UNIT
38.2
(1)
27.3
5.6
ΨJB
Junction-to-board thermal resistance Metric
High-K board
ΨJT
Junction-to-case-Top thermal resistance Metric
High-K board (1)
(1)
MAX
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A, IC
Package Thermal Metrics. Test conditions for ΨJB and ΨJT are clarified in the application report.
RECOMMENDED OPERATING CONDITIONS
Typical values for all parameters are at VCC = 3.3 V and TA = 25°C. All temp limits are specified by design.
VDD
Supply voltage
VIH
Input high voltage
Control Pins
VIL
Input low voltage
Control Pins
VI/O_Diff
Differential voltage
Switch I/O differential voltage for High-bandwidth signal
path only: SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n)
VI/O_CM
Common voltage
Switch I/O common mode voltage for High-bandwidth signal
path only: SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n)
TA
Operating free-air temperature
MIN
TYP
MAX
3.0
3.3
3.6
UNIT
V
2.0
VDD
V
–0.1
0.8
V
0
1.8
Vp-p
0
2.0
V
0
70
°C
ELECTRICAL CHARACTERISTICS – DEVICE PARAMETERS
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC
CONDITIONS
TYP
MAX
2.4
3
mA
VDD = 3.6V, VIN = VDD
95
µA
VDD = 3.6V, VIN = GND
1
µA
Input high current
VDD = 3.6V, VIN = VDD
1
µA
Input high current
VDD = 3.6V, VIN = GND
1
µA
130
µA
VDD = 3.6V, VIN = 2V, VOUT= 2V,
(ILK on open outputs Port A)
4
µA
VDD = 3.6V, VIN = 0V, VOUT= 0V to 4V,
HS_OE_IN = GND
1
µA
Supply current
VDD = 3.6 V, SEL = VDD /GND; OE = GND; Outputs Floating
IIH
Input high current
IIL
Input high current
IIH
IIL
MIN
UNIT
SEL
HS_OE
SSA0/1, SSB0/1, SSC0/1
ILK
High-impedance leakage
current
VDD = 3.6V, VIN = 2V, VOUT= 2V,
(ILK on open outputs Port B and C)
HSA, HSB, HSC
ILK
High-impedance leakage
current
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SLAS975 – NOVEMBER 2013
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ELECTRICAL CHARACTERISTICS – SIGNAL SWITCH PARAMETERS
under recommended operating conditions; RL, RSC = 50 Ω, CL = 10pF (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
70
250
70
250
UNIT
SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n) Signal Path
ton
SEL-to-Switch ton
toff
SEL-to-Switch toff
tPD
Switch propagation delay
tSK(O)
Inter-pair output skew (CH-CH)
tSK(b-b)
Intra-Pair Output Skew (bit-bit)
CON
Outputs ON capacitance
VIN = 0 V, Outputs Open, Switch ON
1.5
pF
COFF
Outputs OFF capacitance
VIN = 0V, Outputs Open, Switch OFF
1
pF
RON
Output ON resistance
VDD = 3.3V, VCM = 0V - 2V,
IO = –8 mA
5
ΔRON
ON resistance match between pairs
of the same channel
RFLAT_ON
ON resistance flatness (RON(MAX)–
RON(MIN )
RL
Differential return loss (VCM = 0 V)
XTALK
OIRR
Differential crosstalk (VCM = 0 V)
Differential off-isolation (VCM = 0 V)
RSC and RL = 50 Ω, See Figure 1
RSC and RL = 50 Ω, See Figure 3
RSC and RL = 50 Ω, See Figure 3
Differential insertion loss (VCM = 0
V)
BW
Bandwidth
85
ps
20
ps
8
ps
8
Ω
VDD = 3.3 V; 0 V ≤ VIN ≤ 2 V;
IO = –8 mA
0.7
Ω
VDD = 3.3 V; -0 V ≤ VIN ≤ 2 V
1.15
Ω
f = 0.3 MHz
-25
f = 2.5 GHz
–11
f = 4 GHz
–11
f = 0.3 MHz
-85
f = 2.5 GHz
–35
f = 4 GHz
–33
f = 0.3 MHz
-85
f = 2.5 GHz
-23
f = 4 GHz
IL
ns
dB
dB
–21
f = 0.3 MHz
-0.43
f = 2.5 GHz
–1.1
f = 4 GHz
–1.3
At –3 dB
dB
dB
10
GHz
HSA(p/n), HSB(p/n), HSC(p/n) SIGNAL PATH
SEL to Switch tON
tON
HS_OE to Switch tON
SEL to Switch tOFF
tOFF
tPD
HS_OE to Switch tOFF
(1)
Switch propagation delay
30
See Figure 2
17
See Figure 2
See Figure 3
ns
12
10
250
ps
tSK(O) (1)
Inter-pair output skew (CH-CH)
100
200
tSK(P) (1)
Intra-Pair Output Skew (bit-bit)
100
200
CON
Outputs ON capacitance
VIN = 0 V, Outputs Open, Switch ON
6
7.5
pF
COFF
Outputs OFF capacitance
VIN = 0 V, Outputs Open, Switch OFF
3.5
6
pF
3
6
VDD = 3 V, VIN = 2.4 V,
IO = 30 mA
3.4
6
VDD = 3 V; VIN = 0 V;
IO = 30 mA
0.2
VDD = 3 V; VIN = 1.7 V;
IO = -15 mA
0.2
RON
Output ON resistance
ΔRON
(1)
6
ON resistance match between pairs
of the same channel
VDD = 3 V, VIN = 0 V,
IO = 30 mA
ps
Ω
Ω
Specified by design
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SLAS975 – NOVEMBER 2013
ELECTRICAL CHARACTERISTICS – SIGNAL SWITCH PARAMETERS (continued)
under recommended operating conditions; RL, RSC = 50 Ω, CL = 10pF (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n) Signal Path
ON resistance flatness (RON(MAX)–
RON(MIN )
RFLAT_ON
VDD = 3 V; VIN = 0 V;
IO = 30 mA
1
VDD = 3 V; VIN = 1.7 V;
IO = -15 mA
1
Ω
XTALK
Differential crosstalk (VCM = 0 V)
RL = 50 Ω, f = 250 MHz
-40
OIRR
Differential off-isolation (VCM = 0 V)
RL = 50 Ω, f = 250 MHz
-41
dB
BW
Bandwidth
RL = 50 Ω
0.9
GHz
dB
TEST TIMING DIAGRAMS
50%
SEL
90%
VOUT
10%
t off
t on
Figure 1. Select to Switch ton and toff
VCC
HSB or HSC VOUT1 or VOUT2
VIN
Logic
Input (1)
RL
CL
VCOM
tON
500 Ω
50 pF
V+
tOFF
500 Ω
50 pF
V+
HSA
CL(2)
HSB or HSC
VCTRL
TEST
RL
SEL
CL(2)
GND
RL
1.8 V
Logic
Input
(VI)
50%
50%
0
tON
tOFF
Switch
Output
(VOUT1 or VOUT2)
(1)
(2)
90%
90%
VOH
VOL
All input pulses are supplied by generators have the following characteristics: PRR ≤ 10 MHZ, ZO = 50 Ω, tr< 5 ns, tf < 5 ns.
CL includes probe and jig capacitance.
Figure 2. Turn-On (tON) and Turn-Off Time (tOFF)
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HD3SS6126
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Vcc
50 Ω
HD3SS6126
A(p)
B/C(p)
50 Ω
B/C(p)
A(p)
50 Ω
A(n)
B/C(n)
B/C(n)
A(n)
50 Ω
SEL
C/B (p)
50%
50%
C/B (n)
A (p)
50%
50%
A (n)
tP1
tP2
Inter-pair skew
tPD = Max(tp1, tp2)
tSK(O) = Difference between tPD for any
two pairs of outputs
t1
t3
t2
t4
C/B/A (p)
50%
C/B/A (n)
C/B/A (p)
tSK(O)
C/B/A (n)
Intra-pair skew
tSK(b-b) = 0.5 X |(t4 – t3) + (t1 – t2)|
NOTES:
1. Measurements based on an ideal input with zero intra-pair skew on
the input, i.e. the input at A to B/C or the input at B/C to A
2. Inter-pair skew is measured from lane to lane on the same channel,
e.g. C0 to C1
3. Intra-pair skew is defined as the relative difference from the p and n
signals of a single lane
Figure 3. Propagation Delay and Skew
8
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
HD3SS6126RUAR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WQFN
RUA
42
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
0 to 70
HD3SS6126
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Nov-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
HD3SS6126RUAR
Package Package Pins
Type Drawing
WQFN
RUA
42
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
16.4
Pack Materials-Page 1
3.8
B0
(mm)
K0
(mm)
P1
(mm)
9.3
1.0
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Nov-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
HD3SS6126RUAR
WQFN
RUA
42
3000
367.0
367.0
38.0
Pack Materials-Page 2
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