F71858 F71858 Hardware KBC with ACPI, Temp. and Fan Control Release Date: July, 2007 Version: V0.26P July, 2007 V0.26P F71858 F71858 Datasheet Revision History Version 0.1P 0.11P 0.12P Date 2005/08/12 2005/09/05 2005/09/12 0.13P 0.14P 0.15P 0.16P 0.17P 2005/11/02 2005/11/20 2005/11/30 2006/01/05 2006/01/13 Page 5 - 0.18P 2006/02/15 - 0.19P 2006/03/15 - 0.20P 2006/04/13 55 0.21P 2006/05/03 35 32 0.22P 2006/06/15 - 0.23P 2006/09/06 - Revision History Preliminary Version Updated Hardware Monitor Functions of Feature List Updated Pin Type Description. Added Application Circuit. Added Function/Register Description Register Modify Register Modify Register modify and pin17/pin10 modify Updated application circuit and register description for LAA version chip. Modified typo. Modified Fan1~Fan3 Duty Change Rate Select Register (CR9Bh) Removed HW Monitor Register Index 70h (HW_IRQ Enable Register) Added Electrical Characteristics Description. Updated Register description. Added Fan4 D0h-D1h registers description. Modified ACPI Control Register Index F5h bit 7 Modified Select KB/MO Wakeup Register 27h bit 7 Modified name of VT1/VT2/VT3 which T1/T2/T0. T0 means local temperature. change to This version datasheet is for LAC version chip use. Added Fan control machine by internal clock when system boot up. Modified typo. 0.24P 2006/11/10 - 0.25P 2006/12/19 - 0.26P 2007/7/6 - This version datasheet is for LAD version chip use. Modified typo. Updated Application Circuit. Company readdress Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. July, 2007 V0.26P F71858 Table of Content 1. 2. 3. 4. 5. General Description ........................................................................................................ 6 Feature List..................................................................................................................... 6 Key Specification ............................................................................................................ 7 Pin Configuration ............................................................................................................ 8 Pin Description ............................................................................................................... 9 5.1 5.2 5.3 5.4 5.5 Power Pin.................................................................................................................... 9 LPC Interface ..............................................................................................................9 Keyboard Controller .................................................................................................. 10 ACPI.......................................................................................................................... 10 H/W Monitor .............................................................................................................. 10 6. Function Description ..................................................................................................... 12 6.1 Keyboard Controller .................................................................................................. 12 6.2 ACPI function ............................................................................................................ 14 6.3 Hardware monitor...................................................................................................... 18 6.4 LED function ............................................................................................................. 28 6.5 AMDSI and Intel SST PECI Function ........................................................................ 29 7. Register Description ..................................................................................................... 30 7.1 Global Control Registers ........................................................................................... 30 7.2 KBC Registers........................................................................................................... 32 7.3 ACPI and PME Registers.......................................................................................... 33 7.4 Hardware Monitor Registers (Index port: 0x295; Data port: 0x296) .......................... 36 7.4.1 7.4.2 7.4.3 Logic Device Number Register .......................................................................... 36 Hardware Monitor Configuration Registers ........................................................ 36 Hardware Monitor Device Registers .................................................................. 36 7.4.3.1 7.4.3.2 7.4.3.3 7.4.3.4 7.4.3.5 7.4.3.6 7.4.3.7 7.4.3.8 7.4.3.9 7.4.3.10 Configuration Register Index 01h.................................................................. 36 Configuration Register Index 02h................................................................... 36 PECI SST AMDSI Interface Configuration Register Index 0Ah ...................... 37 AMDSI Version Register Index 0Bh (MEAS_TYPE ==2’b10) ...................... 37 Dual Single Core select Register Index 0Bh (MEAS_TYPE ==2’b01) ......... 37 TCC Activation Temperature Register Index 0Ch (MEAS_TYPE == 2’b01) 37 AMDSI Node ID Register Index 0Ch (MEAS_TYPE ==2’b10)..................... 37 SST Address Register Index 0Dh................................................................... 38 CPU Temp. Measure Select Register Index 0Eh............................................ 38 Voltage reading and limit Index 20h- 22h ...................................................... 38 July, 2007 V0.26P F71858 7.4.3.11 7.4.3.12 7.4.3.13 7.4.3.14 7.4.3.15 7.4.3.16 7.4.3.17 7.4.3.18 7.4.3.19 7.4.3.20 7.4.3.21 7.4.3.22 7.4.3.23 7.4.3.24 Temperature PME# Enable Register Index 60h ........................................... 38 Temperature Interrupt Status Register Index 61h......................................... 39 Temperature Real Time Status Register Index 62h ...................................... 39 ALERT# Output Enable Register 1 Index 66h.............................................. 40 Temperature PME# mode and Table Select Register -- Index 69h .................. 40 LOCAL and TEMP1 Limit Hysteresis Select Register -- Index 6Ch ................. 41 TEMP2 and TEMP3 Limit Hysteresis Select Register -- Index 6Dh................. 41 DIODE OPEN Status Register -- Index 6Fh..................................................... 41 Temperature Register Index 70h- 8Fh.......................................................... 41 Temperature Filter Select Register -- Index 8Eh .............................................. 42 FAN PME# Enable Register Index 90h ........................................................ 43 FAN Interrupt Status Register Index 91h...................................................... 43 FAN Real Time Status Register Index 92h ................................................... 43 FAN FAULT# Enable Register Index 93h ..................................................... 43 7.4.3.25 7.4.3.26 7.4.3.27 7.4.3.28 7.4.3.29 7.4.3.30 7.4.3.31 7.4.3.32 7.4.3.33 7.4.3.34 7.4.3.35 7.4.3.36 7.4.3.37 7.4.3.38 7.4.3.39 7.4.3.40 7.4.3.41 7.4.3.42 7.4.3.43 7.4.3.44 7.4.3.45 7.4.3.46 7.4.3.47 Fan Type Select Register -- Index 94h............................................................. 44 Fan mode Select Register -- Index 96h ........................................................... 44 Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h........... 45 Auto Fan3 Boundary Hystersis Select Register -- Index 99h ........................... 45 Fan1~Fan3 Duty Change Rate Select Register -- Index 9Bh .......................... 45 FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE Index 9Ch............... 46 FAN3 START UP DUTY-CYCLE/VOLTAGE Index 9Dh................................ 46 Fan Fault Time Register -- Index 9Fh .............................................................. 46 T1 BOUNDARY 1 TEMPERATURE – Index A6h............................................. 47 T1 BOUNDARY 2 TEMPERATURE – Index A7h............................................. 47 T1 BOUNDARY 3 TEMPERATURE – Index A8h............................................. 47 T1 BOUNDARY 4 TEMPERATURE – Index A9h............................................. 47 FAN1 SEGMENT 1 SPEED COUNT – Index AAh......................................... 47 FAN1 SEGMENT 2 SPEED COUNT – Index ABh......................................... 48 FAN1 SEGMENT 3 SPEED COUNT – Index ACh....................................... 48 FAN1 SEGMENT 4 SPEED COUNT – Index ADh....................................... 48 FAN1 SEGMENT 5 SPEED COUNT – Index AEh....................................... 48 FAN1 Temperature Mapping Select – Index AFh......................................... 48 T2 BOUNDARY 1 TEMPERATURE – Index B6h............................................. 49 T2 BOUNDARY 2 TEMPERATURE – Index B7h............................................. 50 T2 BOUNDARY 3 TEMPERATURE – Index B8h............................................. 50 T2 BOUNDARY 4 TEMPERATURE – Index B9h............................................. 50 FAN2 SEGMENT 1 SPEED COUNT – Index BAh ........................................ 50 July, 2007 V0.26P F71858 8. 9. 10. 11. 12. 7.4.3.48 FAN2 SEGMENT 2 SPEED COUNT – Index BBh ........................................ 50 7.4.3.49 FAN2 SEGMENT 3 SPEED COUNT – Index BCh ...................................... 51 7.4.3.50 FAN2 SEGMENT 4 SPEED COUNT – Index BDh ...................................... 51 7.4.3.51 FAN2 SEGMENT 5 SPEED COUNT – Index BEh....................................... 51 7.4.3.52 FAN2 Temperature Mapping Select – Index BFh ........................................ 51 7.4.3.53 T0 BOUNDARY 1 TEMPERATURE – Index C6h ............................................ 52 7.4.3.54 T0 BOUNDARY 2 TEMPERATURE – Index C7h ............................................ 52 7.4.3.55 T0 BOUNDARY 3 TEMPERATURE – Index C8h ............................................ 52 7.4.3.56 T0 BOUNDARY 4 TEMPERATURE – Index C9h ............................................ 53 7.4.3.57 FAN3 SEGMENT 1 SPEED COUNT – Index CAh ........................................ 53 7.4.3.58 FAN3 SEGMENT 2 SPEED COUNT – Index CBh ........................................ 53 7.4.3.59 FAN3 SEGMENT 3 SPEED COUNT – Index CCh ...................................... 53 7.4.3.60 FAN3 SEGMENT 4 SPEED COUNT – Index CDh ...................................... 53 7.4.3.61 FAN3 SEGMENT 5 SPEED COUNT – Index CEh ...................................... 54 7.4.3.62 FAN3 Temperature Mapping Select – Index CFh ........................................ 54 PCB Layout Guide ........................................................................................................ 54 Electrical Characteristics .............................................................................................. 56 9.1 Absolute Maximum Ratings ...................................................................................... 56 9.2 DC Characteristics .................................................................................................... 57 9.3 DC Characteristics Continued ................................................................................... 57 9.4 AC Characteristics .................................................................................................... 58 Ordering Information..................................................................................................... 62 Package Dimensions (48LQFP) ................................................................................... 62 Application Circuit ......................................................................................................... 63 July, 2007 V0.26P F71858 1. General Description The F71858 is hardware KBC integrating the ACPI, temperature sensing and fan control functions specific for the legacy free MB application. The KBC functions include one keyboard and one PS/2 mouse, and can be used with IBM-compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. The controller will assert an interrupt to the system when data are placed in its output buffer. The F71858 provides the ACPI control signals as well such as S3 state, resume reset, PCI reset outputs or power OK signals. The power LED is programmable and compliant with PC2001. As to the environment sensing functions, F71858 provides 2 remote analog dual current temp. sensing inputs and one internal local temperature sensing. One alert signal will be issued while the temperature is over the programmable limit. 4 fan monitoring inputs and 3 fan controlling outputs provide Fintek’s patented auto-fan controlling features. Others, the F71858 supports AMDSI and Intel PECI/SST interfaces for temperature use. for next generation CPU temp. sensing technology. F71858 is in LPC interface and powered by 3VCC, 3V standby, and battery. The package is in 48 pin LQFP Green Package. 2. Feature List General Functions ¾ Comply with LPC Spec. 1.0 ¾ Hardware Keyboard Controller support one PS/2 keyboard and one PS/2 mouse ¾ Fast Gate A20 and Hardware Keyboard Reset ¾ Support DPM (Device Power Management), ACPI KBC ¾ LPC interface support serial interrupt channel 1, 12. ¾ Two 16bit Programmable Address fully decoder, default 0x60 and 0x64. ¾ Support two PS/2 interface, one for PS/2 mouse and the other for keyboard. ¾ Keyboard’s scan code support set1, set2. ¾ Programmable compatibility with the 8042. ¾ Support both interrupt and polling modes. ¾ Fast Gate A20 and Hardware Keyboard Reset. 6 July, 2007 V.26P F71858 ACPI Functions ¾ 1 reset input and 5 PCI reset output pins ¾ 2 programmable power LED ¾ S3Gate control ¾ Resume reset ¾ Power ok signal Hardware Monitor Functions ¾ 2 current type accurate (3℃) thermal inputs for CPU thermal diode/2N3906 transistors ¾ One internal local thermal sensor ¾ One alert pin (Pin HW_IRQ#)(default limit 100°C for CPU temp.) ¾ Temperature sensing range from -40℃~127℃ ¾ 4 fan speed monitoring inputs ¾ 3 fan speed auto-control (support 3 wire and 4 wire fans) ¾ Support PWM and DAC mode control ¾ Default PWM duty is 40% when system boot up promptly ¾ Provide Intel PECI/SST interface for temperature sensing ¾ Provide AMDSI interface for temperature sensing ¾ Support 3 channels voltage monitor ( VCC3V + VSB3V + VBAT) ¾ Voltage monitor resolution is 8mV per LSB Package ¾ 48-pin LQFP 3. Key Specification Supply Voltage 3.0V to 3.6V Operating Supply Current 5 mA typ. 7 July, 2007 V.26P F71858 4. Pin Configuration 8 July, 2007 V.26P F71858 5. Pin Description I/O12t I/OOD12t I/OD16t5v OD16-u10-5v I/OD12ts5v O8-u47-5v O8 O16 O30 AOUT OD12 OD12-5v OD24 INt5v INts INts5v AIN P 5.1 - TTL level bi-directional pin with 12 mA source-sink cap ability. - TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA source-sink capability. - TTL level bi-directional pin,Open-drain output with 16 mA source-sink capability, 5V tolerance. - Open-drain output pin with 16 mA sink capability, pull-up 10k ohms, 5V tolerance. - TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink capability, 5V tolerance. - Open-drain pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance. - Output pin with 8 mA source-sink capability. - Output pin with 16 mA source-sink capability. - Output pin with 30 mA source-sink capability. - Output pin(Analog). - Open-drain output pin with 12 mA sink capability. - Open-drain output pin with 12 mA sink capability, 5V tolerance. - Open-drain output pin with 24 mA sink capability. - TTL level input pin,5V tolerance. - TTL level input pin and schmitt trigger. - TTL level input pin and schmitt trigger, 5V tolerance. - Input pin(Analog). - Power. Power Pin Pin No. 9 24 40 48 45 21 5.2 Pin Name VCC VCC3V VSB3V VBAT GND GND(D-) Type P P P P P P Description 3V power 3V power for analog (Provide voltage monitor) 3V stand by power (Provide voltage monitor) Battery power (Provide voltage monitor) Ground Ground for temperature sensing use. LPC Interface Pin No. 1 Pin Name LRESET# Type INts5v PWR VCC 8 2 SERIRQ LFRAM# I/O12t INts VCC VCC 3,4,5,6 LAD[3:0] I/O12t VCC 7 PCICLK INt VCC Description Reset signal. It can connect to PCIRST# signal on the host. Serial IRQ input/Output. Indicates start of a new cycle or termination of a broken cycle. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. 33MHz PCI clock input. 9 July, 2007 V.26P F71858 5.3 Keyboard Controller Pin No. 19 Pin Name KBRST# Type OD12-u10 PWR VCC 18 GA20 OD12-u10 VCC 42 41 44 43 KDATA KCLK MDATA MCLK I/OD16ts,5V I/OD16ts,5V I/OD16ts,5V I/OD16ts,5V VSB VSB VSB VSB Description Keyboard reset. This pin is high after system reset. Internal pull high 3.3V with 10k ohms. (KBC P20) Gate A20 output. This pin is high after system reset. Internal pull high 3.3V with 10k ohms. (KBC P21) Keyboard Data. Keyboard Clock. PS2 Mouse Data. PS2 Mouse Clock. Type OD16,5V OD16,5V INts5v OD16,5V PWR VSB VSB VSB VSB Description Power LED for VSB. Power LED for VSB. Reset buffer input signal. Output buffer of RSTIN# and LRESET# for IDE reset. 27,28,29 46 Pin Name LED1 LED2 RSTIN# PCIRST1# PCIRST5# PCIRST[2:4]# PWROK O16 IOD12,5V VSB VBAT 39 38 PS_IN# PS_OUT# INts5v OD12 VSB VSB 35 36 33 34 S3# S4# S3GATE PS_ON# INts INts OD12-5v OD12-5v VSB VSB VSB VSB 47 RSMRST# OD12 VBAT Output buffer of RSTIN# and LRESET#. PWROK function, It is power good signal of VCC, which is delayed 400ms (default and programmable) as VCC arrives at 2.8V. Main power switch button input. Panel Switch Output. This pin is low active and pulse output. It is power on request output#. S3# Input is Main power on-off switch input. S4# Input is for S3/S4 (S5) state switch input. Control dual voltage signal. Power supply on-off control output. Connect to ATX power supply PS_ON# signal. Resume Reset# function, It is power good signal of VSB, which is delayed 66ms as VSB arrives at 2.3V. 5.4 ACPI Pin No. 31 32 25 26,30 5.5 H/W Monitor Pin No. 14 11 Pin Name FANIN1 FAN_CTL1 Type INt s 5 v OD12-5v AOUT PWR VCC VCC 15 12 FANIN2 FAN_CTL2 INt s 5 4 v OD12-5v AOUT VCC VCC 16 FANIN3 INt s 5 v VCC Description Fan 1 tachometer input. Fan 1 control output. This pin provides duty-cycle output or a voltage output. Default duty is 40%. Fan 2 tachometer input. Fan 2 control output. This pin provides duty-cycle output or a voltage output. Default duty is 40%. Fan 3 speed input. Default PWM duty is 40%. 10 PWM PWM PWM PWM July, 2007 V.26P F71858 13 FAN_CTL3/ OD12-5V AOUT VCC Fan 3 control output and 3pin fan is recommended to be controlled by this pin but not 4pin fan. This pin provides PWM duty-cycle output or a voltage output. HPWM_DC Power on strapping : 23 FANIN4 SST AMDSI_CLK D2+ VCC 22 D1+(CPU) VCC Thermal diode/transistor temperature sensor input. 10 VCC Intel PECI hardware monitor interface. AMD SI data interface. 20 PECI AMDSI_DAT HW_IRQ# INt s 5 v ILv/OD8-S1 OD12 AOUT AIN AOUT AIN ILv/OD8-S1 ILv/OD12 OD12-5V Pull high: Fan control method will be PWM Mode NC: Fan control method will be DAC Mode Fan 4 speed input. Intel SST hardware monitor interface. Clock output for AMD SI interface. Thermal diode/transistor temperature sensor input. VCC Active LOW output. This pin will be logic low when the temperature exceeds its limit or fan fault event. 37 PME# OD12 VSB Generated PME event. It supports the PCI PME# interface. This signal allows the peripheral to request the system to wake up from the S3 state. 17 VCC 11 July, 2007 V.26P F71858 6. Function Description 6.1 Keyboard Controller The KBC circuit provides the functions included a keyboard and/or a PS/2 mouse, and can be used with IBM-compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. The controller will assert an interrupt to the system when data are placed in its output buffer. Output Buffer The output buffer is an 8-bit read-only register at I/O address 60H. The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. Input Buffer The input buffer is an 8-bit write-only register at I/O address 60H or 64H. Writing to address 60H sets a flag to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written to I/O address 60H is sent to keyboard through the controller's input buffer only if the input buffer full bit in the status register is “0”. Status Register The status register is an 8-bit read-only register at I/O address 64H, that holds information about the status of the keyboard controller and interface. BIT It may be read at any time. BIT FUNCTION DESCRIPTION 0 Output Buffer Full 0: Output buffer empty 1: Output buffer full 1 Input Buffer Full 0: Input buffer empty 1: Input buffer full 2 System Flag This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller (KCCB). It defaults to 0 after a power-on reset. 3 Command/Data 0: Data byte 1: Command byte 12 July, 2007 V.26P F71858 4 Inhibit Switch 0: Keyboard is inhibited 1: Keyboard is not inhibited 5 Mouse Output Buffer 0: Muse output buffer empty 1: Mouse output buffer full 6 General Purpose Time-out 0: No time-out error 1: Time-out error 7 Parity Error 0: Odd parity 1: Even parity (error) Commands COMMAND FUNCTION 20h Read Command Byte 60h Write Command Byte BIT DESCRIPTION 0 Enable Keyboard Interrupt 1 Enable Mouse Interrupt 2 System flag 3 Reserve 4 Disable Keyboard Interface 5 Disable Mouse interface 6 IBM keyboard Translate Mode 7 Reserve A7h Disable Auxiliary Device Interface A8h Enable Auxiliary Device Interface A9h Auxiliary Interface Test 8’h00: indicate Auxiliary interface is ok. 8’h01: indicate Auxiliary clock is low. 8’h02: indicate Auxiliary clock is high 8’h03: indicate Auxiliary data is low 8’h04: indicate Auxiliary data is high AAh Self-test Returns 055h if self test succeeds ABh keyboard Interface Test 8’h00: indicate keyboard 8’h01: indicate keyboard 8’h02: indicate keyboard 8’h03: indicate keyboard 8’h04: indicate keyboard ADh interface is ok. clock is low. clock is high data is low data is high Disable Keyboard Interface 13 July, 2007 V.26P F71858 AEh Enable Keyboard Interface C0h Read Input Port(P1) and send data to the system C1h Continuously puts the lower four bits of Port1 into STATUS register C2h Continuously puts the upper four bits of Port1 into STATUS register D0h Send Port2 value to the system D1h Only set/reset GateA20 line based on the system data bit 1 D2h Send data back to the system as if it came from Keyboard D3h Send data back to the system as if it came from Muse D4h Output next received byte of data from system to Mouse FEh Pulse only RC(the reset line) low for 6µS if Command byte is even KBC Command Description PS2 wakeup function The KBC supports keyboard and mouse wakeup function, keyboard wakeup function has 4 kinds of conditions, when key is pressed combinational key (1) CTRL +ESC (2) CTRL+F1 (3) CTRL+SPACE (4) ANY KEY (5) windows 98 wakeup up key, KBC will assert PME signal. Mouse wakeup function has 2 kinds of conditions, when mouse (1) BUTTON CLICK or (2) BUTTON CLICK AND MOVEMENT, KBC will assert PME signal. Those wakeup conditions are controlled by configuration register. 6.2 ACPI function The Advanced Configuration and Power Interface (ACPI) is a system for controlling the use of power in a computer. It lets computer manufacturer and user to determine the computer’s power usage dynamically. There are three ACPI states that are of primary concern to the system designer and they are designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in this state. The other two are called sleep states and reflect different power consumption when power-down. S3 is a state that the processor is powered down but the last procedural state is being stored in memory which is still active. S5 is a state that memory is off and the last procedural state of the processor has been stored to the hard disk. Take S3 and S5 as comparison, since memory is fast, the computer can quickly come back to full-power state, the disk is slower than the memory and the computer takes longer time to come back to full-power state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3. It is anticipated that only the following state transitions may happen: S0→S3, S0→S5, S5→S0, S3→S0 and S3→S5. Among them, S3→S5 is illegal transition and won’t be allowed by state machine. It is 14 July, 2007 V.26P F71858 necessary to enter S0 first in order to get to S5 from S3. As for transition S5→S3 will occur only as an immediate state during state transition from S5→S0. It isn’t allowed in the normal state transition. The below diagram described the timing, the always on and always off, keep last state could be set in control register. In keep last state mode, one register will keep the status of before power loss. If it is power on before power loss, it will remain power on when power is resumed, otherwise, if it is power off before power loss, it will remain power off when power is resumed. VBAT VSB RSMRST# S3# PS_ON# PSIN# PSOUT# VCC3V ACPI Default Timing Always Off VBAT VSB RSMRST# S3# PS_ON# PSIN# PSOUT# VCC3V ACPI Default Timing Always On 15 July, 2007 V.26P F71858 PCIRST and PWROK Signals The F71858 supports 5 output buffers for 5 reset signals. The result of PCIRST[1:5]# outcome will be affected by conditions as below. The PWROK signal is affected by RST_IN#/LRESET#/DVCC3VOK.when rstcon_en set 1, POWEROK signal is affect by DVCC3VOK and when rstcon_en set 0, POWEROK signal is affect by RST_IN#/ LRESET#/DVCC3VOK, reference as below. Rst_in# 50ms 1 Rst_dat Lreset# PCIRST 0 Rst_dis Rstcon_en Rst_in# 50ms D_VCC3VOK 0 D_VCC3VOK 1 1ms PWROK Rstcon_en PCIRST# and PWROK 16 July, 2007 V.26P F71858 S3 GATE Signals The S3 GATE signal response S0/S3/S5 state and condition is as below. When system is in S3 state, S3_GATE is asserted logic high; the other state is asserted logic low. It is anticipated that only the following state transitions may happen: S0→S3, S0→S5, S5→S0, S3→S0 and S3→S5. Among them, S5→S3 is illegal transition and S3_GATE signal will be keep logic level. IDLE S3 = 1 & S4 = 1& D_VDD3VOK = 1 S3_GATE = 0 S3/S4/D_VDDOK S3_GATE = 1 S3 = 0&S4 = 0 S3 = 0&S4 = 1 S3 / S4 S3_GATE = 0 S3 = 0&S4 = 0 S3_GATE diagram 17 July, 2007 V.26P F71858 6.3 Hardware monitor For the 8-bit ADC has the 8mv LSB, the maximum input voltage of the analog pin is 2.304V. Therefore the voltage under 2.304V (ex:1.5V) can be directly connected to these analog inputs. The voltage higher than 2.304V should be reduced by a factor with external resistors so as to obtain the input range. VCC, VSB 3.3V and VBAT 3V are the exception for it is main power of the F71858. Therefore these powers can directly connect to this chip’s power pin and need no external resistors. There are two functions in these pins with 3.3V/3V. The first function is to supply internal logic power of the F71858 and the second function is that this voltage with 3.3V/3V is connected to internal serial resistors to monitor the VCC VSB 3.3V and VBAT voltage. The internal serial resistors are two 150K ohm, so that the internal reduced voltage is half of 3.3V/3V. F71858 only support three power voltage monitor but without hardware high low limit protect. So it will not trigger PME event when voltage too high or too low. Voltage Inputs 150K (directly connect to the chip) 3VCC VIN1 (directly connect to the chip) 3VSB 150K 3VBAT 8-bit ADC with 8 mV LSB D+ Typical BJT Connection 2N3906 Typical Thermister Connection GND The F71858 monitors a local and 2 remote temperature sensor. Both can be measured from -40°C to 145°C and there are four kinds of temperature to display. The temperature format is as the following table: Table mode 0: Display range is from 0°C to 127°C. The values in high byte registers are mean the temperature reading value and the unit is 1°C. The value in low bye register bit7~bit5 are temperature reading value and the unit is 0.125°C. Temperature Digital Output Digital Output (High byte) (Low byte) 0.125°C 0000 0000 001X XXXX 1°C 0000 0001 000X XXXX 90°C 0101 1010 000X XXXX 18 July, 2007 V.26P F71858 127.875°C 0111 1111 111X XXXX open 1011 1011 000X XXXX short 1100 1100 000X XXXX Table mode 1: Display range is from 0°C to 145°C. The values in high byte registers are mean the temperature reading value and the unit is 1°C. The value in low bye register bit7~bit5 are temperature reading value and the unit is 0.125°C. Temperature Digital Output Digital Output (High byte) (Low byte) 0.250°C 0000 0000 010X XXX0 1°C 0000 0001 000X XXX0 100°C 0110 0100 000X XXX0 145.875°C 1001 0001 111X XXX0 open 1011 1011 000X XXXX short 1100 1100 000X XXXX Table mode 2: (Default) Display range is from -40°C to 127°C. The values in high byte registers bit7 is sign bit and the values in high byte registers bit6~bit0 are mean the temperature reading value and the unit is 1°C. The value in low bye register bit7~bit5 are temperature reading value and the unit is 0.125°C. Temperature Digital Output Digital Output (High byte) (Low byte) -40°C 1101 1000 000X XXXX -1°C 1111 1111 000X XXXX 0°C 0000 0000 000X XXXX 100°C 0110 0100 000X XXXX 127.875°C 0111 1111 111X XXXX open 1011 1011 000X XXXX short 1100 1100 000X XXXX Table mode 3: Display range is from -40°C to 145°C. The values in high byte registers bit7~bit0 are mean the temperature reading value and the unit is 1°C. The value in low bye register bit7~bit5 are temperature reading value and the unit is 0.125°C. The sign bit is in low bye register bit0 19 July, 2007 V.26P F71858 Temperature Digital Output Digital Output (High byte) (Low byte) -40°C 1101 1000 000X XXX1 -1°C 1111 1111 111X XXX1 0°C 0000 0000 000X XXX0 1°C 0000 0001 000X XXX0 90°C 0101 1010 000X XXX0 127°C 0111 1111 111X XXX0 145.875°C 1001 0001 111X XXX0 open 1011 1011 000X XXXX short 1100 1100 000X XXXX Remote-sensor transistor manufacturers Manufacturer Model Number Panasonic 2SB0709 2N3906 Philips PMBT3906 Monitor Temperature from “thermal diode” Also, if the CPU, GPU or external circuits provide thermal diode for temperature measurement, the F71858 is capable to these situations. The build-in reference table is for PNP 2N3906 transistor, and each different kind of thermal diode should be matched with specific margin and BJT gain. The transistor is directly connected into temperature pins. ADC Noise Filtering The ADC is integrating type with inherently good noise rejection. Micro-power operation places constraints on high-frequency noise rejection; therefore, careful PCB board layout and suitable external filtering are required for high-accuracy remote measurement in electronically noisy environment. High frequency EMI is best filtered at D+ and D- with an external 2200pF capacitor. Too high capacitance may introduce errors due to the rise time of the switched current source. Nearly all noise sources tested cause the ADC measurement to be higher than the actual temperature, depending on the frequency and amplitude. Temperature HM_IRQ Signal (HM_IRQ# and PME#) There are two mode of temperature HM_IRQ function: 1. Hysteresis mode: 20 July, 2007 V.26P F71858 Over temperature event will trigger HM_IRQ# that shown as figure. In hysteresis mode, when monitored temperature exceeds the high temperature threshold value, HM_IRQ# will be asserted until the temperature goes below the hysteresis temperature. T High T HYST HM_IRQ# 2. High low limit mode: (default): When in high low limit mode HM_IRQ# for temperature is shown as figure. When monitored temperature exceeds the over-temperature threshold value, HM_IRQ# will be asserted until the temperature goes below the low limit temperature. T HIGH T LOW HM_IRQ# Temperature PME# There are two mode of temperature PME# function: 1. Hysteresis mode: PME# interrupt for temperature is shown as figure. Temperature exceeding high limit (low limit) or going below high hysteresis (low hysteresis) will cause an interrupt if the previous interrupt has been reset by writing “1” all the interrupt Status Register. 21 July, 2007 V.26P F71858 T HIGH T Hhys T LOW T Lhys PME# (pulse mode) * * * * *Interrupt Reset when Interrupt Status Registers are written 1 2. High low limit mode: (default): PME# interrupt for temperature is shown as figure. Temperature exceeding high limit or going below low limit will cause an interrupt if the previous interrupt has been reset by writing “1” all the interrupt Status Register. T HIGH T LOW PME# (pulse mode) * * *Interrupt Reset when Interrupt Status Registers are written 1 Fan speed count Inputs are provided by the signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage cannot be over 5V. If the input signals from the tachometer outputs are over the 5V, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as follows: 22 July, 2007 V.26P F71858 +12V +12V Pull-up resister 4.7K Ohms Pull-up resister < 1K or totem-pole output +12V 22K~30K FAN Out Fan Input +12V FANIN 1 GND 10K > 1K Fan Input FAN Out FANIN 1 GND F71858 3.3V Zener FAN Connector F71858 Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp Fan with Tach Pull-Up to +12V, or Totern-Pole Output and Register Attenuator +5V +5V Pull-up resister 4.7K Ohms Pull-up resister < 1K or totem-pole output +5V 1K~2.7K FAN Out Fan Input +5V FANIN1 GND 10K > 1K FAN Out Fan Input FANIN1 GND F71858 3.3V Zener FAN Connector F71858 Fan with Tach Pull-Up to +5V, or Totem-Pole Putput and Zener Clamp Fan with Tach Pull-Up to +5V, or Totern-Pole Output and Register Attenuator Determine the fan counter according to: Count = 1.5 × 10 6 RPM In other words, the fan speed counter has been read from register, the fan speed can be evaluated by the following equation. As for fan, it would be best to use 2 pulses tachometer output per round. RPM = 1.5 × 10 6 Count Fan speed control The F71858 provides 2 fan speed control methods: 1. DAC FAN CONTROL 2. PWM DUTY CYCLE DAC Fan Control The range of DC output is 0~3.3V, controlled by 8-bit register. 1 LSB is about 0.013V. The output DC voltage is amplified by external OP circuit, thus to reach maximum FAN OPERATION VOLTAGE, 12V. The output voltage will be given as followed: Output_voltage (V) = 3.3 × Programmed 8bit Register Value 255 23 July, 2007 V.26P F71858 And the suggested application circuit for DAC fan control would be: 8 12V 3 DC OUTPUT VOLTAGE + 2 D1 1N4148 LM358 4 - PMOS 1 R 4.7K JP1 R 10K C 47u 3 2 1 R 27K FANIN MONITOR C 0.1u R 10K CON3 R 3.9K DC FAN Control with OP PWM duty Fan Control The duty cycle of PWM can be programmed by a 8-bit register. The default duty cycle is set to 40%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows. Duty_cycle(%) = Programmed 8bit Register Value × 100% 255 +5V +12V R1 R1 R2 R2 PNP Transistor D G PWM Clock Input PNP Transistor D G NMOS S PWM Clock Input NMOS S + C + C FAN FAN - - Fan speed control mechanism There are some modes to control fan speed and they are 1.Manual mode, 2.Stage auto mode, 3.Linear auto mode. More detail, please refer the description of registers. Manual mode: For manual mode, it generally acts as software fan speed control. Stage auto mode: At this mode, the F71858 provides automatic fan speed control related to temperature variation of CPU/GPU or the system. The F71858 can provide four temperature boundaries and five intervals, and each interval has its related fan speed count. All these values should be set by BIOS first. Take figure as example. When temperature boundaries are set as 40, 50, 24 July, 2007 V.26P F71858 60, and 70°C and there are five intervals (each interval is 10°C). The related desired PWM duty for each interval are 100%, 85%, 65%, 50%, 40%. When the temperature is within 50~60°C, the duty is 65% will be load into FAN expect duty register. Then, the F71858 will adjust PWMOUT duty-cycle to meet the expected value. It can be said that the fan will be turned on with a specific speed set by BIOS and automatically controlled with the temperature variation. The F71858 will take charge of all the fan speed control and need no software support. Desired duty (default 100%) Boundtemp1 (default 70'C) (default 85%) Boundtemp2 (default 60'C) (default 65%) Boundtemp3 (default 50'C) (default 50%) Boundtemp4 (default 40'C) (default 40%) There are two examples as below: A. Stage auto mode (PWM Duty) Set temperature as 60°C, 50°C, 40°C, 30°C and Duty as 100%, 90%, 80%, 70%, 60% PWM duty 60 Degree C 50 Degree C hysteresis 47 Degree C 100% 0xFF 90% 0xE5 80% 0xCC 70% 0xB2 60% 0x99 40 Degree C 30 Degree C Temp. Fan Speed a b c d a. Once temp. is under 30°C, the lowest fan speed keeps 60% PWM duty b. Once temp. is over 30°C,40°C,50°C, the fan speed will vary from 60% to 90% PWM duty and increase with temp. level. c. Once temp. keeps in 55°C, fan speed keeps in 90% PWM duty d. If set the hysteresis as 3°C (default 4°C), once temp reduces under 47°C, fan speed reduces to 80% PWM duty and stays there. B. Stage auto mode (RPM%) 25 July, 2007 V.26P F71858 Set temperature as 60°C, 50°C, 40°C, 30°C and assume the Full Speed is 6000rpm, set 90% of full speed RPM(5400rpm), 80%(4800rpm), 70%(4200rpm), 60%(3600rpm) of full speed RPM 6000RPM 60 Degree C 90%(5400RPM) 50 Degree C hysteresis 47 Degree C 80%(4800RPM) 40 Degree C 70%(4200RPM) 30 Degree C 60%(3600RPM) Temp. Fan Speed a b c d a. Once temp. is under 30°C, the lowest fan speed keeps 60% of full speed (3600RPM). b. Once temp. is over 30°C,40°C,50°C, the fan speed will vary from 3600RPM to 5400RPM and increase with temp. level. c. Once temp. keeps in 55°C, fan speed keeps in 90% of full speed (5400RPM) d. If set the hysteresis as 3°C (default 4°C), once temp reduces under 47°C, fan speed reduces to 4800RPM and stays there. Linear auto mode: Otherwise, F71858 supports linear auto mode. Below has two examples to describe this mode. More detail, please refer the register description. A. Linear auto mode (PWM Duty) Set temperature as 70°C, 60°C, 50°C, 40°C and Duty as 100%, 70%, 60%, 50%, 40% PWM duty 100% 70 Degree C hysteresis 65 Degree C 70% 60 Degree C 60% 50 Degree C 50% 40 Degree C Temp. Fan Speed 40% a b c d a. Once temp. is under 40°C, the lowest fan speed keeps 40% PWM duty b. Once temp. is over 40°C,50°C,60°C, the fan speed will vary from 40% to 70% PWM duty 26 July, 2007 V.26P F71858 and linearly increase with temp. variation. The temp.-fan speed monitoring and flash interval is 1sec. c. Once temp. goes over 70°C, fan speed will directly increase to 100% PWM duty (full speed) d. If set the hysteresis as 5°C(default is 4°C), once temp reduces under 65°C (not 70°C), fan speed reduces from 100% PWM duty and decrease linearly with temp.. B. Linear auto mode (RPM%) Set temperature as 70°C, 60°C, 50°C, 40°C and if full speed is 6000RPM, setting 100%, 70%, 60%, 50%, 40% of full speed. 6000RPM 70 Degree C hysteresis 65 Degree C 70%(4200RPM) 60 Degree C 60%(3600RPM) 50 Degree C 50%(3000RPM) 40 Degree C 40%(2400RPM) Temp. Fan Speed a b c d a. Once temp. is under 40°C, the lowest fan speed keeps 40% of full speed (2400RPM) b. Once temp. is over 40°C,50°C,60°C, the fan speed will vary from 40% to 70% of full speed and almost linearly increase with temp. variation. The temp.-fan speed monitoring and flash interval is 1sec. c. Once temp. goes over 70°C, fan speed will directly increase to full speed 6000RPM. d. If set the hysteresis as 5°C, once temp reduces under 65°C (not 70°C), fan speed reduces from full speed and decrease linearly with temp.. PWMOUT Duty-cycle operating process In both “Manual RPM” and “Temperature RPM” modes, the F71858 adjust PWMOUT duty-cycle according to current fan count and expected fan count. It will operate as follows: (1). When expected count is 0xFFF, PWMOUT duty-cycle will be set to 0x00 to turn off fan. (2). When expected count is 0x000, PWMOUT duty-cycle will be set to 0xFF to turn on fan with full speed. (3). If both (1) and (2) are not true, When PWMOUT duty-cycle decrease to MIN_DUTY(≠ 00h), obviously the duty-cycle will decrease to 00h next, When F71858 up the fan speed will keep duty-cycle at start duty for 27 July, 2007 V.26P F71858 1.2 seconds. After that, the F71858 starts to compare current fan count and expected count in order to increase or decrease its duty-cycle. This ensures that if there is any glitch during the period, the F71858 will ignore it. Start Duty Stop Duty FAN HM_IRQ Signal (HM_IRQ# and PME#) Fan fault will be asserted when the fan speed doesn’t meet the expected fan speed within a programmable period (default is 11 seconds) or when fan stops with respect to PWM duty-cycle which should be able to turn on the fan. There are two conditions may cause the FAN_FAULT# event. (1). When PWM_Duty reaches 0xFF, the fan speed count can’t reach the fan expected count in time. 11 sec(default) Current Fan Count Expected Fan Count 100% Duty-cycle Fan_Fault# (2). After the period of detecting fan full speed, when PWM_Duty > Min. Duty, and fan count still in 0xFFF. 6.4 LED function The F71858 provides two LEDs to indicate system state (S0, S3, and S5). Every state has indicate 4 kinds of mode (1) always 0 (2) oscillate 1Hz (3) oscillate 1/2 Hz (4) always 1 and can be controlled by configuration register. When system is in s0 state, LED1 defaults 0 and LED2 defaults 1. When system is in s3 state, LED1 and LED2 oscillate 1Hz. When system is in s5 state, LED1 defaults 1 and LED2 defaults 0. 28 July, 2007 V.26P F71858 6.5 AMDSI and Intel SST PECI Function The F71858 provides Intel SST/PECI/AMDSI interfaces for new generational CPU temperature sensing. In AMDSI interface, there are SIC and SID signals for temperature information reading from AMD CPU. The SIC signal is for clocking use, the other is for data transferring. More detail please refer register description. VDDIO 300 300 F71858 AMD CPU SIC SIC SID SID In Intel SST and PECI interfaces, the F71858 can connect to CPU/SST directly. The F71858 can read the temperature data from CPU, than the fan control machine of F71858 can implement the Fan to cool down CPU temperature. As same as PECI, chipset can get information from F71858 including CPU temperature, system temperature (F71858 provides D+/D- for system temperature sensing), fan speed status by SST. The application circuit is as below. More detail please refer the register description. Intel ICH8 F71858 SST SST Intel F71858 CPU PECI PECI 100K 29 July, 2007 V.26P F71858 7. Register Description 7.1 Global Control Registers The configuration register is used to control the behavior of the corresponding devices. To configure the register, using the index port to select the index and then writing data port to alter the parameters. The default index port and data port are 0x4E and 0x4F respectively. To enable configuration, the entry key 0x87 must be written to the index port. To disable configuration, write exit key 0x78 twice or key 0xaa once to the index port. Following is a example to enable configuration and disable configuration by using debug. -o 4e 87 7.1.1 -o 4e 87 ( enable configuration ) -o 4e aa ( disable configuration ) Software Reset Register Index 02h Bit Name 7-1 Reserved 0 7.1.2 SOFT_RST Name 7-0 LDN Bit Description - - Reserved R/W 0 Write 1 to reset the register and device powered by VDD ( VCC ). Logic Device Number Register Index 07h Bit 7.1.3 R/W Default R/W Default R/W 00h Description 00h: Select KBC device configuration registers. 01h: Select PME & ACPI device configuration registers. 02h: Select hardware monitor device configuration registers. Chip ID Register Index 20h Name 7-0 CHIP_ID1 R/W Default R 05h Description Chip ID 1 of F71858. 30 July, 2007 V.26P F71858 7.1.4 Bit Chip ID Register Index 21h Name 7-0 CHIP_ID2 7.1.5 Bit Bit Name Bit Name Chip ID2 of F71858. R/W Default R 19h Description Vendor ID 1 of Fintek devices. R/W Default R 34h Description Vendor ID 2 of Fintek devices. Port Select Register Index 25h Name 7-5 Reserved 4 07h Vendor ID Register Index 24h 7-0 VENDOR_ID2 7.1.7 R Description Vendor ID Register Index 23h 7-0 VENDOR_ID1 7.1.6 R/W Default PORT_4E_EN R/W Default Description - - Reserved. R/W 1 The port could be changed by writing this register. 0: Configuration register port is 2E/2F. 1: Configuration register port is 4E/4F. (Default) 3-0 Reserved 7.1.8 Bit 7 - - Reserved. Select KB/MO Wakeup Register Index 27h Name Dis_wake R/W Default R/W 0 Description 1: disable KB/MO wakeup function 0: enable KB/MO wakeup function. 6-4 Reserved 2 MO_SEL - 0 Reserved. R/W 0 Select mouse Key to wakeup host 0: click mouse key 1: any mouse key 3,1-0 KB_SEL R/W 000 Select combination key to wakeup host 000: CTRL + ESC 001: CTRL + F1 010: CTRL +SPACE 011: ANY KEY 100:windows 98 wakeup up key 31 July, 2007 V.26P F71858 7.2 KBC Registers 7.2.1 Logic Device Number Register Logic Device Number Register Index 07H Bit Name 7-0 LDN R/W Default R/W 00h Description 00h: Select KBC device configuration registers. 01h: Select PME & ACPI device configuration registers. 02h: Select hardware monitor device configuration registers. 7.2.2 KBC Configuration Registers KBC Device Enable Register Index 30h Bit Name 7-1 Reserved 0 KBC_EN R/W Default Description - - Reserved R/W 1 0: disable KBC. 1: enable KBC. Base Address High Register Index 60h Bit Name 7-0 BASE_ADDR_HI R/W Default R/W 00h Description The MSB of KBC base address. Base Address Low Register Index 61h Bit Name 7-0 BASE_ADDR_LO R/W Default R/W 60h Description The LSB of KBC base address. Keyboard IRQ Channel Enable Register Index 70h Bit Name 7-6 Reserved 0 ENKBCIRQ R/W Default - - R/W 1B Description Reserved. Enable the IRQ channel for Keyboard. Mouse IRQ Channel Enable Register Index 72h Bit Name 7-6 Reserved 0 ENMOCIRQ R/W Default - - R/W 1B Description Reserved. Enable the IRQ channel for Mouse. 32 July, 2007 V.26P F71858 7.3 ACPI and PME Registers 7.3.1 Logic Device Number Register Logic Device Number Register Index 07H Bit Name 7-0 LDN R/W Default R/W 00h Description 00h: Select KBC device configuration registers. 01h: Select PME & ACPI device configuration registers. 02h: Select hardware monitor device configuration registers. 7.3.2 ACPI and PME Configuration Registers Device Enable Register Index 30h Bit Name 7-1 Reserved 0 PME_EN R/W Default Description - - Reserved R/W 0 0: disable PME. 1: enable PME. PME Event Enable Register Index F0h Bit Name R/W Default Description 7 Reserved - - Reserved 6 MS_PME_EN R/W 0 PS/2 mouse PME event enable. 0: disable PS/2 mouse PME event. 1: enable PS/2 mouse PME event. 5 KB_PME_EN R/W 0 PS/2 keyboard PME event enable. 0: disable PS/2 keyboard PME event. 1: enable PS/2 keyboard PME event. - - Reserved R/W 0 Hardware Monitor PME event enable. 0: disable Hardware Monitor PME event. 1: enable Hardware Monitor PME event. 4-1 Reserved 0 HM_PME_EN PME Event Status Register Index F1h Bit Name 7 Reserved 6 5 R/W Default Description - - Reserved MS_PME_ST R/W 0 PS/2 mouse PME event status. 0: PS/2 mouse has no PME event. 1: PS/2 mouse has a PME event to assert. Write 1 to clear to be ready for next PME event. KB_PME_ST R/W 0 PS/2 keyboard PME event status. 0: PS/2 keyboard has no PME event. 1: PS/2 keyboard has a PME event to assert. Write 1 to clear to be ready for next PME event. - - Reserved 4-1 Reserved 33 July, 2007 V.26P F71858 0 HM_PME_ST R/W 0 Hardware Monitor PME event status. 0: Hardware Monitor has no PME event. 1: Hardware Monitor has a PME event to assert. Write 1 to clear to be ready for next PME event. ACPI Control Register Index F4h Bit 7 Name R/W Default Description TS3 R/W 0 Set to 1 into S1 state. Two wake up methods: 1. PME wake up event Æ Must write this bit to 0. 2. PS_OUT# wake up event Æ Auto clear this bit. 6-5 Reserved - - Reserved. 4 ENKBWAKEUP R/W 0 0:disable keyboard wakeup signal (PS_OUT#) 1:enable keyboard wakeup signal 3 ENMOWAKEUP R/W 0 0:disable mouse wakeup signal (PS_OUT#) 1:enable mouse wakeup signal R/W 11 The ACPI Control the PSON# to always on or always off or keep last state 00 : keep last state 10 : Always on 01 : Reserved (always on) 11: Always off R/W 0 When VSB 3V comes, it will set to 1, and write 1 to clear it 2-1 PWRCTRL 0 VSB_PWR_LOSS ACPI Control Register Index F5h Bit Name 7 SEL_S3 6 Reserved R/W Default Description R/W 0 1:selected by TS3 TS3 0: chip decided into S3 state from S3 pin 1 : chip direct into S3 state 0: chip decided into S3 state from VDD (VCC) power detect ok., which chip detects voltage circuit - - Reserved 5 BY_PASS_LRST R/W 1 Bypass LRESET# to PCIRESET[5:1] 4 RSTCON_EN R/W 0 R/W 11 1 Bypass_db R/W 0 PWROK and PCIRST[5:1] are affect by RSTCON bit. When RSTCON set 0, PWROK output RST_IN and VDD (VCC) voltage detect ok. RSTCON set to 1, PWROK only output VDD (VCC) voltage detect ok. When RSTCON set to 0, PCIRST[5:1] output LRESET# and confreg reset dat(0XF8) . RSTCON set tp 1, PCIRST[5:1] output RST_IN, LRESET# and confreg reset dat(0XF8). The PWROK delay timing from VCC3VOK by followed setting 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms BYPASS the S3#/S4#/PSIN#/RSTIN# Pins. 0 VINDB_EN R/W 1 Enable the RSTIN# debounce. 3-2 DELAY ACPI Soft reset Register Index F6h Bit 7 Name SOFT_RST_ACPI R/W Default W 0 Description Software Reset to ACPI Set to 1 to reset ACPI 34 July, 2007 V.26P F71858 6-0 Reserved - - Reserved ACPI reset enable Register Index F7h Bit Name 7-5 Reserved 4-0 PCI_RST_EN R/W Default R/W - Description Reserved 5’h1F RESET output enable ACPI reset data Register Index F8h Bit Name 7-5 Reserved 4-0 PCI_RST_DAT R/W Default - - W 5’h0 Description Reserved Write 1 to RESET output low pulse 2ms. LED S0 status Register Index F9h Bit Name 7 phase 6 Reserved 5-4 LED2_S0 3 phase 2 Reserved 1-0 LED1_S0 R/W Default Description R/W 0 When bit 7 is the same of the bit 3, LED2 oscillate phase is the same LED1. - - Reserved R/W 2’b11 Indicate LED2 response when system in S0 state 00:LED assert 0 01: oscillate 1Hz 10: oscillate 1/2Hz 11: tri-state R/W 0 When bit 7 is the same of the bit 3, LED2 oscillate phase is the same LED1. - - Reserved W 2’b00 Indicate LED1 response when system in S0 state 00:LED assert 0 01: oscillate 1Hz 10: oscillate 1/2Hz 11: tri-state LED S3/S5 ststus Register Index FAh Bit Name R/W Default Description 7-6 LED2_S5 R/W 2’b00 Indicate LED2 response when system in S5 state 00:LED assert 0 01: oscillate 1Hz 10: oscillate 1/2Hz 11: tri-state 5-4 LED2_S3 R/W 2’b01 Indicate LED2 response when system in S3 state 00:LED assert 0 01: oscillate 1Hz 10: oscillate 1/2Hz 11: tri-state 3-2 LED1_S5 R/W 2’b11 Indicate LED1 response when system in S5 state 00:LED assert 0 01: oscillate 1Hz 10: oscillate 1/2Hz 11: tri-state. 1-0 LED1_S3 W 2’b01 Indicate LED1 response when system in S3 state 00:LED assert 0 01: oscillate 1Hz 10: oscillate 1/2Hz 11: tri-state 35 July, 2007 V.26P F71858 7.4 Hardware Monitor Registers (Index port: 0x295; Data port: 0x296) 7.4.1 Logic Device Number Register Logic Device Number Register Index 07H Logic Device Number Register Index 07H Bit Name 7-0 LDN R/W Default R/W 00h Description 00h: Select KBC device configuration registers. 01h: Select PME & ACPI device configuration registers. 02h: Select Hardware Monitor device configuration registers. 7.4.2 Hardware Monitor Configuration Registers KBC Device Enable Register Index 30h Bit Name 7-1 Reserved 0 HM_EN R/W Default Description - - Reserved R/W 1 0: disable hardware monitor. 1: enable hardware monitor. Base Address High Register Index 60h Bit Name 7-0 BASE_ADDR_HI R/W Default R/W 02h Description The MSB of HM base address. Base Address Low Register Index 61h Bit Name 7-0 BASE_ADDR_LO R/W Default R/W 95h Description The LSB of HM base address. 7.4.3 Hardware Monitor Device Register 7.4.3.1 Configuration Register Index 01h Bit Name R/W Default Description 7 Reserved R 0 Reserved 6 Reserved R/W 0 Reserved 5-4 Reserved R 0 Reserved 3 Reserved R/w 0 Reserved 2 POWER_DOWN R/W 0 Hardware monitor function power down. 1 FAN_START R/W 1 0 V_T_START R/W 1 et one to enable startup of fan monitoring operations; a zero puts the part in standby mode. Set one to enable startup of temperature and voltage monitoring operations; a zero puts the part in standby mode. 7.4.3.2 Configuration Register Index 02h Bit Name R/W Default Description 36 July, 2007 V.26P F71858 7-6 Reserved 5-4 ALERT_MODE 4-0 Reserved R 0 Return 0. 0 00: The ALERT# will be low active level mode. 01: The ALERT# will be low active pulse mode. (160us) 10: The ALERT # will indicate by 1Hz LED function. 11: The ALERT # will indicate by (400/800HZ) BEEP output. 0 -- R/W R 7.4.3.3 PECI SST AMDSI Interface Configuration Register Index 0Ah Bit Name R/W Default 7-6 Reserved R/W 0 Reserved. 5 T1_IIR_EN R/W 0 Set 1 to enable the IIR for AMDSI/PECI reading. 4 SST_EN R/W 0 Enable SST Interface. 00 00: PECI output high level will be 1.23V 01: PECI output high level will be 1.13V 10: PECI output high level will be 1.00V 11: PECI output high level will be 1.00V Select the CPU temperature measure method 00: External thermal diode. 01: PECI interface. 10: AMDSI interface. 11: Reserved. 3-2 PECI_POWER_SEL R/W 0 1-0 MEAS_TYPE R/W Description 7.4.3.4 AMDSI Version Register Index 0Bh Bit Name 7-0 AMDSI_VER (MEAS_TYPE ==2’b10) R/W Default R - Description When AMDSI interface enable, this will be AMDSI version register. Return the AMDSI version. 7.4.3.5 Dual Single Core select Register Index 0Bh Bit Name 7-2 Reserved (MEAS_TYPE ==2’b01) R/W Default R 1 TEMPVALUE_SEL W 0 Dual Core_EN R/W Description - Reserved 0 When Dual Core CPU selection. Temperature value measurement method will be select by this bit. 0: Average dual cores’ temperature. 1: Select higher one temperature of these two cores. When PECI interface enable, this will be Dual Single Core select register. 0: Single Core CPU selection 1: Dual Core CPU selection 0 7.4.3.6 TCC Activation Temperature Register Index 0Ch Bit 7-0 Name TCC_TEMP R/W Default R/W 0 Description TCC Activation Temperature. The absolute value of CPU temperature is calculated by the equation: CPU_TEMP = TCC_TEMP + PECI Reading. The range of this register is 0 ~ 255. 7.4.3.7 AMDSI Node ID Register Index 0Ch Bit Name 7-0 NODE_ID (MEAS_TYPE == 2’b01) (MEAS_TYPE ==2’b10) R/W Default R - Description Return the AMDSI node id. 37 July, 2007 V.26P F71858 7.4.3.8 SST Address Register Index 0Dh Bit Name 7-0 SST_ADDR R/W Default R/W Description 8’h4C Address for SST interface. Programmable. 7.4.3.9 CPU Temp. Measure Select Register Index 0Eh Bit Name R/W Default 7-4 Reserved - 3 ADD R/W 0 Reserved. 0 Temperature scale selection. 1: Temp. Measure = Reading Value + Reading Value* 2-Scale[2:0] 0: Temp. Measure = Reading Value - Reading Value* 2-Scale[2:0] When ADD=1, the Temp. Measure is 000: 1 * Reading Value 001: 3/2 * Reading Value …….. 110: 65/64 * Reading Value 111: 129/128 * Reading Value ------------------------------------------------------------------------When ADD=0, the Temp. Measure is 000: 1 * Reading Value 001: 1/2 * Reading Value …….. 110: 63/64 * Reading Value 111: 127/128 * Reading Value 000 2-0 SCALE[2:0] Description R/W 7.4.3.10 Voltage reading and limit Index 20h- 22h Address Attribute 20h 21h 22h RO RO RO Default Value ---- Description VCC3V reading. The unit of reading is 8mV. VSB3V reading. The unit of reading is 8mV. VBAT3V reading. The unit of reading is 8mV. 7.4.3.11 Temperature PME# Enable Register Index 60h Bit Name Description R 0 Reserved R/W 0 R/W 0 EN_L_HIGH_PME R/W 0 3 Reserved R 0 A one enables the corresponding interrupt status bit for PME# interrupt. (CR61 bit6) A one enables the corresponding interrupt status bit for PME# interrupt. (CR61 bit5) A one enables the corresponding interrupt status bit for PME# interrupt. (CR61 bit4) Reserved 2 EN_ T2_LOW_PME R/W 0 R/W 0 R/W 0 7 6 5 4 1 0 Reserved R/W Default EN_T2_HIGH_PME EN_T1_HIGH_PME EN_ T1_LOW_PME EN_L_LOW_PME A one enables the corresponding interrupt status bit for PME# interrupt. (CR61 bit2) A one enables the corresponding interrupt status bit for PME# interrupt. (CR61 bit1) A one enables the corresponding interrupt status bit for PME# interrupt. (CR61 bit0) 38 July, 2007 V.26P F71858 7.4.3.12 Temperature Interrupt Status Register Index 61h Bit 7 6 Name Reserved T2_HIGH_STS R/W Default R Reserved 0 H_L_LIMIT_MODE set to 1 (CR69 bit 4) “default” Set when the TEMP2(CR74) exceeds the HIGH limit(CR84) or when temperature return from over HIGH to under LOW limit(CR85). Write 1 to clear this bit, write 0 will be ignored. H_L_LIMIT_MODE set to 0 (CR69 bit 4) Set when the TEMP2(CR74) exceeds the HIGH limit(CR84) or when temperature return from over HIGH to under “HIGH limit –hysteresis (CR6D)”. Write 1 to clear this bit, write 0 will be ignored. H_L_LIMIT_MODE set to 1 (CR69 bit 4) “default” Set when the TEMP1(CR72) exceeds the HIGH limit(CR82) or when temperature return from over HIGH to under LOW limit(CR83). Write 1 to clear this bit, write 0 will be ignored. H_L_LIMIT_MODE set to 0 (CR69 bit 4) Set when the TEMP1(CR72) exceeds the HIGH limit(CR82) or when temperature return from over HIGH to under “HIGH limit –hysteresis (CR6C)”. Write 1 to clear this bit, write 0 will be ignored. R/W 0 5 T1_HIGH_STS R/W 0 4 LOCAL_HIGH_STS R/W 3 Reserved R 0 0 2 T2_LOW_STS R/W 0 1 T1_LOW_STS R/W 0 0 LOCAL_LOW_STS Description 0 R/W H_L_LIMIT_MODE set to 1 (CR69 bit 4) “default” Set when the LOCAL TEMP (CR70) exceeds the HIGH limit(CR80) or when temperature return from over HIGH to under LOW limit(CR81). Write 1 to clear this bit, write 0 will be ignored. H_L_LIMIT_MODE set to 0 (CR69 bit 4) Set when the LOCAL TEMP exceeds the HIGH limit (CR80) or when temperature return from over HIGH to under “HIGH limit –hysteresis (CR6C)”.. Write 1 to clear this bit, write 0 will be ignored. Reserved H_L_LIMIT_MODE set to 1 (CR69 bit 4) “default” This bit always return 0. H_L_LIMIT_MODE set to 0 (CR69 bit 4) Set when the TEMP2 exceeds the LOW limit (CR85) or when temperature return from over HIGH to under “LOW limit –hysteresis (CR6D)”.. Write 1 to clear this bit, write 0 will be ignored. H_L_LIMIT_MODE set to 1 (CR69 bit 4) “default” This bit always return 0. H_L_LIMIT_MODE set to 0 (CR69 bit 4) Set when the TEMP1 exceeds the LOW limit (CR83) or when temperature return from over HIGH to under “LOW limit –hysteresis (CR6C)”.. Write 1 to clear this bit, write 0 will be ignored. H_L_LIMIT_MODE set to 1 (CR69 bit 4) “default” This bit always return 0. H_L_LIMIT_MODE set to 0 (CR69 bit 4) Set when the LOCAL TEMP exceeds the LOW limit (CR81) or when temperature return from over HIGH to under “LOW limit –hysteresis (CR6C)”.. Write 1 to clear this bit, write 0 will be ignored. 7.4.3.13 Temperature Real Time Status Register Index 62h Bit 7 Name Reserved R/W Default R 0 Description Reserved 39 July, 2007 V.26P F71858 0 6 T2_HIGH_EXC R/W 0 5 T1_HIGH_EXC R/W 0 4 3 LOCAL_HIGH_EXC R/W Reserved R 0 0 2 T2_LOW_EXC R/W 0 1 T1_LOW_EXC R/W 0 0 LOCAL_LOW_EXC R/W H_L_LIMIT_MODE set to 1 (CR69 bit 4) Set when the TEMP2 exceeds the HIGH limit (CR84). Clear when the TEMP2 is below the LOW limit (CR85) –hysteresis (CR6D) temperature. H_L_LIMIT_MODE set to 0 (CR69 bit 4) Set when the TEMP2 exceeds the HIGH limit (CR84). Clear when the TEMP2 is below the “HIGH limit (CR84) –hysteresis (CR6D)” temperature. H_L_LIMIT_MODE set to 1 (CR69 bit 4) Set when the TEMP1 exceeds the HIGH limit(CR82). Clear when the TEMP1 is below the LOW limit (CR83) –hysteresis (CR6C) temperature. H_L_LIMIT_MODE set to 0 (CR69 bit 4) Set when the TEMP1 exceeds the HIGH limit (CR82). Clear when the TEMP1 is below the “HIGH limit (CR82)–hysteresis (CR6C)” temperature. H_L_LIMIT_MODE set to 1 (CR69 bit 4) Set when the Local TEMP exceeds the HIGH limit (CR80). Clear when the Local TEMP is below the LOW limit (CR81) –hysteresis (CR6C) temperature. H_L_LIMIT_MODE set to 0 (CR69 bit 4) Set when the Local TEMP exceeds the HIGH limit (CR80). Clear when the Local TEMP is below the “HIGH limit(CR80)–hysteresis(CR6C)” temperature. Reserved H_L_LIMIT_MODE set to 1 (CR69 bit 4) This bit always return 0. H_L_LIMIT_MODE set to 0 (CR69 bit 4) Set when the TEMP2 exceeds the LOW limit (CR85). Clear when the TEMP2 is below the “LOW limit(CR85) –hysteresis (CR6D)” temperature. H_L_LIMIT_MODE set to 1 (CR69 bit 4) This bit always return 0. H_L_LIMIT_MODE set to 0 (CR69 bit 4) Set when the TEMP1 exceeds the LOW limit (CR83). Clear when the TEMP1 is below the “LOW limit(CR83) –hysteresis (CR6C)” temperature. H_L_LIMIT_MODE set to 1 (CR69 bit 4) This bit always return 0. H_L_LIMIT_MODE set to 0 (CR69 bit 4) Set when the Local TEMP exceeds the LOW limit (CR81). Clear when the Local TEMP is below the “LOW limit(CR81)–hysteresis (CR6C)” temperature. 7.4.3.14 ALERT# Output Enable Register 1 Index 66h Bit Name R/W Default Description 7-3 Reserved R 0h -- 2 EN_T2_ALERT R/W 0 1 EN_T1_ALERT R/W 1 When T2_HIGH_EXC(CR65 bit6) is active and this bit is Enabled. Then pin ALERT# will be active and user can select ALERT mode from (CR02). When T1_HIGH_EXC(CR65 bit5) is active and this bit is Enabled. Then pin ALERT# will be active and user can select ALERT mode from (CR02). When LOCAL_HIGH_EXC(CR65 bit4) is active and this bit is Enabled. Then pin ALERT# will be active and user can select ALERT mode from (CR02). 0 0 EN_LOCAL_ALERT R/W 7.4.3.15 Temperature PME# mode and Table Select Register -- Index 69h Bit 7-5 Name Reserved R/W Default R 0h Description -- 40 July, 2007 V.26P F71858 4 H_L_LIMIT_MODE R/W 1 3-2 Reserved R 0h 1-0 TEMP_TABLE_SEL R/W 2h If H_L_LIMIT_MODE set to 1 TEMP exceeds will be set when over HIGH limit. And clear when the TEMP below the LOW limit –hysteresis temperature. Else if H_L_LIMIT_MODE set to 0 TEMP exceeds will be set when over HIGH/LOW limit. And clear when the TEMP below the “HIGH/LOW limit–hysteresis” temperature. -00: Temperature display range 0’C~127’C 01: Temperature display range 0’C~145’C 10: Temperature display range -40’C ~127’C 11: Temperature display range -40’C ~145’C (default) 7.4.3.16 LOCAL and TEMP1 Limit Hysteresis Select Register -- Index 6Ch Bit Name R/W Default 7-4 TEMP1_HYS R/W 0h 3-0 LOCAL_HYS R/W 0h Description TEMP1 will exceeds when over limit until under then “limit - TEMP1_HYS (hysteresis)” L TEMP will exceeds when over limit until under then “limit – L TEMP_HYS (hysteresis)” 7.4.3.17 TEMP2 and TEMP3 Limit Hysteresis Select Register -- Index 6Dh Bit Name R/W Default Description 7-4 Reserved R 0h Reserved 3-0 TEMP2_HYS R/W 0h TEMP2 will exceeds when over limit until under then “limit – TEMP2_HYS (hysteresis)” 7.4.3.18 DIODE OPEN Status Register -- Index 6Fh Bit Name 7-3 Reserved R/W Default Description RO 0h Reserved 2 T2_DIODE_OPEN RO 0h External diode 2 is open (1) or short (0) 1 T1_DIODE_OPEN RO 0h External diode 1 is open (1) or short (0) 0 T0_DIODE_OPEN RO 0h Internal diode 0 is open (1) or short (0) 7.4.3.19 Temperature Register Index 70h- 8Fh Address Attribute Default Value 70h RO -- 71h RO -- Description When TEMP_TABLE_SEL=0x0 (CR69) Local temperature[10:3] reading. The unit of reading is 1ºC.At the moment of reading this register. Maximum display is 127’C, minimum display is 0’C When TEMP_TABLE_SEL=0x1 (CR69) Local temperature[10:3] reading. The unit of reading is 1ºC.At the moment of reading this register. Maximum display is 145’C, minimum display is 0’C When TEMP_TABLE_SEL=0x2 (CR69) “default” Local temperature[10:3] reading. The unit of reading is 1ºC.At the moment of reading this register. Bit10 is the sign bit of the local temperature. Maximum display is 127’C, minimum display is -40’C When TEMP_TABLE_SEL=0x3 (CR69) Local temperature[10:3] reading. The unit of reading is 1ºC.At the moment of reading this register. CR71 Bit0 is the sign bit of the local temperature. Maximum display is 145’C, minimum display is -40’C (when open this byte will return 0xBB, short this byte will return 0xCC) CR71 bit7-bit5 are the Local temperature reading value[2:0]. The unit of reading is 0.125ºC. When TEMP_TABLE_SEL=0x3 (CR69) 41 July, 2007 V.26P F71858 CR71 bit 0 is the sign bit of the Local temperature. When TEMP_TABLE_SEL=0x0 (CR69) º Temperature 1 [10:3] reading. The unit of reading is 1 C.At the moment of reading this register. Maximum display is 127’C, minimum display is 0’C When TEMP_TABLE_SEL=0x1 (CR69) Temperature 1 [10:3] reading. The unit of reading is 1ºC.At the moment of reading this register. Maximum display is 145’C, minimum display is 0’C When TEMP_TABLE_SEL=0x2 (CR69) “default” Temperature 1 [10:3] reading. The unit of reading is 1ºC.At the moment of reading this register. Bit10 is the sign bit of the temperature 1. Maximum display is 127’C, minimum display is -40’C When TEMP_TABLE_SEL=0x3 (CR69) Temperature 1 [10:3] reading. The unit of reading is 1ºC.At the moment of reading this register. CR73 Bit0 is the sign bit of the temperature 1. Maximum display is 145’C, minimum display is -40’C (when open this byte will return 0xBB, short this byte will return 0xCC) CR73 bit7-bit5 are the temperature 1 reading value[2:0]. The unit of reading is 0.125ºC. When TEMP_TABLE_SEL=0x3 (CR69) CR73 bit 0 is the sign bit of the temperature 1. When TEMP_TABLE_SEL=0x0 (CR69) º Temperature 2[10:3] reading. The unit of reading is 1 C.At the moment of reading this register. Maximum display is 127’C, minimum display is 0’C When TEMP_TABLE_SEL=0x1 (CR69) Temperature 2 [10:3] reading. The unit of reading is 1ºC.At the moment of reading this register. Maximum display is 145’C, minimum display is 0’C When TEMP_TABLE_SEL=0x2 (CR69) “default” Temperature 2 [10:3] reading. The unit of reading is 1ºC.At the moment of reading this register. Bit10 is the sign bit of the temperature 2. Maximum display is 127’C, minimum display is -40’C When TEMP_TABLE_SEL=0x3 (CR69) Temperature 2 [10:3] reading. The unit of reading is 1ºC.At the moment of reading this register. CR75 Bit0 is the sign bit of the temperature 2. Maximum display is 145’C, minimum display is -40’C (when open this byte will return 0xBB, short this byte will return 0xCC) CR75 bit7-bit5 are the temperature 2 reading value[2:0]. The unit of reading is º 0.125 C. When TEMP_TABLE_SEL=0x3 (CR69) CR75 bit 0 is the sign bit of the temperature 2. 72h RO -- 73h RO -- 74h RO -- 75h RO -- 76-7Fh RO FFh Reserved 80h R/W 46h Local Temperature sensor HIGH limit. The unit is 1ºC. 81h R/W 3Ch Local Temperature sensor LOW limit. The unit is 1ºC. 82h R/W 64h Temperature sensor 1 HIGH limit. The unit is 1 C. 83h R/W 55h Temperature sensor 1 LOW limit. The unit is 1 C. 84h R/W 64h Temperature sensor 2 HIGH limit. The unit is 1ºC. 85h R/W 55h Temperature sensor 2 LOW limit. The unit is 1ºC. 86~8Dh RO FFH Reserved º º 7.4.3.20 Temperature Filter Select Register -- Index 8Eh Bit 7-6 5-4 Name Reserved IIR-QUEUR2 R/W Default R R/W Description 0h -- 1h The queue time for second filter to quickly update values. 00: 8 times. 01: 16 times. (default). 10: 24 times. 11: 32 times. 42 July, 2007 V.26P F71858 3-2 IIR-QUEUR1 R/W 1h 1-0 IIR-QUEUR-LOCAL R/W 1h The queue time for second filter to quickly update values. 00: 8 times. 01: 16 times. (default). 10: 24 times. 11: 32 times. The queue time for second filter to quickly update values. 00: 8 times. 01: 16 times. (default). 10: 24 times. 11: 32 times. 7.4.3.21 FAN PME# Enable Register Index 90h Bit Name 7-3 Reserved 2 R/W Default RO 0h EN_FAN3_PME R/W 0h 1 EN_FAN2_PME R/W 0h 0 EN_FAN1_PME R/W 0h Description Reserved A one enables the corresponding interrupt status bit for PME# interrupt. (CR91 bit2) A one enables the corresponding interrupt status bit for PME# interrupt. (CR91 bit1) A one enables the corresponding interrupt status bit for PME# interrupt. (CR91 bit0) 7.4.3.22 FAN Interrupt Status Register Index 91h Bit 7-3 Name Reserved R/W Default RO 0 2 FAN3_STS R/W -- 1 FAN2_STS R/W -- 0 FAN1_STS R/W -- Description Reserved This bit is set when the fan3 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. This bit is set when the fan2 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. This bit is set when the fan1 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. 7.4.3.23 FAN Real Time Status Register Index 92h Bit Name 7-3 Reserved R/W Default -- Description 0 2 FAN3_EXC RO -- 1 FAN2_EXC RO -- 0 FAN1_EXC RO -- Reserved This bit set to high mean that fan3 count can’t meet expect count over than SMI time(CR9F) or when duty not zero but fan stop over then 3 sec. This bit set to high mean that fan2 count can’t meet expect count over than SMI time(CR9F) or when duty not zero but fan stop over then 3 sec. This bit set to high mean that fan1 count can’t meet expect count over than SMI time(CR9F) or when duty not zero but fan stop over then 3 sec. 7.4.3.24 FAN FAULT# Enable Register Index 93h Bit Name R/W Default Description 0h Reserved FULL_WITH_T2_EN R/W 0 Set one will enable FAN to force full speed when T2 over high limit. 5 FULL_WITH_T1_EN R/W 0 Set one will enable FAN to force full speed when T1 over high limit. 4 FULL_WITH_T0_EN R/W 0 Set one will enable FAN to force full speed when T0 (Local Temperature) over high limit. 7 Reserved 6 RO 43 July, 2007 V.26P F71858 3 2 1 0 Reserved RO 0 Reserved EN_FAN3_ALERT R/W 0 EN_FAN2_ALERT R/W 0 EN_FAN1_ALERT R/W 0 When FAN3_EXC(CR92 bit2) is active and this bit is Enabled. The pin ALERT# will be active and user can select ALERT mode from (CR02). When FAN2_EXC(CR92 bit1) is active and this bit is Enabled. The pin ALERT# will be active and user can select ALERT mode from (CR02). When FAN1_EXC(CR92 bit0) is active and this bit is Enabled. The pin ALERT# will be active and user can select ALERT mode from (CR02). 7.4.3.25 Fan Type Select Register -- Index 94h Bit Name R/W Default 7-6 Reserved RO 0h 5-4 FAN3_TYPE R/W 1Sb 3-2 FAN2_TYPE R/W 1Sb 1-0 FAN1_TYPE R/W 1Sb Description Reserved for fan 4 00: Output PWM mode (push pull) to control fans. 01: Use DAC mode application circuit to control fan speed by fan’s power terminal. 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Use DAC mode application circuit to control fan speed by fan’s power terminal. Bit 0 default value is trapping by pin FAN3_CTRL. If pull up 10K the bit0 default value is 0, else if without pull up resister bit0 default value will be 1(for DAC mode) 00: Output PWM mode (push pull) to control fans. 01: Use DAC mode application circuit to control fan speed by fan’s power terminal . 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Use DAC mode application circuit to control fan speed by fan’s power terminal. Bit 0 default value is trapping by pin FAN3_CTRL. If pull up 10K the bit0 default value is 0, else if without pull up resister bit0 default value will be 1(for DAC mode) 00: Output PWM mode (push pull) to control fans. 01: Use DAC mode application circuit to control fan speed by fan’s power terminal . 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Use DAC mode application circuit to control fan speed by fan’s power terminal. Bit 0 default value is trapping by pin FAN3_CTRL. If pull up 10K the bit0 default value is 0, else if without pull up resister bit0 default value will be 1(for DAC mode) “S” mean default by trapping. 7.4.3.26 Fan mode Select Register -- Index 96h Bit Name 7-6 Reserved 5-4 FAN3_MODE R/W Default RO R/W Description 0h Reserved for fan 4 1h 00: Auto fan speed control, fan speed will follow different temperature by different RPM that define in 0xC6-0xCE. 01: Auto fan speed control, fan speed will follow different temperature by different duty cycle that define in 0xC6-0xCE. 10: Manual mode fan control, user can write expect RPM count to 0xC2-0xC3, and F71858 will auto control duty cycle (PWM fan type) or voltage (DAC mode type) to control fan speed. 11: Reserved 44 July, 2007 V.26P F71858 3-2 FAN2_MODE R/W 1h 1-0 FAN1_MODE R/W 1h 00: Auto fan speed control, fan speed will follow different temperature by different RPM that define in 0xB6-0xBE. 01: Auto fan speed control, fan speed will follow different temperature by different duty cycle (voltage) that define in 0xB6-0xBE. 10: Manual mode fan control, user can write expect RPM count to 0xB2-0xB3, and F71858 will auto control duty cycle (PWM fan type) or voltage (DAC mode type) to control fan speed. 11: Reserved 00: Auto fan speed control, fan speed will follow different temperature by different RPM that define in 0xA6-0xAE. 01: Auto fan speed control, fan speed will follow different temperature by different duty cycle that define in 0xA6-0xAE. 10: Manual mode fan control, user can write expect RPM count to 0xA2-0xA3, and F71858 will auto control duty cycle (PWM fan type) or voltage(DAC mode type) to control fan speed. 11: Reserved. 7.4.3.27 Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h Bit Name R/W Default 4h 7-4 FAN2_HYS R/W 3-0 FAN1_HYS R/W 4h Description 0000: Boundary hysteresis. (0~15 degree C) Segment will change when the temperature over the boundary temperature and below the (Boundary temperature– hysteresis ). 0000: Boundary hysteresis. (0~15 degree C) Segment will change when the temperature over the boundary temperature and below the (Boundary temperature – hysteresis ). 7.4.3.28 Auto Fan3 Boundary Hystersis Select Register -- Index 99h Bit Name 7-4 Reserved 3-0 FAN3_HYS R/W Default RO Description 0h Reserved for fan 4 2h 0000: Boundary hysteresis. (0~15 degree C) Segment will change when the temperature over the boundary temperature and below the (Boundary temperature– hysteresis ). R/W 7.4.3.29 Fan1~Fan3 Duty Change Rate Select Register -- Index 9Bh Bit Name 7-6 Reserved 5-4 FAN3_RATE_SEL R/W Default RO 0h Reserved for fan 4 1h Fan3 duty update rate: 00: 2.5Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz Fan2 duty update rate: 00: 2.5Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz Fan1 duty update rate: 00: 2.5Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz R/W 1h 3-2 FAN2_RATE_SEL R/W 1h 1-0 FAN1_RATE_SEL R/W Description 45 July, 2007 V.26P F71858 7.4.3.30 FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE Index 9Ch Bit Name R/W Default 5h 7-4 FAN2_MIN_DUTY R/W 5h 3-0 FAN1_MIN_DUTY R/W Description When fan start, the FAN_CTRL2 will increase duty-cycle from 0 to this (value x 8) directly. And if fan speed is down, the FAN_CTRL 2 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). When fan start, the FAN_CTRL 1 will increase duty-cycle from 0 to this (value x 8 directly. And if fan speed is down, the FAN_CTRL 1 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). 7.4.3.31 FAN3 START UP DUTY-CYCLE/VOLTAGE Index 9Dh Bit Name R/W Default 7-4 Reserved 3-0 RO FAN3_MIN_DUTY Description 0h Reserved 5h When fan start, the FAN_CTRL 3 will increase duty-cycle from 0 to this (value x 8 directly. And if fan speed is down, the FAN_CTRL 3 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). R/W 7.4.3.32 Fan Fault Time Register -- Index 9Fh Bit Name 7-4 Reserved 3-0 R/W Default -- F_FAULT_TIME R/W Description -- Reservd Ah This register determines the time of fan fault. The condition to cause fan fault event is: When PWM_Duty reaches FFh, if the fan speed count can’t reach the fan expect count in time. The unit of this register is 1 second. The default value is 11 seconds. (Set to 0 , means 1 seconds. ; Set to 1, means 2 seconds. Set to 2, means 3 seconds. …. ) Another condition to cause fan fault event is fan stop and the PWM duty is greater than the minimum duty programmed by the register index 97-98h. Fan1 Index A0h- AFh Address Attribute Default Value A0h RO 8’h0f A1h RO 8’hff A2h R/W 8’h00 A3h R/W 8’h01 Description FAN1 count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN1 count reading (LSB). RPM mode(CR96 bit0=0): FAN1 expect speed count value (MSB), in auto fan mode (CR96 bit1Î0) this register is auto updated by hardware. Duty mode(CR96 bit0=1): This byte is reserved byte. RPM mode(CR96 bit0=0): FAN1 expect speed count value (LSB) or expect PWM duty, in auto fan mode this register is auto updated by hardware and read only. Duty mode(CR96 bit0=1): The Value programming in this byte is duty value. In auto fan mode(CR96 46 July, 2007 V.26P F71858 A4h R/W 8’h03 A5h R/W 8’hff bit1Î0) this register is updated by hardware. Ex: 5Î 5*100/255 % 255 Î 100% FAN1 full speed count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN1 full speed count reading (LSB). 7.4.3.33 T1 BOUNDARY 1 TEMPERATURE – Index A6h Bit Name 7 Reserved 6-0 BOUND1TEMP1 R/W Default RO R/W 0 Description Return 0 when read. st 46h The 1 BOUNDARY temperature for T1 in temperature mode. (70oC) When T1 temperature is exceed this boundary, FAN1 expect value will load from segment 1 register (index AA)h. When T1 temperature is below this boundary – hysteresis, FAN1 expect value will load from segment 2 register (index ABh). 7.4.3.34 T1 BOUNDARY 2 TEMPERATURE – Index A7h Bit Name 7 Reserved 6-0 BOUND2TEMP1 R/W Default RO R/W 0 Description Return 0 when read. The 2st BOUNDARY temperature for T1 in temperature mode. 3C o (60 C) When T1 temperature is exceed this boundary, FAN1 expect value will load from segment 2 register (index AB)h. When T1 temperature is below this boundary – hysteresis, FAN1 expect value will load from segment 3 register (index ACh). 7.4.3.35 T1 BOUNDARY 3 TEMPERATURE – Index A8h Bit Name 7 Reserved 6-0 BOUND3TEMP1 R/W Default RO R/W 0 Description Return 0 when read. st 32h The 3 BOUNDARY temperature for T1 in temperature mode. (50oC) When T1 temperature is exceed this boundary, FAN1 expect value will load from segment 3 register (index AC)h. When T1 temperature is below this boundary – hysteresis, FAN1 expect value will load from segment 4 register (index ADh). 7.4.3.36 T1 BOUNDARY 4 TEMPERATURE – Index A9h Bit 7 6-0 Name Reserved BOUND4TEMP1 R/W Default RO R/W 0 Description Return 0 when read. st 28h The 4 BOUNDARY temperature for T1 in temperature mode. (40oC) When T1 temperature is exceed this boundary, FAN1 expect value will load from segment 4 register (index ADh). When T1 temperature is below this boundary – hysteresis, FAN1 expect value will load from segment 5 register (index AEh). 7.4.3.37 FAN1 SEGMENT 1 SPEED COUNT – Index AAh Bit Name R/W Default Description 47 July, 2007 V.26P F71858 FFh The meaning of this register is depending on the FAN1_MODE(CR96) (100%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. Ex: 7-0 SEC1SPEED1 R/W 32 Expectspeed= × Fullspeeed 32+ value 100%:full speed: User must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. X% full speed: The value programming in this byte is Î (100-X)*32/X 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7.4.3.38 FAN1 SEGMENT 2 SPEED COUNT Bit 7-0 Name SEC2SPEED1 R/W Default R/W Description D9h The meaning of this register is depending on the FAN1_MODE(CR96) (85%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7.4.3.39 FAN1 SEGMENT 3 SPEED COUNT Bit 7-0 Name SEC3SPEED1 7-0 Name SEC4SPEED1 R/W Description A6h The meaning of this register is depending on the FAN1_MODE(CR96) (65%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7-0 Name SEC5SPEED1 R/W Description 80h The meaning of this register is depending on the FAN1_MODE(CR96) (50%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7 6 Name R/W Description 66h The meaning of this register is depending on the FAN1_MODE(CR96) (40%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. – Index AFh R/W Default FAN1_LD_BEFORE_EN R/W FAN1_NO_STOP – Index AEh R/W Default 7.4.3.42 FAN1 Temperature Mapping Select Bit – Index ADh R/W Default 7.4.3.41 FAN1 SEGMENT 5 SPEED COUNT Bit – Index ACh R/W Default 7.4.3.40 FAN1 SEGMENT 4 SPEED COUNT Bit – Index ABh R/W 0 0 Description Set 1 that fan speed will keep current temp. status before system re-boot up. Set 1 that FAN1 will not stop but keep at FAN1_MIN_DUTY x 4. 48 July, 2007 V.26P F71858 5 FAN1_UP_T_EN 4 R/W FAN1_INTERPOLATION_EN R/W 0 0 1 3 FAN1_JUMP_HIGH_EN R/W 1 2 FAN1_JUMP_LOW_EN R/W 1-0 FAN1_TEMP_SEL R/W 1 Set 1 to force FAN1 to the highest speed if any temperature over its high limit. Set 1 will enable the interpolation of the fan expect table. (Auto Linear Mode) Set 1 that FAN1 speed will jump to FAN1 SEGMENT 1 SPEED when temperature over T1 Boundary 1. Set 0 that FAN1 speed will raise up to FAN1 SEGMENT 1 SPEED by slop value( CR9B) when temperature over T1 Boundary 1. Set 1 that FAN1 speed will jump to FAN1 SEGMENT 2 SPEED when temperature under FAN1 Boundary Hystersis. Set 0 that FAN1 speed will decrease to FAN1 SEGMENT 2 SPEED by slop value( CR9B) when temperature under FAN1 Boundary Hystersis. 0: fan1 follows local temperature 0. 1: fan1 follows temperature 1. 2: fan1 follows temperature 2. 3: fan1 doesn’t follow and temperature, that means the auto mode function will be disabled. Fan2 Index B0h- BFh Address Attribute Default Value B0h RO 8’h0f B1h RO 8’hff B2h R/W 8’h00 B3h R/W 8’h01 B4h R/W 8’h03 B5h R/W 8’hff Description FAN2 count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN2 count reading (LSB). RPM mode(CR96 bit2=0): FAN2 expect speed count value (MSB), in auto fan mode(CR96 bit3Î0) this register is auto updated by hardware. Duty mode(CR96 bit2=1): This byte is reserved byte. RPM mode(CR96 bit2=0): FAN2 expect speed count value (LSB) or expect PWM duty , in auto fan mode this register is auto updated by hardware and read only. Duty mode(CR96 bit2=1): The Value programming in this byte is duty value. In auto fan mode(CR96 bit3Î0) this register is updated by hardware. Ex: 5Î 5*100/255 % 255 Î 100% FAN2 full speed count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN2 full speed count reading (LSB). 7.4.3.43 T2 BOUNDARY 1 TEMPERATURE – Index B6h Bit 7 6-0 Name Reserved BOUND1TEMP2 R/W Default RO R/W 0 Description Return 0 when read. st 46h The 1 BOUNDARY temperature for T2 in temperature mode. (70oC) When T2 temperature is exceed this boundary, FAN2 expect value will load from segment 1 register (index BA)h. When T2 temperature is below this boundary – hysteresis, FAN2 expect value will load from segment 2 register (index BAh). 49 July, 2007 V.26P F71858 7.4.3.44 T2 BOUNDARY 2 TEMPERATURE – Index B7h Bit Name 7 Reserved 6-0 BOUND2TEMP2 R/W Default RO R/W 0 Description Return 0 when read. The 2st BOUNDARY temperature for T2 in temperature mode. 3C (60oC) When T2 temperature is exceed this boundary, FAN2 expect value will load from segment 2 register (index BB)h. When T2 temperature is below this boundary – hysteresis, FAN2 expect value will load from segment 3 register (index BBh). 7.4.3.45 T2 BOUNDARY 3 TEMPERATURE – Index B8h Bit 7 6-0 Name Reserved BOUND3TEMP2 R/W Default RO R/W 0 Description Return 0 when read. st 32h The 3 BOUNDARY temperature for T2 in temperature mode. (50oC) When T2 temperature is exceed this boundary, FAN2 expect value will load from segment 3 register (index BC)h. When T2 temperature is below this boundary – hysteresis, FAN2 expect value will load from segment 4 register (index BCh). 7.4.3.46 T2 BOUNDARY 4 TEMPERATURE – Index B9h Bit Name 7 Reserved 6-0 BOUND4TEMP2 R/W Default RO R/W 0 Description Return 0 when read. st 28h The 4 BOUNDARY temperature for T2 in temperature mode. (40oC) When T2 temperature is exceed this boundary, FAN2 expect value will load from segment 4 register (index BDh). When T2 temperature is below this boundary – hysteresis, FAN2 expect value will load from segment 5 register (index BDh). 7.4.3.47 FAN2 SEGMENT 1 SPEED COUNT Bit Name – Index BAh R/W Default Description FFh The meaning of this register is depending on the FAN_MODE(CR96) (100%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 7-0 SEC1SPEED2 32 Expect speed = × Full speeed 32 + value R/W 100%:full speed: User must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. X% full speed: The value programming in this byte is Î (100-X)*32/X 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7.4.3.48 FAN2 SEGMENT 2 SPEED COUNT – Index BBh Bit 7-0 Name SEC2SPEED2 R/W Default R/W Description D9h The meaning of this register is depending on the FAN_MODE(CR96) (85%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 50 July, 2007 V.26P F71858 7.4.3.49 FAN2 SEGMENT 3 SPEED COUNT Bit 7-0 Name SEC3SPEED2 R/W Default R/W Description A6h The meaning of this register is depending on the FAN_MODE(CR96) (65%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7.4.3.50 FAN2 SEGMENT 4 SPEED COUNT Bit 7-0 Name SEC4SPEED2 7-0 Name SEC5SPEED2 R/W Description 80h The meaning of this register is depending on the FAN_MODE(CR96) (50%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7 Name R/W Description 66h The meaning of this register is depending on the FAN_MODE(CR96) (40%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. FAN2_LD_BEFORE_EN R/W 0 FAN2_NO_STOP R/W 0 5 FAN2_UP_T_EN R/W 0 FAN2_INTERPOLATION_EN R/W 0 1 3 – Index BFh R/W Default 6 4 – Index BEh R/W Default 7.4.3.52 FAN2 Temperature Mapping Select Bit – Index BDh R/W Default 7.4.3.51 FAN2 SEGMENT 5 SPEED COUNT Bit – Index BCh FAN2_JUMP_HIGH_EN R/W 1 2 FAN2_JUMP_LOW_EN R/W 1-0 FAN2_TEMP_SEL R/W 2 Description Set 1 that fan speed will keep current temp. status before system re-boot up. Set 1 that FAN2 will not stop but keep at FAN2_MIN_DUTY x 4. Set 1 to force FAN2 to the highest speed if any temperature over its high limit. Set 1 will enable the interpolation of the fan expect table. (Auto Linear Mode) Set 1 that FAN2 speed will jump to Fan2 SEGMENT 1 SPEED when temperature over T2 Boundary 1. Set 0 that FAN2 speed will raise up to Fan2 SEGMENT 1 SPEED by slop value( CR9B) when temperature over T2 Boundary 1. Set 1 that FAN2 speed will jump to Fan2 SEGMENT 2 SPEED when temperature under FAN2 Boundary Hystersis. Set 0 that FAN2 speed will decrease to Fan2 SEGMENT 2 SPEED by slop value( CR9B) when temperature under FAN2 Boundary Hystersis. 0: fan2 follows local temperature 0. 1: fan2 follows temperature 1. 2: fan2 follows temperature 2. 3: fan2 doesn’t follow and temperature, that means the auto mode function will be disabled. Fan3 Index C0h- CFh 51 July, 2007 V.26P F71858 Address Attribute Default Value C0h RO 8’h0F C1h RO 8’hff C2h R/W 8’h00 C3h R/W 8’h01 C4h R/W 8’h03 C5h R/W 8’hff Description FAN3 count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN3 count reading (LSB). RPM mode(CR96 bit4=0): FAN3 expect speed count value (MSB), in auto fan mode(CR96 bit5Î0) this register is auto updated by hardware. Duty mode(CR96 bit4=1): This byte is reserved byte. RPM mode(CR96 bit4=0): FAN3 expect speed count value (LSB) or expect PWM duty , in auto fan mode this register is auto updated by hardware and read only. Duty mode(CR96 bit4=1): The Value programming in this byte is duty value. In auto fan mode(CR96 bit5Î0) this register is updated by hardware. Ex: 5Î 5*100/255 % 255 Î 100% FAN3 full speed count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN3 full speed count reading (LSB). 7.4.3.53 T0 BOUNDARY 1 TEMPERATURE – Index C6h Bit Name 7 Reserved 6-0 BOUND1TEMP3 R/W Default RO R/W 0 Description Return 0 when read. st 46h The 1 BOUNDARY temperature for T0 in temperature mode. (70oC) When T0 temperature is exceed this boundary, FAN3 expect value will load from segment 1 register (index CA)h. When T0 temperature is below this boundary – hysteresis, FAN3 expect value will load from segment 2 register (index CAh). 7.4.3.54 T0 BOUNDARY 2 TEMPERATURE – Index C7h Bit Name 7 Reserved 6-0 BOUND2TEMP3 R/W Default RO R/W 0 Description Return 0 when read. The 2st BOUNDARY temperature for T0 in temperature mode. 3C o (60 C) When T0 temperature is exceed this boundary, FAN3 expect value will load from segment 2 register (index CB)h. When T0 temperature is below this boundary – hysteresis, FAN3 expect value will load from segment 3 register (index CBh). 7.4.3.55 T0 BOUNDARY 3 TEMPERATURE – Index C8h Bit 7 6-0 Name Reserved BOUND3TEMP3 R/W Default RO R/W 0 Description Return 0 when read. st 32h The 3 BOUNDARY temperature for T0 in temperature mode. (50oC) When T0 temperature is exceed this boundary, FAN3 expect value will load from segment 3 register (index CC)h. When T0 temperature is below this boundary – hysteresis, FAN3 expect value will load from segment 4 register (index CCh). 52 July, 2007 V.26P F71858 7.4.3.56 T0 BOUNDARY 4 TEMPERATURE – Index C9h Bit Name 7 Reserved 6-0 BOUND4TEMP3 R/W Default RO R/W 0 Description Return 0 when read. st 28h The 4 BOUNDARY temperature for T0 in temperature mode. (40oC) When T0 temperature is exceed this boundary, FAN3 expect value will load from segment 4 register (index CDh). When T0 temperature is below this boundary – hysteresis, FAN3 expect value will load from segment 5 register (index CDh). 7.4.3.57 FAN3 SEGMENT 1 SPEED COUNT Bit Name – Index CAh R/W Default Description FFh The meaning of this register is depending on the FAN_MODE(CR96) (100%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 7-0 SEC1SPEED3 32 Expect speed = × Full speeed 32 + value R/W 100%:full speed: User must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. X% full speed: The value programming in this byte is Î (100-X)*32/X 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7.4.3.58 FAN3 SEGMENT 2 SPEED COUNT – Index CBh Bit 7-0 Name SEC2SPEED3 R/W Default R/W 7.4.3.59 FAN3 SEGMENT 3 SPEED COUNT Bit 7-0 Name SEC3SPEED3 7-0 Name SEC4SPEED3 – Index CCh R/W Default R/W Description A6h The meaning of this register is depending on the FAN_MODE(CR96) (65%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7.4.3.60 FAN3 SEGMENT 4 SPEED COUNT Bit Description D9h The meaning of this register is depending on the FAN_MODE(CR96) (85%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. – Index CDh R/W Default R/W Description 80h The meaning of this register is depending on the FAN_MODE(CR96) (50%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 53 July, 2007 V.26P F71858 7.4.3.61 FAN3 SEGMENT 5 SPEED COUNT Bit Name 7-0 SEC5SPEED3 R/W Default R/W Description 66h The meaning of this register is depending on the FAN_MODE(CR96) (40%) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7.4.3.62 FAN3 Temperature Mapping Select Bit 7 Name 0 6 FAN3_NO_STOP R/W 0 5 FAN3_UP_T_EN R/W 0 FAN3_INTERPOLATION_EN R/W 0 1 3 – Index CFh R/W Default FAN3_LD_BEFORE_EN R/W 4 – Index CEh FAN3_JUMP_HIGH_EN R/W 1 2 FAN3_JUMP_LOW_EN R/W 1-0 FAN3_TEMP_SEL R/W 0 Description Set 1 that fan speed will keep current temp. status before system re-boot up. Set 1 that FAN3 will not stop but keep at FAN3_MIN_DUTY x 4. Set 1 to force FAN3 to the highest speed if any temperature over its high limit. Set 1 will enable the interpolation of the fan expect table. (Auto Linear Mode) Set 1 that FAN3 speed will jump to Fan3 SEGMENT 1 SPEED when temperature over T0 Boundary 1. Set 0 that FAN3 speed will raise up to Fan3 SEGMENT 1 SPEED by slop value( CR9B) when temperature over T0 Boundary 1. Set 1 that FAN3 speed will jump to Fan3 SEGMENT 2 SPEED when temperature under FAN3 Boundary Hystersis. Set 0 that FAN3 speed will decrease to Fan3 SEGMENT 2 SPEED by slop value( CR9B) when temperature under FAN3 Boundary Hystersis. 0: fan3 follows local temperature 0. 1: fan3 follows temperature 1. 2: fan3 follows temperature 2. 3: fan3 doesn’t follow and temperature, that means the auto mode function will be disabled. Fan4 Index D0h- D1h Address Attribute Default Value D0h RO 8’h0F D1h RO 8’hff Description FAN4 count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN4 count reading (LSB). 格式 8. PCB Layout Guide F71858 adopts Current Mode measure method to do temperature detected. The measure data will not be affected by different process of CPU due to use current mode technology. This 54 July, 2007 V.26P F71858 technology measures mini-voltage from the remote sensor so a good PCB layout must be cared about noise minimizing. The noises often come from circuit trace which is a track from remote sensor (CPU side) to detect circuit input (F71858 side). The signal on this track will be inducted mini-noises when it passes through a high electromagnetic area. Those effects will result in the mini-noises and show in the detected side. It will be reported a wrong data which you want to measure. Please pay attention and follow up the check list below in order to get an actual and real temperature inside the chip. 1. The D1+/D2+ and AGND (D-) tracks Must Not pass through/by PWM POWER-MOS. Keep as far as possible from POWER MOS. 2. Place a 0.1µF bypass capacitor close to the VCC pin. Place an external 2200pF input filter capacitors across D+, D- and close to the F71858. Near the pin AGND (D-) Must Be placed a through hole into the GND Plane before connect to the external 2200pF capacitor. VCC 99 0.1uF F71858 F71872F D1+ 89 AGND(D-) THERMDA THERMDC From thermal diode 2200pF 86 3. Place the F71858 as close as practical to the remote sensor diode. In noisy environments, such as a computer main-board, the distance can be 4 to 8 inches. (typ). This length can be increased if the worst noise sources are avoided. Noise sources generally include clock generators, CRTs, memory buses and PCI/ISA bus etc. 4. Separated route the D1+, D2+ with AGND (D-) tracks close together and in parallel after adding external 2200pF capacitor. For more reliable, it had better with grounded guard tracks on each side. Provide a ground plane under the tracks if possible. Do not route D+ & D- lines next to the deflection coil of the CRT. And also don’t route the trace across fast digital signals which can easily induce bigger error. GND 10MILS THERMDA(DXP) 10MILS THERMDC(DXN) 10MILS MINIMUM 10MILS GND 55 July, 2007 V.26P F71858 5. Use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended. 6. Try to minimize the number of component/solder joints, called through hole, which can cause thermocouple effects. Where through holes are used, make sure that they are in both the D+ and D- path and at the same temperature. Thermocouple effects should not be a major problem as 1℃ corresponds to about 200µV. It means that a copper-solder thermocouple exhibits 3µV/℃, and takes about 200µV of the voltage error at D+ & D- to cause a 1℃ measurement error. Adding a few thermocouples causes a negligible error. 7. If the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. It will work up to around 6 to 12 feet. Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance will affect the measurement accuracy. When using long cables, the filter capacitor should be reduced or removed. Cable resistance can also induce errors. For example: 1 Ω series resistance introduces about 0.5℃ error. 9. Electrical Characteristics 9.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage Input Voltage RATING UNIT -0.5 to 5.0 V -0.5 to VCC+0.5 V 56 July, 2007 V.26P F71858 Operating Temperature Storage Temperature 0 to +70 °C -55 to 150 °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device 9.2 DC Characteristics (Ta = 0° C to 70° C, VCC = 3.3V ± 10% , VSS = 0V ) PARAMETER RATING Operating Voltage 3.0 to 3.6 VCC/VSB Operating Voltage 2.4 to 3.6 VBAT 9.3 DC Characteristics Continued (Ta = 0° C to 70° C, VCC = 3.3V ± 10%, VSS = 0V) PARAMETER SYM. MIN TYP MAX. UNIT CONDITIONS I/O12t - TTL level bi-directional pin with 12 mA source-sink capability(3.3V) Input Low Voltage VIL -0.5 0.8 V Input High Voltage VIH 2.0 VCC+ V 0.3 Output Low Current IOL 12 mA 0.4V Output High Current IOH 12 mA 2.4V Input High Leakage ILIH -1 1 µA Input Low Leakage ILIL -1 1 µA I/OD16t-5V - TTL level bi-directional pin with 16 mA source-sink capability(3.3V), 5 tolerance Input Low Voltage VIL -0.5 0.8 V Input High Voltage VIH 2.0 VCC+ V 0.3 Output Low Current IOL 12 mA 0.4V Input High Leakage ILIH -1 1 µA Input Low Leakage ILIL -1 1 µA OD12 – Open-drain output pin with12mA source-sink capability(3.3V) Output Low Current 12 Ma 0.4V OD12_5v – Open-drain output pin with12mA source-sink capability(3.3V), 5 tolerance Output Low Current 12 Ma 0.4V OD16-u10,5V – Open-drain output pin with12mA source-sink capability(3.3V), 5 tolerance, 10k pull high Output Low Current 12 Ma 0.4V INts – TTL level input pin and schmitt trigger Input Low Threshold Voltage 0.8 V Input Hign Threshold Voltage 2.0 V Hysteresis 0.5 V Input High Leakage +1 µA Input Low Leakage -1 µA INts_5v – TTL level input pin and schmitt trigger, 5 tolerance Input Low Threshold Voltage 0.8 V Input Hign Threshold Voltage 2.0 V Hysteresis 0.5 V Input High Leakage +1 µA 57 July, 2007 V.26P F71858 Input Low Leakage 9.4 µA -1 AC Characteristics 9.4.1 PS/2 Interface NO. DESCRIPTION MIN. MAX. UNIT T1 Duration of start of receive 5 25 µS T2 Data valid after falling edge of PS2CLK 5 T8 - 5 µS T3 PS2DAT setup time to falling edge of PS2CLK 1 T4 PS2DAT hold time from falling edge of PS2CLK 5 T5 Duration of inhibit PS/2 device >0 T6 Duration of Data Frame 2 mS T7 Duration of PS2CLK inactive 30 50 µS T8 Duration of PS2CLK active 30 50 µS T9 Duration of PS/2 device inhibit 100 300 µS T10 Duration of start of transmit 15 mS T11 Data valid after falling edge of PS2CLK 4 µS T12 PS2DAT setup time to rising edge of PS2CLK 1 T13 PS2DAT hold time from rising edge of PS2CLK 5 µS 95 µS µS µS 95 µS PS/2 interface timing table Data Received from PS/2 Device T6 PS2CLK 1 T1 PS2DAT 2 3 5 6 7 8 9 10 T2 B0 B1 11 T5 T3 T7 T8 START Bit 4 T4 B2 B3 B4 B5 B6 B7 P STOP Bit Host received from PS/2 interface timing diagram Data Sent to PS/2 Device 58 July, 2007 V.26P F71858 T6 T10 PS2CLK 1 2 3 4 T9 T11 START Bit PS2DAT 5 6 7 8 9 11 10 T12 T7 T8 B0 B1 B2 T13 B3 B5 B4 B6 B7 P STOP Bit ACK Host Send to PS/2 device timing diagram 9.4.2 LPC Interface NO. DESCRIPTION MIN. MAX. UNIT T1 LFRAME# drive low after rising edge of PCICLK 2 12 nS T2 LFRAME# drive high after rising edge of PCICLK 2 12 nS T3 LDA[3:0] floating after rising edge of PCICLK 28 nS T4 LDA[3:0] setup time to rising edge of PCICLK 7 nS T5 LDA[3:0] hold time from rising edge of PCICLK 0 nS T6 Period of PCICLK 27 T7 Duration of PCICLK low 12 nS T8 Duration of PCICLK high 12 nS 33 nS LPC interface timing table Typical Timing for Host Read PCICLK T1 T2 T4 LFRAME# LAD[3:0] T3 Start DIR ADDR ADDR ADDR ADDR HTAR T5 HZ 4 or 8 Clocks 0110 Sync 0-i Clocks 1-j Clocks Data Data PTAR HZ 2 - 2k Clocks Host read timing diagram Typical Timing for Host Write 59 July, 2007 V.26P F71858 PCICLK T6 T8 T7 LFRAME# LAD[3:0] Start DIR ADDR ADDR ADDR ADDR Data Data HTAR HZ Sync PTAR HZ Host write timing diagram Timing for Aboart Mechanism PCICLK LFRAME# LAD[3:0] Start DIR ADDR ADDR ADDR ADDR HTAR HZ 4 or 8 Clocks 0110 Sync Sync 0-i Clocks Too many Syncs causes timeout Peripheral must stop driving Host will drive high Host abort timing diagram 9.4.3 Serialized IRQ Interface NO. MIN. MAX. UNIT T1 Host drive SERIRQ low after rising edge of PCICLK DESCRIPTION 2 12 nS T2 Host drive SERIRQ high after rising edge of PCICLK 2 12 nS T3 Slave drive SERIRQ low after rising edge of PCICLK 2 12 nS T4 Slave drive SERIRQ high after rising edge of PCICLK 2 12 nS T5 Period of PCICLK 27 33 nS T6 Duration of PCICLK low 12 nS T7 Duration of PCICLK high 12 nS SIRQ interface timing table Start Frame Timing 60 July, 2007 V.26P F71858 Start Frame SL or H IRQ0 Frame H R S T R IRQ1 Frame S T R IRQ2 Frame S T R T PCICLK T1 T3 T2 SERIRQ T4 Start 4 - 8 Clocks Drive Source Host Controller IRQ1 H : Host Control IRQ1 None SL : Slave Control R : Recovery None T : Turn-around S : Sample SIRQ start frame timing diagram Stop Frame Timing IRQ14 Frame S R IRQ15 Frame T S R IOCHCK# Frame T S R T Next Cycle Stop Frame H I R T PCICLK T5 T6 T7 T1 T2 SERIRQ Drive Source Stop 0-n Clocks None H : Host Control SL : Slave Control Host Controller None IRQ15 R : Recovery 2 or 3 Clocks T : Turn-around S : Sample I : Idle SIRQ stop frame timing diagram 61 July, 2007 V.26P F71858 10.Ordering Information Part Number Package Type Production Flow F71858DG 48-LQFP (Green Package) Commercial, 0°C to +70°C 11.Package Dimensions (48LQFP) HD D 25 36 Dimension in inch Symbol E 48 HE 13 1 e b Nom. A A1 A2 b c D E e HD HE L L1 y 24 37 Min. 12 0 Max. Dimension in mm Min. Nom. Max. --- --- 1.60 0.05 --- 0.15 1.35 1.40 1.45 0.17 0.20 0.27 0.09 --- 0.20 7.00 7.00 0.50 9.00 9.00 0.45 0.60 0.75 1.00 --- 0.08 --- 0 3.5 7 Notes: c A2 Seating Plane See Detail F A A1 y L L1 Detail F 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. Feature Integration Technology Inc. Headquarters Taipei Office 3F-7, No 36, Tai Yuan St., Bldg. K4, 7F, No.700, Chung Cheng Rd., Chupei City, Hsinchu, Taiwan 302, R.O.C. Chungho City, Taipei, Taiwan 235, R.O.C. TEL : 886-3-5600168 TEL : 866-2-8227-8027 FAX : 886-3-5600166 FAX : 866-2-8227-8037 Please note that all datasheet and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this datasheet belong to their respective owner 62 July, 2007 V.26P F71858 12.Application Circuit VSB3V DEVICERST# PLED SLED S3GATE PS_ON# S3# S4# KCLK KDATA MCLK 0.1u MDATA VCC3V D2+ D1+ GND(D-) HW_IRQ# F71858D KBRST# GA20 FANIN4/SST/AMDSI_CLK FANIN3 FANIN2 FANIN1 FAN_CTL3/HPWM_DC PS_ON# PS_IN# RSTIN# IDERST# VCC3V C1 0.1u OVT# KBRST# GA20 RP1 2 4 6 8 VCC3V 1 3 5 7 RP2 VSB5V 2 4 6 8 VCC5V 4.7K D2+ D1+ GND(D-) OVT# KBRST# GA20 SST/AMDSI_CLK FANIN3 FANIN2 FANIN1 FANCTL3 PWOK OVT# 1 3 5 7 RP3 VCC3V 2 4 6 8 4.7K VSB5V VCC5V R2 330 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 1 3 5 7 4.7K 36 35 34 33 32 31 30 29 28 27 26 25 PME# PS_OUT# PS_IN# VSB3V KCLK KDATA MCLK MDATA GND PWOK RSMRST# VBAT LRESET# LFRAM# LAD0 LAD1 LAD2 LAD3 PCICLK SERIRQ VCC PECI/AMDSI_DAT FANCTL1 FANCTL2 PWOK RSMRAT# 37 38 39 40 41 42 43 44 45 46 47 48 S4# S3# PS_ON# S3GATE LED2 LED1 PCIRST5# PCIRST4# PCIRST3# PCIRST2# PCIRST1# RSTIN# PME# PS_OUT# PS_IN# C2 PWOK RSMRST# VBAT DEVICERST# PCIRST3# PCIRST2# PCIRST1# IDERST# RSTIN# IDERST# RSTIN# U7 PME# PS_OUT# VSB3V PS_IN# PS_OUT# PME# RSMRST# DEVICERST# R3 330 DIODE LRESET# LFRAM# LAD0 LAD1 LAD2 LAD3 PCICLK SERIRQ DIODE D1 FANCTL2 FANCTL1 D2 PECI/AMDSI_DAT SLED PLED VCC3V Title Size A Date: 63 F71858DG Document Number F71858DG Tuesday , December 19, 2006 Rev 0.21 Sheet 1 of 3 July, 2007 V.26P F71858 D1+ D+ D1+ C3 3300P GND(D-) D2+ from CPU DSST/AMDSI_CLK D2+ C4 Q1 PNP 3906 3300P SST for SYSTEM GND(D-) HOST DIODE SENSING CIRCUIT SST 1.8V 300 SST/AMDSI_CLK 300 PECI/AMDSI_DAT SI_CLK PECI 100k PECI/AMDSI_DAT SI_DAT Client AMD PECI AMDSI Title Size A Date: 64 Temperature Document Number F71858DG Tuesday , December 19, 2006 Rev 0.21 Sheet 2 of 3 July, 2007 V.26P F71858 +12V R14 4.7K R15 4.7K 12V VCC5V R20 R16 4.7K 2 FANCTL1 4 3 2 1 R19 27K + R26 U2A Q3 1 - 0 D4 1N4148 R12 4.7K LM358 FANIN1 JP2 R21 10K R17 10K C9 0.1U JP12 R26 3 4 HEADER Q3 + MOSFET N 2N7002 47U 330 8 D4 1N4148 4 C7 FANCTL1 NDS0605/SOT Q2 PNP R17 4.7K C12 47u FANIN1 C14 0.1u R18 10K CON3 R19 3.9K 0 R16 27K 3 2 1 DC FAN Control with OP 1 (4 PIN FAN Control) PWM FAN 1 SPEED CONTROL 12V +12V 4.7K R28 4.7K 8 R27 VCC5V Q5 PNP 5 D6 1N4148 R31 4.7K 6 FANCTL2 NDS0605/SOT U2B Q5 D6 1N4148 7 - R25 4.7K LM358 R34 330 JP15 Q6 + MOSFET N 2N7002 47U R32 3 2 1 27K FANIN2 R30 10K R35 10K C14 0.1U HEADER 3 PWM FAN 2 JP4 4 C11 FANCTL2 R29 4.7K + C16 47u C17 CON3 R32 3.9K SPEED CONTROL R27 27K 3 2 1 FANIN2 0.1u R31 10K DC FAN Control with OP 2 12V R40 4.7K VCC5V Q8 PNP D8 1N4148 R42 4.7K FANCTL3 R45 330 C15 Q9 + MOSFET N 2N7002 47U JP17 3 2 1 3 R41 4.7K R44 2 FANCTL3 FANIN3 NDS0605/SOT Q8 D8 1N4148 1 - R36 4.7K JP6 R41 10K C18 0.1U R43 3.9K PWM FAN 3 U3A LM358 27K R47 10K HEADER 3 + 4 4.7K 8 +12V R39 SPEED CONTROL C20 47u R39 27K 3 2 1 FANIN3 C21 0.1u R42 10K CON3 DC FAN Control with OP 3 FAN CONTROL FOR PWM OR DC Title Size B Date: 65 FAN circuit Document Number F71858DG Tuesday , December 19, 2006 Rev 0.21 Sheet 3 of 3 July, 2007 V.26P F71858 VSB5V J1 1 2 3 F1 CON3 VCC5V R5 4.7K R6 4.7K F2 M-DIN_6-R JS1 FUSE 1 2 3 6 5 4 R7 4.7K R8 4.7K L1 MDAT 1 2 3 6 5 4 L2 KDAT FB FB L3 MCLK M-DIN_6-R JS2 FUSE L4 KCLK FB FB C5 C6 C7 C8 C9 C10 100P 100P 0.1U 100P 100P 0.1U PS2 MOUSE INTERFACE PS2 KEYBOARD INTERFACE Title Size A Date: 66 KBC Document Number F71858DG Tuesday , December 19, 2006 Rev 0.21 Sheet 1 of 1 July, 2007 V.26P