FINTEK F81218

F81218
F81218D/DG
ISA/LPC to 6 UART Datasheet
Release Date: August, 2007
Version: V0.33P
F81218
August, 2007
V0.33P
F81218
F81218 Datasheet Revision History
Version
Date
Page
Revision History
0.24P
2003/7/10
25
Revised index 25h to index 26h
0.25P
2003/07/31
17
Updated WDT enable timer as power-on setting
24MHz clock input : 10 sec
48MHz clock input : 5 sec
0.26P
2003/09/16
0.27P
2004/01/07
56
Revised the pin naming, between Pin91 to Pin96
0.28P
2005/04/15
52
Added “Green Package” ordering information
28
Added Full Duplex Function for IR self test
30
(Bit 2 of IR control register index F1h)
0.29P
2006/03/24
Updated application circuit
-
Modified UART Clock Select Register (F0h) bit 1:0
description. Reserved 01/10/11 clock selection.
-
Added flow control registers of UART1~ UART6 register
F0h bit 4.
-
Added AC timing characteristics description.
0.30P
2006/04/03
-
Modified RS485 register description
0.31P
2006/05/30
-
Added note description of AC Timing characteristics.
0.32P
2007/7/5
-
Company readdress
0.33P
2007/8/20
9
Modify typo of pin type (Pin 85,86,87,88,89)
Please note that all data and specifications are subject to change without notice. All the trade marks of products and
companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for use
in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such
improper use or sales.
F81218
August, 2007
V0.33P
F81218
Table of Content
1. General Description ......................................................................................................................................... 1
2. Feature List ...................................................................................................................................................... 1
3. Pin Configuration............................................................................................................................................. 2
4. Pin Description................................................................................................................................................. 3
4.1 ISA/LPC Interface ................................................................................................................................. 3
4.2 UART Interface...................................................................................................................................... 5
4.3 GPIO pins............................................................................................................................................. 10
4.4 Power ................................................................................................................................................... 10
5. Functional Description................................................................................................................................... 11
5.1 LPC Interface .................................................................................................................................... 11
5.2 UART................................................................................................................................................ 11
5.3 IR Function ....................................................................................................................................... 16
5.4 Watch Dog Timer Function............................................................................................................... 17
5.5 Serial IRQ ......................................................................................................................................... 18
6. Register Description................................................................................................................................... 20
6.1 Global Control Register .................................................................................................................... 23
6.1.1 Software Reset Register – index 02h ........................................................................................ 23
6.1.2 Logic Device Select Register – index 07h................................................................................ 24
6.1.3 Device ID Register– index 20h, 21h......................................................................................... 24
6.1.4 Vendor ID Register– index 23h, 24h......................................................................................... 24
6.1.5 Clock Source Select Register – index 25h................................................................................ 24
6.1.6 GPIO Function Select Register ( ISA Interface Only ) – index 26h......................................... 25
6.1.7 Test Mode Register – index 2Fh ............................................................................................... 25
6.2 UART 1 Device Control Register (LDN 0) ......................................................................................... 26
6.2.1
Device Enable Register – index 30h.................................................................................. 26
6.2.2
I/O Port Select Register – index 60h.................................................................................. 26
6.2.3
I/O Port Select Register – index 61h.................................................................................. 26
6.2.4 IRQ Channel Select Register – index 70h ............................................................................. 26
6.2.5 UART 1 Clock Select Register – index F0h .......................................................................... 27
6.2.6 IR1 Control Register – index F1h.......................................................................................... 28
6.3 UART 2 Device Control Register (LDN 1) ......................................................................................... 28
6.3.1
Device Enable Register – index 30h.................................................................................. 28
6.3.2
I/O Port Select Register – index 60h.................................................................................. 28
6.3.3
I/O Port Select Register – index 61h.................................................................................. 29
6.3.4 IRQ Channel Select Register – index 70h ............................................................................. 29
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6.3.5 UART 2 Clock Select Register – index F0h .......................................................................... 30
6.3.6 IR 2 Control Register – index F1h......................................................................................... 30
6.4 UART 3 Device Control Register (LDN 2) ......................................................................................... 31
6.4.1
Device Enable Register – index 30h.................................................................................. 31
6.4.2
I/O Port Select Register – index 60h.................................................................................. 31
6.4.3
I/O Port Select Register – index 61h.................................................................................. 31
6.4.4 IRQ Channel Select Register – index 70h ............................................................................. 31
6.4.5 UART 3 Clock Select Register – index F0h .......................................................................... 32
6.5 UART 4 Device Control Register (LDN 3) ......................................................................................... 32
6.5.1
Device Enable Register – index 30h.................................................................................. 32
6.5.2
I/O Port Select Register – index 60h.................................................................................. 33
6.5.3
I/O Port Select Register – index 61h.................................................................................. 33
6.5.4 IRQ Channel Select Register – index 70h ............................................................................. 33
6.5.5 UART 4 Clock Select Register – index F0h .......................................................................... 34
6.6 UART 5 Device Control Register (LDN 4) ......................................................................................... 34
6.6.1
Device Enable Register – index 30h.................................................................................. 34
6.6.2
I/O Port Select Register – index 60h.................................................................................. 34
6.6.3
I/O Port Select Register – index 61h.................................................................................. 35
6.6.5 IRQ Channel Select Register – index 70h ............................................................................. 35
6.6.6 UART 5 Clock Select Register – index F0h .......................................................................... 36
6.7 UART 6 Device Control Register (LDN 5) ......................................................................................... 36
6.7.1
Device Enable Register – index 30h.................................................................................. 36
6.7.2
I/O Port Select Register – index 60h.................................................................................. 36
6.7.3
I/O Port Select Register – index 61h.................................................................................. 36
6.7.4 IRQ Channel Select Register – index 70h ............................................................................. 37
6.7.5 UART 6 Clock Select Register – index F0h .......................................................................... 37
6.8 Address Decoder 0 Device Control Register (LDN 6) ........................................................................ 38
6.8.1
Device Enable Register – index 30h.................................................................................. 38
6.8.2
Address Decoder Select Register 0– index 60h................................................................. 38
6.8.3
Address Decoder Select Register 1– index 61h................................................................. 38
6.8.4
Address Mask Register – index 62h .................................................................................. 38
6.8.5
IRQIN0 Channel Select Register (Only for LPC) – index 70h ......................................... 39
6.9 Address Decoder 1 Device Control Register (LDN 7) ........................................................................ 39
6.9.1
Device Enable Register – index 30h.................................................................................. 39
6.9.2
Address Decoder Select Register 0 – index 60h................................................................ 39
6.9.3
Address Decoder Select Register 1 – index 61h................................................................ 40
6.9.4
Address Mask Register – index 62h .................................................................................. 40
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6.9.5
IRQIN1 Channel Select Register (Only for LPC) – index 70h ......................................... 40
6.10 Watch Dog Timer Device Control Register (LDN 8) ........................................................................ 41
6.10.1
Device Enable Register – index 30h.................................................................................. 41
6.10.2
I/O Port Select Register – index 60h.................................................................................. 41
6.10.3
I/O Port Select Register – index 61h.................................................................................. 41
6.10.4 IRQ Channel Select Register – index 70h ......................................................................... 41
6.10.5
Timer Status and Control Register – index F0h................................................................. 42
6.10.6
Timer Count Number Register – index F1h....................................................................... 43
6.11 GPIO and PME Device Control Register (LDN 9)............................................................................ 43
6.11.1
GPIO Port 2 Control Register – index F0h........................................................................ 43
6.11.2
GPIO Port 1 Control Register – index F1h........................................................................ 43
6.11.3
GPIO Port 2 Output Data Control Register – index F2h ................................................... 44
6.11.4
GPIO Port 1 Output Data Register – index F3h ................................................................ 45
6.11.5
PME Event 1 Control Register – index F4h ...................................................................... 45
6.11.6
PME Event 2 Control Register – index F5h ...................................................................... 46
6.11.7
PME Event 3 Control Register – index F6h ...................................................................... 47
6.11.8
GPIO Port 2 Input Status Register – index F7h ................................................................. 47
6.11.9
GPIO Port 1 Input Status Register – index F8h ................................................................. 48
6.11.10 PME Real Time Status Register – index F9h..................................................................... 48
6.11.11 PME Edge Status 1 Register – index FAh ......................................................................... 48
6.11.12 PME Edge Status 2 Register – index FBh ......................................................................... 49
6.11.13 PME Edge Status 3 Register – index FCh ......................................................................... 49
7. Electron Characteristic................................................................................................................................ 51
7.1 Absolute Maximum Ratings ............................................................................................................. 51
7.2 DC Characteristics ............................................................................................................................ 51
7.3 AC Timing Characteristics................................................................................................................ 53
8. Ordering Information .................................................................................................................................. 54
9. Package Dimensions ................................................................................................................................... 55
10. Application Circuit....................................................................................................................................... 54
F81218
August, 2007
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F81218
1. General Description
The F81218 mainly provides 4 pure UART and 2 SIR+UART ports through ISA or LPC
interface which cab be selected by hardware setting.
Each UART includes 16-byte
send/receive FIFO, a programmable baud rate generator, complete modem control capability
and an interrupt system. When using ISA interface mode, total 6 IRQ can be used, and each
one supports sharing function.
2 address decoder pins are provided for ISA mode as well.
When in LPC interface mode, some pins such as DATA pins, IOR, IOW, address decoder,
ISA address A0-A3 can be simple LPC to ISA transferring bridge pins.
And some other pins
can be set to be GPIO pins.
No matter in ISA or LPC mode, one watch dog timer is provided for system controlling
and the time interval can be programmed by register or hardware power on setting pin.
This IC needs one clock 24/48MHz input, and default is 24MHz.
Powered by 3.3V voltage,
the F81218 is in 100pin LQFP package (14mm x 14mm).
2. Feature List
„
Supports LPC or ISA interface (1 hardware setting pin to define LPC or ISA I/F )
„
In LPC mode, also provides simple LPC to ISA bridge
„
Totally provides 6 UART (16550 asynchronous) ports
„
„
„
„
„
„
‹
4 pure UART ports
‹
2 SIR+ UART ports
Provides 6 IRQ and each one can be shared
2 address decoder for ISA/LPC interface
1 watch dog timer with WDTOUT# signal
1 frequency input 24/48MHz
Powered by 3Vcc
100-LQFP(14mm x 14mm)
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3. Pin Configuration
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4. Pin Description
I/O8t5V-d100
- TTL level bi-directional pin with 8 mA source-sink capability, 5V tolerance, pull-down
100K ohms
I/O12t
- TTL level bi-directional pin with 12 mA source-sink capability
I/OD12
- TTL level bi-directional pin, Open-drain outpu with 12 mA sink capability
PCI5V
- bi-direction pin, slew rate control, 5V tolerance.
OUT12
- Output pin with 12 mA source-sink capability
OD12
- Open-drain output pin with 12 mA sink capability
INt
- TTL level input pin
INt5V
- TTL level input pin and 5V tolerance.
INts
- TTL level input pin and schmitt trigger
INts5V
- TTL level input pin and Schmitt trigger, 5V tolerance.
P
- Power
4.1 ISA/LPC Interface
Pin No.
Pin Name
Type
Description
99
ISA_IRQA
O12
Default is ISA IRQ output
IRQIN0
INt5V
When in LPC mode (pin 39 PS_LPC =1), the pin becomes LPC
to ISA IRQ input. About IRQ index setting please refer to pin84
and pin86.
100
ISA_IRQB
O12
Default is ISA IRQ output,
IRQIN1
INt5V
When in LPC mode (pin 39 PS_LPC =1), the pin becomes LPC
to ISA IRQ input. About IRQ index setting please refer to pin74
and pin76.
1
PCIRST#
INts
System PCI reset active low.
2
PME#
OD12
Generated PME event.
3
WDT_OUT#
OD12
Watch dog timer output.
When pin 50 power on setting
PS_WDT=0(default), Watch Dog timer time interval setting is
programmed by register. Once power on setting PS_WDT=1,
watch dog timer time interval will be fixed to 10 sec.
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4~7
ISA_A[3:0]
PCI5V
LPC_A[3:0]
ISA address bus bit 0-3.
When in LPC mode, these pins become LPC to ISA address
output.
8
9
11~14
ISA_IOR
INt5V
CPU I/O read signal.
LPC_IOR
OD12
When in LPC mode, these pin becomes LPC to ISA IOR output.
ISA_IOW
INt5V
CPU I/O write signal.
LPC_IOW
OD12
When in LPC mode, these pin becomes LPC to ISA IOW output.
ISA_A[10:7]
PCI5V
ISA address bus bits 7-10.
When in LPC mode, these signal lines communicate address,
LPC_LAD[3:0]
control, and data information over the LPC bus between a host
and a peripheral.
15
ISA_A6
INts5V
LPC_PCICLK
16
ISA_A5
ISA address bus bit 6
In LPC mode, this pin acts as PCI clock input.
INts5V
ISA address bus bit 5
In LPC mode, indicates start of a new cycle or termination of a
LPC_LFRAME#
broken cycle.
17
ISA_A4
PCI5V
LPC_SERIRQ
19~26
ISA_D[7:0]
ISA address bus bit 4.
In LPC mode, Serial IRQ input/Output.
PCI5V
LPC_D[7:0]
ISA data bus bits 0-7
When in LPC mode, the pins become LPC to ISA data bus bits
0-7.
27
CLKIN
INt
System clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register.
Default is 24MHz
input.
45
ISA_IRQE
O12
Default is ISA IRQ output, can act as GPIO function by
programming register. About IRQ index setting please refer to
pin67.
44
GP15
IN t5V
When in LPC mode, this pin acts as GPIO function
ISA_IRQF
O12
Default is ISA IRQ output, can be GPIO by programming
register. About IRQ index setting please refer to pin33.
GP16
IN t5V
When in LPC mode, this pin acts as GPIO function
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60
ISA_IRQC
O12
Default is ISA IRQ output
LPC_GP26
IN t5V
When in LPC mode (pin 39 PS_LPC =1), the pin becomes GPIO.
About IRQ index setting please refer to pin52
59
ISA_IRQD
O12
Default is ISA IRQ output
GP27
IN t5V
When in LPC mode (pin 39 PS_LPC =1), the pin becomes GPIO.
About IRQ index setting please refer to pin41.
92~96
ISA_A[15:11]
IN t
ISA address bus bits 11-15.
LPC_GP24
I/OD12
In LPC mode, these pins are all GPIO pins.
ISA_CS#
IN t
ISA chip select pin.
GP25
I/OD12
In LPC mode (pin 39 PS_LPC =1), this pin is GPIO.
ADD_DEC[1:0]#
OUT12
ISA address decoder,
LPC_DEC[1:0]#
OD12
When in LPC mode (pin 39 PS_LPC =1), the pin becomes LPC
LPC_GP23
LPC_GP22
LPC_GP21
LPC_GP20
91
98,97
to ISA address decoder.
4.2 UART Interface
Pin No.
Pin Name
Type
Description
28
CTS6#
INt5V
Clear To Send is the modem control input.
29
DSR6#
INt5V
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
30
RTS6#
I/O8t5V-d100
UART 6 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
31
DTR6#
I/O8t5V-d100
UART 6 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to communicate.
32
SIN6
INt5V
Serial Input. Used to receive serial data through the
communication link.
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33
SOUT6
I/O8t5V-d100
UART 6 Serial Output. Used to transmit serial data out to the
communication link.
PS_238_IRQF
Power setting pin to define the IRQF index.
Default PS_238_IRQF = 0, IRQF index is programmed by
register. If PS_238_IRQF = 1, setting IRQF index to 0x238
34
DCD6#
INt5V
Data Carrier Detect.
An active low signal indicates the
modem or data set has detected a data carrier.
35
RI6#
INt5V
Ring Indicator.
An active low signal indicates that a ring
signal is being received from the modem or data set.
36
CTS4#
INt5V
Clear To Send is the modem control input.
37
DSR4#
INt5V
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
38
RTS4#
I/O8t5V-d100
UART 4 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
39
DTR4#
I/O8t5V-d100
UART 4 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to communicate.
PS_LPC
Power on setting pin to define the ISA or LPC interface.
Default PS_LPC=0, ISA interface.
When PS_LPC=1, transfer to LPC interface.
40
SIN4
INt5V
Serial Input.
Used to receive serial data through the
communication link.
41
SOUT4
I/O8t5V-d100
UART 4 Serial Output. Used to transmit serial data out to the
communication link.
PS_2E8_IRQD
Power setting pin to define the IRQD index.
Default PS_2E8_IRQD = 0, IRQF index is programmed by
register.
If PS_2E8_IRQD = 1, setting IRQF index to 0x2E8.
42
DCD4#
INt5V
Data Carrier Detect.
An active low signal indicates the
modem or data set has detected a data carrier.
43
RI4#
INt5V
Ring Indicator.
An active low signal indicates that a ring
signal is being received from the modem or data set.
47
CTS3#
INt5V
Clear To Send is the modem control input.
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48
DSR3#
INt5V
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
49
RTS3#
I/O8t5V-d100
UART 3 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
50
PS_CONF_KE
Power on configuration setting pin. As for detail description,
Y0
please refer to register description.
DTR3#
I/O8t5V-d100
UART 3 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to communicate.
PS_WDT
Power on setting pin to enable the watch dog timer.
Default PS_WDT=0, WDT time programmed by register.
When PS_WDT=1, WDT time is defined as 10 sec.
51
SIN3
INt5V
Serial Input.
Used to receive serial data through the
communication link.
52
SOUT3
I/O8t5V-d100
UART 3 Serial Output. Used to transmit serial data out to the
communication link.
PS_3E8_IRQC
Power setting pin to define the IRQC index.
Default PS_3E8_IRQC = 0, IRQF index is programmed by
register.
If PS_3E8_IRQC = 1, setting IRQC index to 0x3E8.
53
DCD3#
INt5V
Data Carrier Detect.
An active low signal indicates the
modem or data set has detected a data carrier.
54
RI3#
INt5V
Ring Indicator.
An active low signal indicates that a ring
signal is being received from the modem or data set.
62
CTS5#
INt5V
Clear To Send is the modem control input.
63
DSR5#
INt5V
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
64
RTS5#
I/O8t5V-d100
UART 5 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
65
DTR5#
I/O8t5V-d100
UART 5 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to communicate.
66
SIN5
INt5V
Serial Input.
Used to receive serial data through the
communication link.
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67
SOUT5
I/O8t5V-d100
UART 5 Serial Output. Used to transmit serial data out to the
communication link.
PS_338_IRQE
Power setting pin to define the IRQE index.
Default PS_338_IRQE = 0, IRQF index is programmed by
register.
If PS_338_IRQE = 1, setting IRQF index to 0x338.
69
DCD5#
INt5V
Data Carrier Detect.
An active low signal indicates the
modem or data set has detected a data carrier.
70
RI5#
INt5V
Ring Indicator.
An active low signal indicates that a ring
signal is being received from the modem or data set.
71
CTS2#
INt5V
Clear To Send is the modem control input.
72
DSR2#
INt5V
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
73
RTS2#
I/O8t5V-d100
UART 2 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
74
PS_CONF_KE
Power on configuration setting pin. As for detail description,
Y1
please refer to register description.
DTR2#
I/O8t5V-d100
UART 2 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to communicate.
PS_2E0_IRQB
Power setting pin to define the IRQB index.
Default PS_2E0_IRQB = 0, IRQB index is programmed by
register.
If PS_2E0_IRQB = 1, setting IRQB index to 0x2E0.
75
SIN2
INt5V
Serial Input.
Used to receive serial data through the
communication link.
76
SOUT2
I/O8t5V-d100
UART 2 Serial Output. Used to transmit serial data out to the
communication link.
PS_2F8_IRQB
Power setting pin to define the IRQB index.
Default PS_2F8_IRQB = 0, IRQB index is programmed by
register.
If PS_2F8_IRQB = 1, setting IRQB index to 0x2F8.
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77
DCD2#
INt5V
Data Carrier Detect.
An active low signal indicates the
modem or data set has detected a data carrier.
78
RI2#
INt5V
Ring Indicator.
An active low signal indicates that a ring
signal is being received from the modem or data set.
79
IRRX2
INts5V
Infrared Receiver input.
80
IRTX2
OUT12
Infrared Transmitter Output.
81
CTS1#
INt5V
Clear To Send is the modem control input.
82
DSR1#
INt5V
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
83
RTS1#
I/O8t5V-d100
UART 1 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
PS_CONF_2E
Power on configuration setting. Default PS_CONF_2E = 0,
setting the configuration to 0x4E. If PS_CONF_2E =1, setting
the configuration to 0x2E.
84
DTR1#
I/O8t5V-d100
UART 1 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to communicate.
PS_3E0_IRQA
Power setting pin to define the IRQA index.
Default PS_3E0_IRQA = 0, IRQB index is programmed by
register.
If PS_3E0_IRQA = 1, setting IRQA index to 0x3E0.
85
SIN1
INt5V
Serial Input.
Used to receive serial data through the
communication link.
86
SOUT1
I/O8t5V-d100
UART 1 Serial Output. Used to transmit serial data out to the
communication link.
PS_3F8_IRQA
Power setting pin to define the IRQA index.
Default PS_3F8_IRQA = 0, IRQA index is programmed by
register.
If PS_3F8_IRQA = 1, setting IRQA index to 0x3F8.
87
DCD1#
INt5V
Data Carrier Detect.
An active low signal indicates the
modem or data set has detected a data carrier.
88
RI1#
INt5V
Ring Indicator.
An active low signal indicates that a ring
signal is being received from the modem or data set.
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89
IRRX1
INts5V
Infrared Receiver input.
90
IRTX1
OUT12
Infrared Transmitter Output.
4.3 GPIO pins
Pin No.
Pin Name
Type
Description
46,
GPIO14
I/OD12t
General purpose input/output pins.
55~58
GPIO13
GPIO12
GPIO11
GPIO10
4.4 Power
Pin No.
Pin Name
Type
Description
18,68
VCC
P
3.3V power supply.
10,61
GND
P
Ground.
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F81218
5. Functional Description
The F81218 totally provides 6 UART ports through ISA or LPC interface which can be
selected by hardware setting. Among 6 UART ports, two ports can support serial infrared
communication.
Besides, each UART includes 16-byte send/receive FIFO, a
programmable baud rate generator, completed modem control capability and interrupt
system. When using ISA interface mode, total 6 IRQ can be used, and each one supports
sharing function (IRQ sharing).
2 address decoder pins are provided for ISA mode as well.
When in LPC interface mode, some pins such as DATA pins, IOR, IOW, 2 address decoder,
ISA address A0-A3 can be simple LPC to ISA transferring bridge pins.
And some other pins
can be set to be GPIO pins.
No matter in ISA or LPC mode, one watch dog timer is provided for system controlling
and the time interval can be programmed by register or hardware power on setting pin.
This IC needs one clock 24/48MHz input, and default is 24MHz.
Powered by 3.3V voltage, the
F81218 is in 100pin LQFP
5.1
LPC Interface
The F81218 can support LPC interface serving as a bus interface between host
(chipset) and peripheral (I/O chip) by hardware trapping.
pins and more efficient transmission.
bus.
This interface provides much less
Data transfer on the LPC bus is serialized over a 4 bit
The general characteristics of the interface implemented in F81218 are listed as
below:
‹
One control line, namely LPC_FRAME#, which is used by the host to start or stop
transfers. No peripherals drive this signal.
‹
The LPC_LAD[3:0] bus, which communicates information serially.
The information
conveyed is cycle type, cycle direction, chip selection, address, data, and wait states.
‹
PCIRST# is an active low reset signal.
‹
An additional 33 MHz PCI clock is needed in the F81218 for synchronization.
‹
Interrupt requests are issued through LPC_SERIRQ.
‹
Power management events are issued through PME#.
5.2
UART
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A Universal Asynchronous Receiver/Transmitter (UART) is used to implement serial
communication. The F81218 incorporates six fully function UART compatible with NS16550D.
The UART ports perform serial to parallel conversion on receiving characters and parallel to
serial conversion on transmitting characters. The controllable characteristics of the data
transmission are baud rate, number of information bits per character, type of parity checking,
number of stop bits and breaking the transmission.
The serial format is a start bit, followed by
five to eight data bits, a parity bit(if programmable), and one, one and half, or two stop bits.
The
UART also includes completed modem control capability and interrupt system that may be
software trailed to the computing time required to handle the communication link.
The UART
also has a FIFO mode to reduce the number of interrupts presented to the CPU.
In the UART,
there is 16-byte FIFO for both receive and transmit mode.
5.2.1 UART Port Register
5.2.1.1
Receiver Buffer Register – Base + 0
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
RBR[7:0]
R/W
R
Description
The data received .
Read only when LCR[7] is 0
5.2.1.2
Transmitter Holding Register – Base + 0
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
THR[7:0]
R/W
W
Description
Data to be transmitted.
Write only when LCR[7] is 0
5.2.1.3
Divisor Latch ( LS ) – Base + 0
Power-on default [7:0] = 0x01h.
Bit
7:0
Name
DLL[7:0]
R/W
R/W
Description
Baud generator divisor low byte.
Access only when LCR[7] is 1.
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5.2.1.4
Divisor Latch ( MS ) – Base + 1
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
DLM[7:0]
R/W
R/W
Description
Baud generator divisor high byte.
Access only when LCR[7] is 1.
5.2.1.5
Interrupt Enable Register – Base + 1
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:4
Reserved
R/W
Return 0 when read. Access only when LCR[7] is 0
3
EDSSI
R/W
Enable Modem Status Interrupt. Access only when LCR[7] is 0.
2
ELSI
R/W
Enable Line Status Error Interrupt. Access only when LCR[7] is 0.
1
ETBFI
R/W
Enable Transmitter Holding Register Empty Interrupt. Access only
when LCR[7] is 0.
0
ERBFI
R/W
Enable Received Data Available Interrupt. Access only when LCR[7]
is 0
5.2.1.6
Interrupt Identification Register – Base + 2
Power-on default [7:0] = 0x01h.
Bit
7
Name
FIFO_EN
R/W
R
Description
0 : FIFO is disabled
1 : FIFO is enabled.
6
FIFO_EN
R
0 : FIFO is disabled.
1 : FIFO is enabled.
5:4
Reserved
R
Return 0 when read.
3:1
IRQ_ID[2:0]
R
000 : Interrupt is caused by Modem Status
001 : Interrupt is caused by Transmitter Holding Register Empty
010 : Interrupt is caused by Received Data Available.
110 : Interrupt is caused by Character Timeout
011 : Interrupt is caused by Line Status..
0
IRQ_PENDN
R
1 : Interrupt is not pending.
0 : Interrupt is pending.
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5.2.1.7
FIFO Control Register – Base + 2
Power-on default [7:0] = 0x00h.
Bit
7:6
Name
RCVR_TRIG[1:0]
R/W
W
Description
00 : Receiver FIFO trigger level is 1.
01 : Receiver FIFO trigger level is 4.
10 : Receiver FIFO trigger level is 8.
11 : Receiver FIFO trigger level is 14.
5:3
Reserved
W
2
CLRTX
W
1 : Reset the transmitter FIFO.
1
CLRRX
W
1 : Reset the receiver FIFO.
0
FIFO_EN
W
0 : Disable FIFO
1 : Enable FIFO
5.2.1.8
Line Control Register – Base + 3
Power-on default [7:0] = 0x00h.
Bit
7
Name
DLAB
R/W
R/W
Description
0 : Divisor Latch can’t be accessed.
1 : Divisor Latch can be accessed via Base and Base+1.
6
SETBRK
R/W
1 : Transmit a break condition.
0 : Transmitter is in normal condition.
5:3
STKPAR
R/W
XX0 : Parity Bit is disable
EPS
001 : Parity Bit is odd.
PEN
011 : Parity Bit is even
101 : Parity Bit is logic 1
111 : Parity Bit is logic 0
2
STB
R/W
0 : Stop bit is one bit
1 : When word length is 5 bit stop bit is 1.5 bit
else stop bit is 2 bit
1:0
WLS[1:0]
R/W
00 : Word length is 5 bit
01 : Word length is 6 bit
10 : Word length is 7 bit
11 : Word length is 8 bit
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5.2.1.9
MODEM Control Register – Base + 4
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 0 when read.
4
LOOP
R/W
0 : UART in normal condition.
1 : UART is internal loop back
3
OUT2
R/W
0 : All interrupt is disable.
1 : Interrupt is enabled/disabled by IER.
2
OUT1
R/W
Read from MSR[6] is loop back mode
1
RTS
R/W
0 : RTS# is forced to logic 1
1 : RTS# is forced to logic 0
0
DTR
R/W
0 : DTR# is forced to logic 1
1 : DTR# is forced to logic 0
5.2.1.10 Line Status Register – Base + 5
Power-on default [7:0] = 0x60h.
Bit
7
Name
RCR_ERR
R/W
R
Description
0 : No error in the FIFO when FIFO is enabled
1 : Error in the FIFO when FIFO is enabled.
6
TEMT
R
0 : Transmitter is in transmitting.
1 : Transmitter is empty.
5
THRE
R
0 : Transmitter Holding Register is not empty.
1 : Transmitter Holding Register is empty.
4
BI
R
0 : No break condition detected.
1 : A break condition is detected.
3
FE
R
0 : Data received has no frame error.
1 : Data received has frame error.
2
PE
R
0 : Data received has no parity error.
1 : Data received has parity error.
1
OE
R
0 : No overrun condition occur.
1 : A overrun condition occur.
0
DR
R
0 : No data is ready for read.
1 : Data is received .
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5.2.1.11 MODEM Status Register – Base + 6
Power-on default [7:0] = 0xX0h.
Bit
7
Name
DCD
R/W
R
Description
Complement of DCD# input. In loop back mode, this bit is equivalent
to OUT2 in MCR.
6
RI
R
Complement of RI# input. In loop back mode , this bit is equivalent to
OUT1 in MCR
5
DSR
R
Complement of DSR# input. In loop back mode , this bit is
equivalent to DTR in MCR
4
CTS
R
Complement of CTS# input. In loop back mode , this bit is equivalent
to RTS in MCR
3
DDCD
R
0 : No state changed at DCD#.
1 : State changed at DCD#.
2
TERI
R
0 : No Trailing edge at RI#.
1 : A low to high transition at RI#.
1
DDSR
R
0 : No state changed at DSR#.
1 : State changed at DSR#.
0
DCTS
R
0 : No state changed at CTS#.
1 : State changed at CTS#.
5.2.1.11 Scratch Register – Base + 7
Power-on default [7:0] = 0x00h.
Bit
7:0
5.3
Name
SCR_DATA[7:0]
R/W
R/W
Description
Scratch register.
IR Function
The F81218 infrared interface provides a two way wireless communications port using
infrared as the transmission medium. The IrDA 1.0 (SIR) is found in UART1 and UART2. IrDA SIR
specifies asynchronous serial communication at baud rate up to 115.2Kbps. Each byte is sent serial
LSB first beginning with a zero value start bit. A zero is signaled by sending a single infrared pulse at
the beginning of the serial bit time. A one is signaled by the absence of an infrared pulse during the
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bit time. IRTX acts as a transmit pin and IRRX acts as a receiving one. As for detail description,
please refer to register description.
5.4
Watch Dog Timer Function
Watch dog timer is provided for system controlling. If time-out can trigger one signal to low
level, the signal default is tri-state (need external pull up resister).
The time interval has three ways:
One is the hardware power on setting to enable, timer set to 10 second (24MHz). If
48MHz clock input, the timer is set to 5 second.
Two is programmed by registers.
The other is set the base address into registers, and use the base address the control it.
The timer unit has three kinds: 10mS, 1S, 1Min.
5.4.1
Watchdog Port Register
5.4.1.1
Timer Status and Control Register – Base + 0
Power-on default [7:0] = 0x02 when DTR3#/PS_WDT is pull-up, else 0x0.
Bit
Name
R/W
Description
7:3
Reserved
R/W
Return 0 when read.
2:1
WDT_UNIT[1:0]
R/W
00 : Timer Unit is 10ms.
01 : Timer Unit is 1 second
10 : Timer Unit is 1 minute.
11 : reserved.
0
WDT_EVENT
R/W
When read
0 : no time out occur.
1 : time out has occurred.
when write
0 : no action
1 : clear the time out status.
5.4.1.2
Timer Count Number Register – Base + 1
Power-on default [7:0] = 0x0Ah when DTR3#/PS_WDT is pull-up , else 0x00h.
Bit
7:0
Name
WDT_CNT[7:0]
R/W
Description
R/W
The number of count for watchdog timer.
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F81218
Write the same value to enable the timer, write 0 to disable timer.
5.5
Serial IRQ
F81218 supports a serial IRQ scheme.
legacy ISA interrupt requests.
This allows a signal line to be used to report the
Because more than one device may need to share the signal serial
IRQ signal line, an open drain signal scheme is used.
The clock source is the PCI clock.
The
serial interrupt is transferred on the SERIRQ signal, one cycle consisting of three frames types: a
start frame, several IRQ/Data frame, and one Stop frame.
5.5.1 Start Frame
There are two modes of operation for the SERIRQ Start frame: Quiet mode and Continuous
mode.
In the Quiet mode, the peripheral drives the SERIRQ signal active low for one clock, and
then tri-states it.
This brings all the states machines of the peripherals from idle to active states.
The host controller will then take over driving SERIRQ signal low in the next clock and will continue
driving the SERIRQ low for programmable 3 to 7 clock periods.
This makes the total number of
clocks low for 4 to 8 clock periods. After these clocks, the host controller will drive the SERIRQ high
for one clock and then tri-states it.
In the Continuous mode, only the host controller initiates the
START frame to update IRQ/Data line information.
low for 4 to 8 clock periods.
The host controller drives the SERIRQ signal
Upon a reset, the SERIRQ signal is defaulted to the Continuous mode
for the host controller to initiate the first Start frame.
5.5.2 IRQ/Data Frame
Once the start frame has been initiated, all the peripherals must start counting frames based
on the rising edge of the start pulse.
Each IRQ/Data Frame is three clocks: Sample phase,
Recovery phase, and Turn-around phase. During the Sample phase, the peripheral drives SERIRQ
low if the corresponding IRQ is active.
left tri-stated.
If the corresponding IRQ is inactive, then SERIRQ must be
During the Recovery phase, the peripheral device drives the SERIRQ high.
During
the Turn-around phase, the peripheral device left the SERIRQ tri-stated. The IRQ/Data Frame has
a number of specific order , as shown in Table 5-1. The F81218 is only support IRQ3, IRQ4, IRQ5,
IRQ9, IRQ10, and IRQ11.
Table 5-1 IRQSER Sampling periods
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IRQ/Data Frame
Signal Sampled
# of clocks past Start
1
IRQ0
2
2
IRQ1
5
3
SMI#
8
4
IRQ3
11
5
IRQ4
14
6
IRQ5
17
7
IRQ6
20
8
IRQ7
23
9
IRQ8
26
10
IRQ9
29
11
IRQ10
32
12
IRQ11
35
13
IRQ12
38
14
IRQ13
41
15
IRQ14
44
16
IRQ15
47
17
IOCHCK#
50
18
INTA#
53
19
INTB#
56
20
INTC#
59
21
INTD#
62
32:22
Unassigned
95
5.5.3 Stop Frame
After all IRQ/Data Frames have completed, the host controller will terminate SERIRQ by
a Stop frame.
Only the host controller can initiate the Stop frame by driving SERIRQ low for 2 or 3
clocks.
If the Stop Frame is low for 2 clocks, the next SERIRQ cycle's Sample mode is the Quiet
mode.
If the Stop Frame is low for 3 clocks, the next SERIRQ cycle's Sample mode is the
Continuous mode.
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6. Register Description
Registers are programmed by port 0x4E and 0x4F. 0x4E is the index port and 0x4F is the data port .
To enable configuration registers programming, entry key must output twice to index port
continuously. The entry key is decided by power on setting pins RTS2#/PS_CONF_KEY1 and
RTS3#/PS_CONF_KEY0 as following:
RTS2#/PS_CONF_KEY1
RTS3#/PS_CONF_KEY0
Entry key
0
0
0x77 ( default )
0
1
0xA0
1
0
0x87
1
1
0x67
To exit configuration registers programming, output 0xAA to index port.
Sample code for configuration:
1. Clock in used 48MHz, UART 1~6 address (0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x3e0, 0x2e0), IRQ(3,
4, 5 ,9 , 10 , 11, Entry key is 0x77:
outportb(0x4e, 0x77);
outportb(0x4e, 0x77);
//Entry configuration mode
outportb(0x4e, 0x25);
//Select register index 0x25
outportb(0x4f, 0x01);
//Set bit 0 to 1 select clock input to 48MHz
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x00);
//Select LDN 0
outportb(0x4e, 0x60);
//Select LDN 0 register index 0x60
outportb(0x4f, 0x03);
//Set UART 1 base address high byte to 0x03
outportb(0x4e, 0x61);
//Select LDN 0 register index 0x61
outportb(0x4f, 0xf8);
//Set UART 1 base address low byte to 0xf8
outportb(0x4e, 0x70);
//Select LDN 0 register index 0x70
outportb(0x4f, 0x03);
//Set UART 1 interrupt channel to IRQ 3
outportb(0x4e, 0x30);
//Select LDN 0 register index 0x30
outportb(0x4f, 0x01);
//Enable UART 1
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x01);
//Select LDN 1
outportb(0x4e, 0x60);
//Select LDN 1 register index 0x60
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outportb(0x4f, 0x02);
//Set UART 2 base address high byte to 0x02
outportb(0x4e, 0x61);
//Select LDN 1 register index 0x61
outportb(0x4f, 0xf8);
//Set UART 2 base address low byte to 0xf8
outportb(0x4e, 0x70);
//Select LDN 1 register index 0x70
outportb(0x4f, 0x04);
//Set UART 2 interrupt channel to IRQ 4
outportb(0x4e, 0x30);
//Select LDN 1 register index 0x30
outportb(0x4f, 0x01);
//Enable UART 2
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x02);
//Select LDN 2
outportb(0x4e, 0x60);
//Select LDN 2 register index 0x60
outportb(0x4f, 0x03);
//Set UART 3 base address high byte to 0x03
outportb(0x4e, 0x61);
//Select LDN 2 register index 0x61
outportb(0x4f, 0xe8);
//Set UART 3 base address low byte to 0xe8
outportb(0x4e, 0x70);
//Select LDN 2 register index 0x70
outportb(0x4f, 0x05);
//Set UART 3 interrupt channel to IRQ 5
outportb(0x4e, 0x30);
//Select LDN 2 register index 0x30
outportb(0x4f, 0x01);
//Enable UART 3
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x03);
//Select LDN 3
outportb(0x4e, 0x60);
//Select LDN 3 register index 0x60
outportb(0x4f, 0x02);
//Set UART 4 base address high byte to 0x02
outportb(0x4e, 0x61);
//Select LDN 3 register index 0x61
outportb(0x4f, 0xe8);
//Set UART 4 base address low byte to 0xe8
outportb(0x4e, 0x70);
//Select LDN 3 register index 0x70
outportb(0x4f, 0x09);
//Set UART 4 interrupt channel to IRQ 9
outportb(0x4e, 0x30);
//Select LDN 3 register index 0x30
outportb(0x4f, 0x01);
//Enable UART 4
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x04);
//Select LDN 4
outportb(0x4e, 0x60);
//Select LDN 4 register index 0x60
outportb(0x4f, 0x03);
//Set UART 5 base address high byte to 0x03
outportb(0x4e, 0x61);
//Select LDN 4 register index 0x61
outportb(0x4f, 0xe0);
//Set UART 5 base address low byte to 0xe0
outportb(0x4e, 0x70);
//Select LDN 4 register index 0x70
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outportb(0x4f, 0x0a);
//Set UART 5 interrupt channel to IRQ 10
outportb(0x4e, 0x30);
//Select LDN 4 register index 0x30
outportb(0x4f, 0x01);
//Enable UART 5
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x05);
//Select LDN 5
outportb(0x4e, 0x60);
//Select LDN 5 register index 0x60
outportb(0x4f, 0x02);
//Set UART 6 base address high byte to 0x02
outportb(0x4e, 0x61);
//Select LDN 5 register index 0x61
outportb(0x4f, 0xe0);
//Set UART 6 base address low byte to 0xe0
outportb(0x4e, 0x70);
//Select LDN 5 register index 0x70
outportb(0x4f, 0x0b);
//Set UART 6 interrupt channel to IRQ 11
outportb(0x4e, 0x30);
//Select LDN 5 register index 0x30
outportb(0x4f, 0x01);
//Enable UART 6
outportb(0x4e, 0xaa);
//Exit configuration mode
2. Set Address decoder 0 to decode 0x380~0x387:
outportb(0x4e, 0x77);
outportb(0x4e, 0x77);
//Entry configuration mode
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x06);
//Select LDN 6
outportb(0x4e, 0x60);
//Select LDN 6 register index 0x60
outportb(0x4f, 0x03);
//Set Address decoder 0 base address high byte to 0x03
outportb(0x4e, 0x61);
//Select LDN 6 register index 0x61
outportb(0x4f, 0x80);
//Set Address decoder 0 base address low byte to 0x80
outportb(0x4e, 0x62);
//Select LDN 6 register index 0x62
outportb(0x4f, 0x03);
//Set Address decoder 0 base address mask 3 bit
outportb(0x4e, 0x30);
//Select LDN 6 register index 0x30
outportb(0x4f, 0x01);
//Enable Address decoder 0 Device
outportb(0x4e, 0xaa);
//Exit configuration mode
3. Set Address decoder 1 to decode 0x480~0x480:
outportb(0x4e, 0x77);
outportb(0x4e, 0x77);
//Entry configuration mode
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x07);
//Select LDN 7
outportb(0x4e, 0x60);
//Select LDN 7 register index 0x60
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outportb(0x4f, 0x04);
//Set Address decoder 1 base address high byte to 0x04
outportb(0x4e, 0x61);
//Select LDN 7 register index 0x61
outportb(0x4f, 0x80);
//Set Address decoder 1 base address low byte to 0x80
outportb(0x4e, 0x62);
//Select LDN 7 register index 0x62
outportb(0x4f, 0x00);
//Set Address decoder 0 base address decode A0~A15
outportb(0x4e, 0x30);
//Select LDN 7 register index 0x30
outportb(0x4f, 0x01);
//Enable Address decoder 1 Device
outportb(0x4e, 0xaa);
//Exit configuration mode
4. Set Watch Dog timer base address 0x300~0x301:
outportb(0x4e, 0x77);
outportb(0x4e, 0x77);
//Entry configuration mode
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x08);
//Select LDN 8
outportb(0x4e, 0x60);
//Select LDN 8 register index 0x60
outportb(0x4f, 0x03);
//Set Watch Dog timer base address high byte to 0x03
outportb(0x4e, 0x61);
//Select LDN 8 register index 0x61
outportb(0x4f, 0x00);
//Set Watch Dog Timer base address low byte to 0x00
outportb(0x4e, 0x30);
//Select LDN 8 register index 0x30
outportb(0x4f, 0x01);
//Enable Watch Dog Timer Device
outportb(0x4e, 0xaa);
//Exit configuration mode
5. Set Watch Dog timer to 20 second used base address 0x300~0x301:
outportb(0x300, 0x03); //Select unit to one second and clear time out status
outportb(0x301, 0x14);
outportb(0x301, 0x14);
6.1
//Set timer to 20 second and enable timer
Global Control Register
6.1.1 Software Reset Register – index 02h
Power-on default [7:0] = 0x00h
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
SWRST
R/W
Write 1 to reset configuration register. This bit is auto cleared.
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6.1.2 Logic Device Select Register – index 07h
Power-on default [7:0] = 0x00h
Bit
7:0
Name
LDN[7:0]
R/W
R/W
Description
00h : Select UART 1 device configuration register
01h : Select UART 2 device configuration register
02h : Select UART 3 device configuration register
03h : Select UART 4 device configuration register
04h : Select UART 5 device configuration register
05h : Select UART 6 device configuration register
06h : Select Address Decoder 1 device configuration register
07h : Select Address Decoder 2 device configuration register
08h : Select Watchdog Timer device configuration register
09h : Select GPIO and PME device configuration register
6.1.3 Device ID Register– index 20h, 21h
Power-on default [7:0], 0x02h for index 20h, 0x06h for index 21h
Bit
7:0
Name
DEVID
R/W
R
Description
Return 0206h when read index 20h and 21h respectively, indicate the
device ID.
6.1.4 Vendor ID Register– index 23h, 24h
Power-on default [7:0], 0x19h for index 23h, 0x34h for index 24h
Bit
7:0
Name
VENDID
R/W
R
Description
Return 1934h when read index 23h and 24h respectively, indicate the
vendor ID of Fintek.
6.1.5 Clock Source Select Register – index 25h
Power-on default [7:0], 0x00h
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
CLK_SEL
R/W
1 : The CLKIN is 48MHz
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F81218
0 : The CLKIN is 24MHz.
This bit must program to indicate the frequency of the clock source, or
the device will not function correctly.
6.1.6 GPIO Function Select Register ( ISA Interface Only ) – index 26h
Power-on default [7:0],0x00h
Bit
Name
R/W
Description
7:4
Reserved
R/W
Return 0 when read.
3
GP16_SEL
R/W
1 : ISA_IRQF/GP16 functions as GPIO.
0 : ISA_IRQF/GP16 functions as ISA_IRQF.
In LPC mode , ISA_IRQF/GP16 functions as GP16
2
GP15_SEL
R/W
1 : ISA_IRQE/GP15 functions as GPIO.
0 : ISA_IRQE/GP15 functions as ISA_IRQE.
In LPC mode , ISA_IRQE/GP15 functions as GP15
1
GP27_SEL
R/W
1 : ISA_IRQD/GP26 functions as GPIO.
0 : ISA_IRQD/GP26 functions as ISA_IRQD.
In LPC mode , ISA_IRQD/GP27 functions as GP27
0
GP26_SEL
R/W
1 : ISA_IRQC/GP25 functions as GPIO.
0 : ISA_IRQC/GP25 functions as ISA_IRQC.
In LPC mode , ISA_IRQC/GP26 functions as GP26
6.1.7 Test Mode Register – index 2Fh
Power-on default [7:0], 0000_0000b
Bit
7:0
Name
TESTMODE
R/W
R/W
Description
Test mode register, reserved for Fintek use only.
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F81218
6.2 UART 1 Device Control Register (LDN 0)
6.2.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pull-up,
else 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
URA_EN
R/W
0 : Disable UART 1.
1 : Enable UART 1..
6.2.2
I/O Port Select Register – index 60h
Power-on default [7:0] = 0x03h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pullup,
else 0x00h.
Bit
7:0
Name
R/W
URA_BASE[15:8]
R/W
6.2.3
Description
UART 1 I/O Port Address high byte.
I/O Port Select Register – index 61h
Power-on default [7:0] = 0xF8h when SOUT1/PS_3F8_IRQA is pull-up,
0xE0h when DTR1#/PS_3E0_IRQA is pull-up, else 0x00h.
Bit
7:0
Name
URA_BASE[7:0]
6.2.4
R/W
R/W
Description
UART 1 I/O Port Address low byte.
IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x03h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pull-up,
else 0x00h
Bit
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read.
5
URAIRQ_MODE
R/W
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
4
URAIRQ_SHAR
R/W
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
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3:0
SELURAIRQ[3:0]
R/W
In LPC mode , select the Serial IRQ channel.
In ISA mode , select one of six IRQ pins .
03h : use serial IRQ channel 3 in LPC mode or use ISA_IRQA in ISA
mode.
04h : use serial IRQ channel 4 in LPC mode or use ISA_IRQB in ISA
mode.
05h : use serial IRQ channel 5 in LPC mode or use ISA_IRQC in ISA
mode.
09h : use serial IRQ channel 9 in LPC mode or use ISA_IRQD in ISA
mode.
0Ah : use serial IRQ channel 10 in LPC mode or use ISA_IRQE in
ISA mode.
0Bh : use serial IRQ channel 11 in LPC mode or use ISA_IRQF in
ISA mode.
Otherwise will disable interrupt.
6.2.5
UART 1 Clock Select Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 0 when read.
4
RS485
R/W
0: The RTS# is controlled by programming MCR[1]. (offset +4)
1: The RTS# is drive high when transmitting data and sink low when
receiving data.
3
RXW4C_IRA
R/W
0 : No reception delay when SIR is changed from TX to RX.
1 : Reception delay 4 character-time when SIR is changed from TX
to RX.
2
TXW4C_IRA
R/W
0 : No transmission delay when SIR is changed from RX to TX.
1 : Transmission delay 4 character-time when SIR is changed from
RX to TX.
1:0
SELURACLK1
SELURACLK0
R/W
00 : UART 1 clock source is 1.8462MHz ( 24MHz/13 )
01/10/11 selection reserved.
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6.2.6
IR1 Control Register – index F1h
Power-on default [7:0] = 0x44h.
Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 010b when read.
4:3
IRA_MODE1
R/W
0X: Disable IR1 function.
IRA_MODE0
10 : Enable IR1 function, active pulse is 1.6uS.
11 : Enable IR1 function, active pulse is 3/16 bit time.
2
Half_Full_Duplex
R/W
0 : Full Duplex function for IR self test.
1 : Half Duplex function.
Return 1 when read.
1
TXINV_IRA
R/W
0 : IRTX1 is not inversed.
1 : Inverse the IRTX1.
0
RXINV_IRA
R/W
0 : IRRX1 is not inversed.
1 : Inverse the IRRX1.
6.3 UART 2 Device Control Register (LDN 1)
6.3.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB is pull-up,
else 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
URB_EN
R/W
0 : Disable UART 2.
1 : Enable UART 2.
6.3.2
I/O Port Select Register – index 60h
Power-on default [7:0] = 0x02h when SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB is pullup,
else 0x00h.
Bit
7:0
Name
R/W
URB_BASE[15:8]
R/W
Description
UART 2 I/O Port Address high byte.
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F81218
6.3.3
I/O Port Select Register – index 61h
Power-on default [7:0] = 0xF8h when SOUT2/PS_2F8_IRQB is pull-up,
0xE0h when DTR2#/PS_2E0_IRQB is pull-up, else 0x00h.
Bit
7:0
Name
URB_BASE[7:0]
6.3.4
R/W
R/W
Description
UART 2 I/O Port Address low byte.
IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x03h when SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB is pull-up,
else 0x00h
Bit
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read.
5
URBIRQ_MODE
R/W
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
4
URBIRQ_SHAR
R/W
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
3:0
SELURAIRQ[3:0]
R/W
In LPC mode , select the Serial IRQ channel.
In ISA mode , select one of six IRQ pins .
03h : use serial IRQ channel 3 in LPC mode or use ISA_IRQA in ISA
mode.
04h : use serial IRQ channel 4 in LPC mode or use ISA_IRQB in ISA
mode.
05h : use serial IRQ channel 5 in LPC mode or use ISA_IRQC in ISA
mode.
09h : use serial IRQ channel 9 in LPC mode or use ISA_IRQD in ISA
mode.
0Ah : use serial IRQ channel 10 in LPC mode or use ISA_IRQE in
ISA mode.
0Bh : use serial IRQ channel 11 in LPC mode or use ISA_IRQF in
ISA mode.
Otherwise will disable interrupt.
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6.3.5
UART 2 Clock Select Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 0 when read.
4
RS485
R/W
0: The RTS# is controlled by programming MCR[1]. (offset +4)
1: The RTS# is drive high when transmitting data and sink low when
receiving data.
3
RXW4C_IRB
R/W
0 : No reception delay when SIR is changed from TX to RX.
1 : Reception delay 4 character-time when SIR is changed from TX
to RX.
2
TXW4C_IRB
R/W
0 : No transmission delay when SIR is changed from RX to TX.
1 : Transmission delay 4 character-time when SIR is changed from
RX to TX.
1:0
SELURACLK1
R/W
SELURACLK0
6.3.6
00 : UART 2 clock source is 1.8462MHz ( 24MHz/13 )
01/10/11 selection reserved.
IR 2 Control Register – index F1h
Power-on default [7:0] = 0x44h.
Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 010b when read.
4:3
IRB_MODE1
R/W
0X: Disable IR2 function.
IRB_MODE0
10 : Enable IR2 function, active pulse is 1.6uS.
11 : Enable IR2 function, active pulse is 3/16 bit time.
2
Half_Full_Duplex
R/W
0 : Full Duplex function for IR self test.
1 : Half Duplex function.
Return 1 when read.
1
TXINV_IRB
R/W
0 : IRTX2 is not inversed.
1 : Inverse the IRTX2.
0
RXINV_IRB
R/W
0 : IRRX2 is not inversed.
1 : Inverse the IRRX2.
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V0.33P
F81218
6.4 UART 3 Device Control Register (LDN 2)
6.4.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT3/PS_3E8_IRQC is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
URC_EN
R/W
0 : Disable UART 3.
1 : Enable UART 3.
6.4.2
I/O Port Select Register – index 60h
Power-on default [7:0] = 0x03h when SOUT3/PS_3E8_IRQC is pull-up, else 0x00h.
Bit
7:0
Name
R/W
URC_BASE[15:8]
R/W
6.4.3
Description
UART 3 I/O Port Address high byte.
I/O Port Select Register – index 61h
Power-on default [7:0] = E8h when SOUT3/PS_3E8_IRQC is pull-up, else 0x00h.
Bit
7:0
Name
R/W
URC_BASE[7:0]
R/W
6.4.4
Description
UART 3 I/O Port Address low byte.
IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x05h when SOUT3/PS_3E8_IRQC is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read.
5
URCIRQ_MODE
R/W
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
4
URCIRQ_SHAR
R/W
0 : IRQ is not sharing with other device.
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1 : IRQ is sharing with other device.
3:0
SELURCIRQ[3:0]
R/W
In LPC mode , select the Serial IRQ channel.
In ISA mode , select one of six IRQ pins .
03h : use serial IRQ channel 3 in LPC mode or use ISA_IRQA in ISA
mode.
04h : use serial IRQ channel 4 in LPC mode or use ISA_IRQB in ISA
mode.
05h : use serial IRQ channel 5 in LPC mode or use ISA_IRQC in ISA
mode.
09h : use serial IRQ channel 9 in LPC mode or use ISA_IRQD in ISA
mode.
0Ah : use serial IRQ channel 10 in LPC mode or use ISA_IRQE in
ISA mode.
0Bh : use serial IRQ channel 11 in LPC mode or use ISA_IRQF in
ISA mode.
Otherwise will disable the interrupt.
6.4.5
UART 3 Clock Select Register – index F0h
Power-on default [7:0] = 0000_0000b.
Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 0 when read.
4
RS485
R/W
0: The RTS# is controlled by programming MCR[1]. (offset +4)
1: The RTS# is drive high when transmitting data and sink low when
receiving data.
3:2
Reserved
R/W
Return 0 when read.
1:0
SELURCCLK1
R/W
00 : UART 3 clock source is 1.8462MHz ( 24MHz/13 )
SELURCCLK0
01/10/11 selection reserved.
6.5 UART 4 Device Control Register (LDN 3)
6.5.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT4/PS_2E8_IRQD is pull-up, else 0x00h.
Bit
Name
R/W
Description
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7:1
Reserved
R/W
Return 0 when read.
0
URD_EN
R/W
0 : Disable UART 4.
1 : Enable UART 4.
6.5.2
I/O Port Select Register – index 60h
Power-on default [7:0] = 0x02h when SOUT4/PS_2E8_IRQD is pull-up, else 0x00h.
Bit
7:0
Name
R/W
URD_BASE[15:8]
R/W
6.5.3
Description
UART 4 I/O Port Address high byte.
I/O Port Select Register – index 61h
Power-on default [7:0] = 0xE8h when SOUT4/PS_2E8_IRQD is pull-up, else 0x00h.
Bit
7:0
Name
R/W
URD_BASE[7:0]
R/W
6.5.4
Description
UART 4 I/O Port Address low byte.
IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x09h when SOUT4/PS_2E8_IRQD is pull-up, else 0x00h.
Name
R/W
Description
7:6
5
Bit
Reserved
URDIRQ_MODE
R/W
R/W
4
URDIRQ_SHAR
R/W
Return 0 when read.
0 : PCI IRQ sharing mode
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
3:0
SELURDIRQ[3:0]
R/W
In LPC mode , select the Serial IRQ channel.
In ISA mode , select one of six IRQ pins .
03h : use serial IRQ channel 3 in LPC mode or use ISA_IRQA in ISA
mode.
04h : use serial IRQ channel 4 in LPC mode or use ISA_IRQB in ISA
mode.
05h : use serial IRQ channel 5 in LPC mode or use ISA_IRQC in ISA
mode.
09h : use serial IRQ channel 9 in LPC mode or use ISA_IRQD in ISA
mode.
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0Ah : use serial IRQ channel 10 in LPC mode or use ISA_IRQE in
ISA mode.
0Bh : use serial IRQ channel 11 in LPC mode or use ISA_IRQF in
ISA mode.
Otherwise will disable the interrupt.
6.5.5
UART 4 Clock Select Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 0 when read.
4
RS485
R/W
0: The RTS# is controlled by programming MCR[1]. (offset +4)
1: The RTS# is drive high when transmitting data and sink low when
receiving data.
3:2
Reserved
R/W
Return 0 when read.
1:0
SELURCCLK1
R/W
00 : UART 3 clock source is 1.8462MHz ( 24MHz/13 )
SELURCCLK0
01/10/11 selection reserved.
6.6 UART 5 Device Control Register (LDN 4)
6.6.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT5/PS_338_IRQE is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
URE_EN
R/W
0 : Disable UART 5.
1 : Enable UART 5.
6.6.2
I/O Port Select Register – index 60h
Power-on default [7:0] = 0x03h when SOUT5/PS_338_IRQE is pull-up, else 0x00h.
Bit
7:0
Name
R/W
URE_BASE[15:8]
R/W
Description
UART 5 I/O Port Address high byte.
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F81218
6.6.3
I/O Port Select Register – index 61h
Power-on default [7:0] = 0x38hwhen SOUT5/PS_338_IRQE is pull-up, else 0x00h.
Bit
7:0
Name
URE_BASE[7:0]
6.6.5
R/W
R/W
Description
UART 5 I/O Port Address low byte.
IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x0Ah when SOUT5/PS_338_IRQE is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read.
5
UREIRQ_MODE
R/W
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
4
UREIRQ_SHAR
R/W
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
3:0
SELUREIRQ[3:0]
R/W
In LPC mode , select the Serial IRQ channel.
In ISA mode , select one of six IRQ pins .
03h : use serial IRQ channel 3 in LPC mode or use ISA_IRQA in ISA
mode.
04h : use serial IRQ channel 4 in LPC mode or use ISA_IRQB in ISA
mode.
05h : use serial IRQ channel 5 in LPC mode or use ISA_IRQC in ISA
mode.
09h : use serial IRQ channel 9 in LPC mode or use ISA_IRQD in ISA
mode.
0Ah : use serial IRQ channel 10 in LPC mode or use ISA_IRQE in
ISA mode.
0Bh : use serial IRQ channel 11 in LPC mode or use ISA_IRQF in
ISA mode.
Otherwise will disable the interrupt.
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V0.33P
F81218
6.6.6
UART 5 Clock Select Register – index F0h
Power-on default [7:0] = 0000_0000b.
Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 0 when read.
4
RS485
R/W
0: The RTS# is controlled by programming MCR[1]. (offset +4)
1: The RTS# is drive high when transmitting data and sink low when
receiving data.
3:2
Reserved
R/W
Return 0 when read.
1:0
SELURCCLK1
R/W
00 : UART 3 clock source is 1.8462MHz ( 24MHz/13 )
SELURCCLK0
01/10/11 selection reserved.
6.7 UART 6 Device Control Register (LDN 5)
6.7.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT6/PS_238_IRQF is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
URF_EN
R/W
0 : Disable UART 6.
1 : Enable UART 6.
6.7.2
I/O Port Select Register – index 60h
Power-on default [7:0] = 0x02h when SOUT6/PS_238_IRQF is pull-up, else 0x0h.
Bit
7:0
Name
R/W
URF_BASE[15:8]
R/W
6.7.3
Description
UART 6 I/O Port Address high byte.
I/O Port Select Register – index 61h
Power-on default [7:0] = 0x38h when SOUT6/PS_238_IRQF is pull-up, else 0x00h.
Bit
7:0
Name
URF_BASE[7:0]
R/W
R/W
Description
UART 6 I/O Port Address low byte.
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August, 2007
V0.33P
F81218
6.7.4
IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x0Bh when SOUT6/PS_238_IRQF is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read.
5
URFIRQ_MODE
R/W
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
4
URFIRQ_SHAR
R/W
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
3:0
SELURFIRQ[3:0]
R/W
In LPC mode , select the Serial IRQ channel.
In ISA mode , select one of six IRQ pins .
03h : use serial IRQ channel 3 in LPC mode or use ISA_IRQA in ISA
mode.
04h : use serial IRQ channel 4 in LPC mode or use ISA_IRQB in ISA
mode.
05h : use serial IRQ channel 5 in LPC mode or use ISA_IRQC in ISA
mode.
09h : use serial IRQ channel 9 in LPC mode or use ISA_IRQD in ISA
mode.
0Ah : use serial IRQ channel 10 in LPC mode or use ISA_IRQE in
ISA mode.
0Bh : use serial IRQ channel 11 in LPC mode or use ISA_IRQF in
ISA mode.
Otherwise will disable the interrupt.
6.7.5
UART 6 Clock Select Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 0 when read.
4
RS485
R/W
0: The RTS# is controlled by programming MCR[1]. (offset +4)
1: The RTS# is drive high when transmitting data and sink low when
receiving data.
3:2
Reserved
R/W
Return 0 when read.
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F81218
1:0
SELURCCLK1
R/W
00 : UART 3 clock source is 1.8462MHz ( 24MHz/13 )
SELURCCLK0
01/10/11 selection reserved.
6.8 Address Decoder 0 Device Control Register (LDN 6)
6.8.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
ADDEC0_EN
R/W
0 : Disable Address Decoder 0.
1 : Enable Address Decoder 0.
6.8.2
Address Decoder Select Register 0– index 60h
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
R/W
DEC0_BASE[15:8]
R/W
6.8.3
Description
Address high byte for ADD_DEC0/LPC_DEC0 .
Address Decoder Select Register 1– index 61h
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
R/W
DEC0_BASE[7:0]
R/W
6.8.4
Description
Address low byte for ADD_DEC0/LPC_DEC0.
Address Mask Register – index 62h
Power-on default [7:0] = 0x00h
Bit
Name
R/W
Description
7:3
Reserved
R/W
Return 0 when read.
2:0
DEC0_SEL[2:0]
R/W
000 : Decode all 16 bits .
001 : Decode bit 15:1
010 : Decode bit 15:2
011 : Decode bit 15:3
100 : Decode bit 15:4
-38-
August, 2007
V0.33P
F81218
6.8.5
IRQIN0 Channel Select Register (Only for LPC) – index 70h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read.
5
IRQIN0_MODE
R/W
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
4
IRQIN0_SHAR
R/W
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
3:0
SELRQIN0[3:0]
R/W
In LPC mode , select the Serial IRQ channel.
03h : use serial IRQ channel 3 in LPC mode.
04h : use serial IRQ channel 4 in LPC mode.
05h : use serial IRQ channel 5 in LPC mode.
09h : use serial IRQ channel 9 in LPC mode.
0Ah : use serial IRQ channel 10 in LPC mode.
0Bh : use serial IRQ channel 11 in LPC mode.
Otherwise will disable the interrupt.
6.9 Address Decoder 1 Device Control Register (LDN 7)
6.9.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
ADDEC1_EN
R/W
0 : Disable Address Decoder 1.
1 : Enable Address Decoder 1.
6.9.2
Address Decoder Select Register 0 – index 60h
Power-on default [7:0] = 0x00h.
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Bit
7:0
Name
R/W
DEC1_BASE[15:8]
R/W
6.9.3
Description
Address high byte for ADD_DEC1/LPC_DEC1 .
Address Decoder Select Register 1 – index 61h
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
R/W
DEC1_BASE[7:0]
R/W
6.9.4
Description
Address low byte for ADD_DEC1/LPC_DEC1.
Address Mask Register – index 62h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:3
Reserved
R/W
Return 0 when read.
2:0
DEC1_SEL[2:0]
R/W
000 : Decode all 16 bits .
001 : Decode bit 15:1
010 : Decode bit 15:2
011 : Decode bit 15:3
100 : Decode bit 15:4
6.9.5
IRQIN1 Channel Select Register (Only for LPC) – index 70h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read.
5
IRQIN1_MODE
R/W
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
4
IRQIN1_SHAR
R/W
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
3:0
SELIRQIN1[3:0]
R/W
In LPC mode , select the Serial IRQ channel.
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In ISA mode , select one of six IRQ pins .
03h : use serial IRQ channel 3 in LPC mode.
04h : use serial IRQ channel 4 in LPC mode.
05h : use serial IRQ channel 5 in LPC mode.
09h : use serial IRQ channel 9 in LPC mode.
0Ah : use serial IRQ channel 10 in LPC mode.
0Bh : use serial IRQ channel 11 in LPC mode.
Otherwise will disable the interrupt.
6.10 Watch Dog Timer Device Control Register (LDN 8)
6.10.1 Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when DTR3#/PS_WDT is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
WDT_EN
R/W
0 : Disable Watchdog Timer.
1 : Enable Watchdog Timer.
6.10.2 I/O Port Select Register – index 60h
Power-on default [7:0] = 0x04h when DTR3#/PS_WDT is pull-up, else 0x00h.
Bit
7:0
Name
WDT_BASE[15:8]
R/W
R/W
Description
I/O Base high byte.
6.10.3 I/O Port Select Register – index 61h
Power-on default [7:0] = 0x42h when DTR3#/PS_WDT is pull-up, else 0x00h.
Bit
7:0
Name
R/W
WDT_BASE[7:0]
R/W
Description
I/O Base low byte.
6.10.4 IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x00h.
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Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 0 when read.
4
WDTIRQ_EN
R/W
0 : Time out is asserted only via WDT_OUT#.
1 : Time out is asserted via IRQ and WDT_OUT#.
3:0
SELWDTIRQ[3:0]
R/W
In LPC mode , select the Serial IRQ channel.
In ISA mode , select one of six IRQ pins .
03h : use serial IRQ channel 3 in LPC mode or use ISA_IRQA in ISA
mode.
04h : use serial IRQ channel 4 in LPC mode or use ISA_IRQB in ISA
mode.
05h : use serial IRQ channel 5 in LPC mode or use ISA_IRQC in ISA
mode.
09h : use serial IRQ channel 9 in LPC mode or use ISA_IRQD in ISA
mode.
0Ah : use serial IRQ channel 10 in LPC mode or use ISA_IRQE in
ISA mode.
0Bh : use serial IRQ channel 11 in LPC mode or use ISA_IRQF in
ISA mode.
Otherwise will disable the interrupt.
6.10.5 Timer Status and Control Register – index F0h
Power-on default [7:0] = 0x02h when DTR3#/PS_WDT is pull-up , else 0x00h.
Bit
Name
R/W
Description
7:3
Reserved
R/W
Return 0 when read.
2:1
WDT_UNIT[1:0]
R/W
00 : Timer Unit is 10ms.
01 : Timer Unit is 1 second
10 : Timer Unit is 1 minute.
11 : reserved.
0
WDT_EVENT
R/W
When read
0 : no time out occur.
1 : time out has occurred.
when write
0 : no action
1 : clear the time out status.
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6.10.6 Timer Count Number Register – index F1h
Power-on default [7:0] = 0x0Ah when DTR3#/PS_WDT is pull-up, else 0x00h.
Bit
7:0
Name
WDT_CNT[7:0]
R/W
Description
R/W
The number of count for watchdog timer.
Write the same value twice to enable the timer, otherwise will disable
timer.
6.11 GPIO and PME Device Control Register (LDN 9)
6.11.1 GPIO Port 2 Control Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
7
Name
GP27_OE
R/W
R/W
Description
0 : GP27 is in input mode.
1 : GP27 is in output mode.
6
GP26_OE
R/W
0 : GP26 is in input mode.
1 : GP26 is in output mode.
5
GP25_OE
R/W
0 : GP25 is in input mode.
1 : GP25 is in output mode.
4
GP24_OE
R/W
0 : GP24 is in input mode.
1 : GP24 is in output mode.
3
GP23_OE
R/W
0 : GP23 is in input mode.
1 : GP23 is in output mode.
2
GP22_OE
R/W
0 : GP22 is in input mode.
1 : GP22 is in output mode.
1
GP21_OE
R/W
0 : GP21 is in input mode.
1 : GP21 is in output mode.
0
GP20_OE
R/W
0 : GP20 is in input mode.
1 : GP20 is in output mode.
6.11.2 GPIO Port 1 Control Register – index F1h
Power-on default [7:0] = 0x00h.
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Bit
7
Name
CLRGPOE_EN
R/W
R/W
Description
0 : GP14, GP13, GP12, GP11, GP10 is in original mode when
Watchdog timeout occurred.
1 : GP14, GP13, GP12, GP11, GP10 is reset to input mode when
Watchdog timeout occurred.
6
GP16_OE
R/W
0 : GP16 is in input mode.
1 : GP16 is in output mode.
5
GP15_OE
R/W
0 : GP15 is in input mode.
1 : GP15 is in output mode.
4
GP14_OE
R/W
0 : GP14 is in input mode.
1 : GP14 is in output mode.
3
GP13_OE
R/W
0 : GP13 is in input mode.
1 : GP13 is in output mode.
2
GP12_OE
R/W
0 : GP12 is in input mode.
1 : GP12 is in output mode.
1
GP11_OE
R/W
0 : GP11 is in input mode.
1 : GP11 is in output mode.
0
GP10_OE
R/W
0 : GP10 is in input mode.
1 : GP10 is in output mode.
6.11.3 GPIO Port 2 Output Data Control Register – index F2h
Power-on default [7:0] = 0xFFh.
Bit
7
Name
R/W
GP27_OUT
R/W
Description
0 : GP27 is output low in output mode.
1 : GP27 is tri-state.
6
GP26_OUT
R/W
0 : GP26 is output low in output mode.
1 : GP26 is tri-state.
5
GP25_OUT
R/W
0 : GP25 is output low in output mode.
1 : GP25 is tri-state.
4
GP24_OUT
R/W
0 : GP24 is output low in output mode.
1 : GP24 is tri-state.
3
GP23_OUT
R/W
0 : GP23 is output low in output mode.
1 : GP23 is tri-state.
2
GP22_OUT
R/W
0 : GP22 is output low in output mode.
1 : GP22 is tri-state.
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1
GP21_OUT
R/W
0 : GP21 is output low in output mode.
1 : GP21 is tri-state.
0
GP20_OUT
R/W
0 : GP20 is output low in output mode.
1 : GP20 is tri-state.
6.11.4 GPIO Port 1 Output Data Register – index F3h
Power-on default [7:0] = 0x7Fh.
Bit
Name
R/W
Description
7
Reserved
R/W
Return 0 when read.
6
GP16_OUT
R/W
0 : GP16 is output low in output mode.
1 : GP16 is tri-state.
5
GP15_OUT
R/W
0 : GP15 is output low in output mode.
1 : GP15 is tri-state.
4
GP14_OUT
R/W
0 : GP14 is output low in output mode.
1 : GP14 is tri-state.
3
GP13_OUT
R/W
0 : GP13 is output low in output mode.
1 : GP13 is tri-state.
2
GP12_OUT
R/W
0 : GP12 is output low in output mode.
1 : GP12 is tri-state.
1
GP11_OUT
R/W
0 : GP11 is output low in output mode.
1 : GP11 is tri-state.
0
GP10_OUT
R/W
0 : GP10 is output low in output mode.
1 : GP10 is tri-state.
6.11.5 PME Event 1 Control Register – index F4h
Power-on default [7:0] = 0x7Fh.
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Bit
7
Name
GPME27_EN
R/W
R/W
Description
0 : disable PME via GP27
1 : enable PME via GP27.
6
GPME26_EN
R/W
0 : disable PME via GP26
1 : enable PME via GP26.
5
GPME25_EN
R/W
0 : disable PME via GP25
1 : enable PME via GP25.
4
GPME24_EN
R/W
0 : disable PME via GP24
1 : enable PME via GP24.
3
GPME23_EN
R/W
0 : disable PME via GP23
1 : enable PME via GP23.
2
GPME22_EN
R/W
0 : disable PME via GP22
1 : enable PME via GP22.
1
GPME21_EN
R/W
0 : disable PME via GP21
1 : enable PME via GP21.
0
GPME20_EN
R/W
0 : disable PME via GP20
1 : enable PME via GP20.
6.11.6 PME Event 2 Control Register – index F5h
Power-on default [7:0] = 0x7Fh.
Bit
Name
R/W
Description
7
Reserved
R/W
Return 0 when read.
6
GPME16_EN
R/W
0 : disable PME via GP16
1 : enable PME via GP16.
5
GPME15_EN
R/W
0 : disable PME via GP15
1 : enable PME via GP15.
4
GPME14_EN
R/W
0 : disable PME via GP14
1 : enable PME via GP14.
3
GPME13_EN
R/W
0 : disable PME via GP13
1 : enable PME via GP13.
2
GPME12_EN
R/W
0 : disable PME via GP12
1 : enable PME via GP12.
1
GPME11_EN
R/W
0 : disable PME via GP11
1 : enable PME via GP11.
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0
GPME10_EN
R/W
0 : disable PME via GP10
1 : enable PME via GP10.
6.11.7 PME Event 3 Control Register – index F6h
Power-on default [7:0] = 0x7Fh.
Bit
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read.
5
URFPME_EN
R/W
0 : disable PME via IRQ of UART 6
1 : enable PME via IRQ of UART 6.
4
UREPME_EN
R/W
0 : disable PME via IRQ of UART 5
1 : enable PME via IRQ of UART 5.
3
URDPME_EN
R/W
0 : disable PME via IRQ of UART 4
1 : enable PME via IRQ of UART 4.
2
URCPME_EN
R/W
0 : disable PME via IRQ of UART 3
1 : enable PME via IRQ of UART 3.
1
URBPME_EN
R/W
0 : disable PME via IRQ of UART 2
1 : enable PME via IRQ of UART 2.
0
URAPME_EN
R/W
0 : disable PME via IRQ of UART 1
1 : enable PME via IRQ of UART 1.
6.11.8 GPIO Port 2 Input Status Register – index F7h
Bit
Name
R/W
Description
7
GP27_ST
R/W
Status of GP27
6
GP26_ST
R/W
Status of GP26
5
GP25_ST
R/W
Status of GP25
4
GP24_ST
R/W
Status of GP24
3
GP23_ST
R/W
Status of GP23
2
GP22_ST
R/W
Status of GP22
1
GP21_ST
R/W
Status of GP21
0
GP20_ST
R/W
Status of GP20
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6.11.9 GPIO Port 1 Input Status Register – index F8h
Bit
Name
R/W
Description
7
Reserved
R/W
Return 0 when read
6
GP16_ST
R/W
Status of GP16
5
GP15_ST
R/W
Status of GP15
4
GP14_ST
R/W
Status of GP14
3
GP13_ST
R/W
Status of GP13
2
GP12_ST
R/W
Status of GP12
1
GP11_ST
R/W
Status of GP11
0
GP10_ST
R/W
Status of GP10
6.11.10
Bit
PME Real Time Status Register – index F9h
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read
5
PME_ST_REAL3[5]
R/W
Status of UART 6 IRQ.
4
PME_ST_REAL3[4]
R/W
Status of UART 5 IRQ.
3
PME_ST_REAL3[3]
R/W
Status of UART 4 IRQ.
2
PME_ST_REAL3[2]
R/W
Status of UART 3 IRQ.
1
PME_ST_REAL3[1]
R/W
Status of UART 2 IRQ.
0
PME_ST_REAL3[0]
R/W
Status of UART 1 IRQ.
6.11.11 PME Edge Status 1 Register – index FAh
Power on default = 0x00h
Bit
7
Name
PME_ST_EDGE1[7]
R/W
R/W
Description
0 : No transition at GP27
1 : A high to low transition at GP27 in input mode.
6
PME_ST_EDGE1[6]
R/W
0 : No transition at GP26
1 : A high to low transition at GP26 in input mode.
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5
PME_ST_EDGE1[5]
R/W
0 : No transition at GP25
1 : A high to low transition at GP25 in input mode.
4
PME_ST_EDGE1[4]
R/W
0 : No transition at GP24
1 : A high to low transition at GP24 in input mode.
3
PME_ST_EDGE1[3]
R/W
0 : No transition at GP23
1 : A high to low transition at GP23 in input mode.
2
PME_ST_EDGE1[2]
R/W
0 : No transition at GP22
1 : A high to low transition at GP22 in input mode.
1
PME_ST_EDGE1[1]
R/W
0 : No transition at GP21
1 : A high to low transition at GP21 in input mode.
0
PME_ST_EDGE1[0]
R/W
0 : No transition at GP20
1 : A high to low transition at GP20 in input mode.
6.11.12
PME Edge Status 2 Register – index FBh
Power on default = 0x00h
Bit
Name
R/W
Description
7
Reserved
R/W
Return 0 when read.
6
PME_ST_EDGE2[6]
R/W
0 : No transition at GP16
1 : A high to low transition at GP16 in input mode.
5
PME_ST_EDGE2[5]
R/W
0 : No transition at GP15
1 : A high to low transition at GP15 in input mode.
4
PME_ST_EDGE2[4]
R/W
0 : No transition at GP14
1 : A high to low transition at GP14 in input mode.
3
PME_ST_EDGE2[3]
R/W
0 : No transition at GP13
1 : A high to low transition at GP13 in input mode.
2
PME_ST_EDGE2[2]
R/W
0 : No transition at GP12
1 : A high to low transition at GP12 in input mode.
1
PME_ST_EDGE2[1]
R/W
0 : No transition at GP11
1 : A high to low transition at GP11 in input mode.
0
PME_ST_EDGE2[0]
R/W
0 : No transition at GP10
1 : A high to low transition at GP10 in input mode.
6.11.13
PME Edge Status 3 Register – index FCh
Power on default = 0x00h
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Bit
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read.
5
PME_ST_EDGE3[5]
R/W
0 : No transition at UART 6 IRQ
1 : A low to high transition at UART 6 IRQ.
4
PME_ST_EDGE3[4]
R/W
0 : No transition at UART 5 IRQ
1 : A low to high transition at UART 5 IRQ.
3
PME_ST_EDGE3[3]
R/W
0 : No transition at UART 4 IRQ
1 : A low to high transition at UART 4 IRQ.
2
PME_ST_EDGE3[2]
R/W
0 : No transition at UART 3 IRQ
1
PME_ST_EDGE3[1]
R/W
0 : No transition at UART 2 IRQ
1 : A low to high transition at UART 3 IRQ.
1 : A low to high transition at UART 2 IRQ.
0
PME_ST_EDGE3[0]
R/W
0 : No transition at UART 1 IRQ
1 : A low to high transition at UART 1 IRQ.
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7. Electron Characteristic
7.1
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Power Supply Voltage
-0.5 to 4.0
V
Input Voltage
-0.5 to 5.5
V
Operating Temperature
0 to +70
°C
Storage Temperature
-55 to +150
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the
life and reliability of the device.
7.2
DC Characteristics
((Ta = 0° C to 70° C, VDD = 3.3V ± 10%, VSS = 0V)
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA
Input Low Voltage
VIL
0.8
Input High Voltage
VIH
2.0
Output Low Current
IOL
10
Output High Current
IOH
Input High Leakage
Input Low Leakage
V
V
12
mA
VOL = 0.4V
-10
mA
VOH = 2.4V
ILIH
+10
µA
VIN = VDD
ILIL
-10
µA
VIN = 0V
-12
I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level
input
Input Low Threshold Voltage
Vt-
0.5
0.8
Input High Threshold Voltage
Vt+
1.6
2.0
Output Low Current
IOL
10
12
Output High Current
IOH
V
VDD = 3.3 V
V
VDD = 3.3 V
mA
VOL = 0.4 V
-10
mA
VOH = 2.4V
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0V
-12
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7.2 DC Characteristics, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
mA
VOL = 0.4V
mA
VOH = 2.4V
mA
VOL = 0.4V
mA
VOL = 0.4V
OUT12t - TTL level output pin with source-sink capability of 12 mA
Output Low Current
IOL
Output High Current
IOH
12
16
-14
-12
OD8 - Open-drain output pin with sink capability of 8 mA
Output Low Current
IOL
6
8
OD16 - Open-drain output pin with sink capability of 16 mA
Output Low Current
IOL
12
16
I/OOD16ts - TTL level bi-directional pin, can select to OD or OUT by register, with 16 mA
source-sink capability
Input Low Threshold Voltage
Vt-
0.5
0.8
1.1
V
VDD = 3.3 V
Input High Threshold Voltage
Vt+
1.6
2.0
2.4
V
VDD = 3.3 V
Output Low Current
IOL
6
8
mA
VOL = 0.4 V
Output High Current
IOH
-12
mA
VOH = 2.4V
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0V
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0 V
-16
INt - TTL level input pin
2.0
V
INts - TTL level Schmitt-triggered input pin
Input Low Threshold Voltage
Vt-
0.5
0.8
1.1
V
VDD = 3.3V
Input High Threshold Voltage
Vt+
1.6
2.0
2.4
V
VDD = 3.3V
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0 V
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7.3
AC Timing Characteristics
ISA Interface – IOR#
ADDR
DATA
ISA_CS#
thold
trdata
ISA_IOR#
ISA Interface – IOW#
ADDR
DATA
ISA_CS#
ISA_IOW#
Internal ADDR
Internal DATA
twrdel
Internal WR
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Recovery Time
ADDR
DATA
CS#
ISA_IOW#
trecovery
ISA_IOR#
Name
trdata
thold
twrdel
trecovery
Description
Min.
Typ.
Max.
The time from the IOR# falling edge to data valid.
52ns
-
124ns
The time from the IOR# rising edge to data invalid.
2ns
52ns
The time from the IOW# rising edge to the data written to registers.
84ns
126ns
The time from the end of IOW# to the next IOW# (or IOR#)
126ns
Note: In normal ISA W/R cycle. ISA_IOW# and ISA_IOR# are embraced in ISA_CS# as the wave forms show.
When it is not the case, the reference point of the timing would be changed to the latest falling edge and the
first rising edge.
8. Ordering Information
Part Number
Package Type
Production Flow
F81218D
100-LQFP (Normal)
Commercial, 0°C to +70°C
F81218DG
100-LQFP (Green Package)
Commercial, 0°C to +70°C
-54-
August, 2007
V0.33P
F81218
9. Package Dimensions
100pin-LQFP
Feature Integration Technology Inc.
Headquarters
Taipei Office
3F-7, No 36, Tai Yuan St.,
Bldg. K4, 7F, No.700, Chung Cheng Rd.,
Chupei City, Hsinchu, Taiwan 302, R.O.C.
Chungho City, Taipei, Taiwan 235, R.O.C.
TEL : 886-3-5600168
TEL : 866-2-8227-8027
FAX : 886-3-5600166
FAX : 866-2-8227-8037
www: http://www.fintek.com.tw
Please note that all datasheet and specifications are subject to change without notice. All the trade
marks of products and companies mentioned in this datasheet belong to their respective owner
-55-
August, 2007
V0.33P
F81218
10. Application Circuit
(Power On Setting Pin)
PIN_73
PIN_74
PIN_86
VCC3V
PCIRST#
PME#
WDT_OUT#
LAD3
LAD2
LAD1
LAD0
PCICLK
LFRAME#
SERIRQ
CLK24IN
R14
R15
8.2K
4.7K
VSB3V
R16
10K
DTR3#
RTS3#
DSR3#
CTS3#
GP14
GP15
GP16
RI4#
DCD4#
SOUT4
SIN4
DTR4#
RTS4#
DSR4#
CTS4#
RI6#
DCD6#
SOUT6
SIN6
DTR6#
RTS6#
DSR6#
CTS6#
CLKIN
D0
F81218D
PCIRST#
PME#
WDT_OUT#
A3
A2
A1
A0
IOR#
IOW#
GND
LAD3
LAD2
LAD1
LAD0
PCICLK
LFRAME#
SERIRQ
VCC
D7
D6
D5
D4
D3
D2
D1
PIN_83
PIN_84
SOUT2
DCD2#
RI2#
IRRX2
IRTX2
CTS1#
DSR1#
RTS1#
DTR1#
SIN1
SOUT1
DCD1#
RI1#
IRRX1
IRTX1
GP25
GP24
GP23
GP22
GP21
GP20
ADD_DEC0#
ADD_DEC1#
IRQA
IRQB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CTS1#
DSR1#
RTS1#
DTR1#
SIN1
SOUT1
DCD1#
RI1#
IRRX
IRTX
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SIN2
DTR2#
RTS2#
DSR2#
CTS2#
RI5#
DCD5#
VCC
SOUT5
SIN5
DTR5#
RTS5#
DSR5#
CTS5#
GND
GP26
GP27
GP10
GP11
GP12
GP13
RI3#
DCD3#
SOUT3
SIN3
U1
PIN_76
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
PIN_49
PIN_50
PIN_52
PIN_67
PIN_73
PIN_74
PIN_76
PIN_83
PIN_84
PIN_86
R2
4.7K
PIN_52
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CTS2#
DSR2#
RTS2#
DTR2#
SIN2
SOUT2
DCD2#
RI2#
R1
PIN_41
PIN_67
C1
0.1U
PIN_39
RI5#
DCD5#
SOUT5
SIN5
DTR5#
RTS5#
DSR5#
CTS5#
PIN_33
VCC3V
VCC3V
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PIN_50
PIN_49
PIN_41
PIN_39
PIN_33
RI3#
DCD3#
SOUT3
SIN3
DTR3#
RTS3#
DSR3#
CTS3#
R1 on: UART 6 addr:0x238 IRQ11/F;
off:UART 6 disabled.
R7 on: UART 5 addr:0x338 IRQ10/E;
off:UART 5 disabled.
R3 on: UART 4 addr:0x2e8 IRQ9; off:UART 4 disabled.
R6 on: UART 3 addr:0x3e8 IRQ5; off:UART 3 disabled.
R10 on : UART 2 addr:0x2f8 irq4; R9 on and R10 off: UART 2 addr:0x2e0 IRQ4;
R9 off and R10 off:UART 2 disabled.
R13 on : UART 1 addr:0x3f8 irq3; R12 on and R13 off: UART 1 addr:0x3e0 IRQ3;
R12 off and R13 off:UART 1 disabled.
RI4#
DCD4#
SOUT4
SIN4
DTR4#
RTS4#
DSR4#
CTS4#
RI6#
DCD6#
SOUT6
SIN6
DTR6#
RTS6#
DSR6#
CTS6#
R5 on: Watch Dog Timer enabled and setting to 10 second when the clock input
is 24Mhz. If the clock input is 48Mhz , the timer is setting to 5 second.
off :disabled.
R2 On:LPC interface; Off:ISA intreface
R8
R4
R11
Address
0
0
0
0x4e/0x4f
Entry Key
0x77
0
0
1
0x2e/0x2f
0x77
0
1
0
0x4e/0x4f
0xa0
0
1
1
0x2e/0x2f
0xa0
1
0
0
0x4e/0x4f
0x87
1
0
1
0x2e/0x2f
0x87
1
1
0
0x4e/0x4f
0x67
1
1
1
0x2e/0x2f
0x67
On:1
Off:0
VCC3V
VCC3V
C2
0.1U
Title
Feature Integration Technology Inc.
Size
B
Date:
-54-
Document Number
F81218D f or LPC
Tuesday , September 16, 2003
Rev
0.2
Sheet
1
of
2
August, 2007
V0.33P
F81218
U2
VCC5V
RTS1#
DTR1#
C3
0.1USOUT1
RI1#
CTS1#
DSR1#
SIN1
DCD1#
20
16
15
13
19
18
17
14
12
11
U3
VCC
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
1
5
6
8
2
3
4
7
9
10
+12V
VCC5V
RTS1
DTR1
SOUT1RI1
CTS1
DSR1
SIN1DCD1
P1
RI1
DTR1
CTS1
SOUT1RTS1
SIN1DSR1
DCD1
-12V
5
9
4
8
3
7
2
6
1
RTS4#
DTR4#
SOUT4
RI4#
C4
0.1U CTS4#
DSR4#
SIN4
DCD4#
20
16
15
13
19
18
17
14
12
11
DB9
RS232
(SOP20)
20
16
15
13
19
18
17
14
12
11
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
1
5
6
8
2
3
4
7
9
10
+12V
VCC5V
RTS2
DTR2
SOUT2RI2
CTS2
DSR2
SIN2DCD2
P3
RI2
DTR2
CTS2
SOUT2RTS2
SIN2DSR2
DCD2
-12V
5
9
4
8
3
7
2
6
1
RTS5#
DTR5#
SOUT5
C6
0.1U RI5#
CTS5#
DSR5#
SIN5
DCD5#
20
16
15
13
19
18
17
14
12
11
DB9
20
16
15
13
19
18
17
14
12
11
-12V
5
6
8
2
3
4
7
9
10
+12V
RTS4
DTR4
SOUT4RI4
CTS4
DSR4
SIN4DCD4
P2
RI4
DTR4
CTS4
SOUT4RTS4
SIN4DSR4
DCD4
-12V
5
9
4
8
3
7
2
6
1
DB9
(UART4)
VCC
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
1
5
6
8
2
3
4
7
9
10
+12V
RTS5
DTR5
SOUT5RI5
CTS5
DSR5
SIN5DCD5
P4
RI5
DTR5
CTS5
SOUT5RTS5
SIN5DSR5
DCD5
-12V
5
9
4
8
3
7
2
6
1
DB9
(UART5)
U7
VCC
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
RS232
(SOP20)
GND
1
RS232
(SOP20)
(UART2)
U6
VCC5V
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
U5
VCC
RS232
(SOP20)
RTS3#
DTR3#
SOUT3
C7
0.1U RI3#
CTS3#
DSR3#
SIN3
DCD3#
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
RS232
(SOP20)
(UART1)
U4
VCC5V
RTS2#
DTR2#
SOUT2
C5
0.1U RI2#
CTS2#
DSR2#
SIN2
DCD2#
VCC
1
5
6
8
2
3
4
7
9
10
+12V
VCC5V
RTS3
DTR3
SOUT3RI3
CTS3
DSR3
SIN3DCD3
P5
RI3
DTR3
CTS3
SOUT3RTS3
SIN3DSR3
DCD3
-12V
5
9
4
8
3
7
2
6
1
RTS6#
DTR6#
SOUT6
RI6#
C8
0.1U CTS6#
DSR6#
SIN6
DCD6#
20
16
15
13
19
18
17
14
12
11
DB9
VCC
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
RS232
(SOP20)
(UART3)
1
5
6
8
2
3
4
7
9
10
+12V
RTS6
DTR6
SOUT6RI6
CTS6
DSR6
SIN6DCD6
P6
RI6
DTR6
CTS6
SOUT6RTS6
SIN6DSR6
DCD6
-12V
5
9
4
8
3
7
2
6
1
DB9
(UART6)
VCC3V
JP1
1
2
3
4
5
IRRX
IRTX
C9
HEADER 5
0.1U
Title
Feature Integration Technology Inc.
(IrDA)
Size
B
Date:
-55-
Document Number
UART and IrDA
Tuesday , September 16, 2003
Rev
0.2
Sheet
1
of
2
August, 2007
V0.33P
F81218
(Power On Setting Pin)
PIN_73
PIN_74
PIN_86
SA15
SA14
SA13
SA12
SA11
IRQ3
IRQ4
VCC3V
R15
VSB3V
R16
10K
DTR3#
RTS3#
DSR3#
CTS3#
GP14
IRQE
IRQF
RI4#
DCD4#
SOUT4
SIN4
DTR4#
RTS4#
DSR4#
CTS4#
RI6#
DCD6#
SOUT6
SIN6
DTR6#
RTS6#
DSR6#
CTS6#
CLKIN
ISA_D0
F81218D
PCIRST#
PME#
WDT_OUT#
ISA_A3
ISA_A2
ISA_A1
ISA_A0
IOR#
IOW#
GND
ISA_A10
ISA_A9
ISA_A8
ISA_A7
ISA_A6
ISA_A5
ISA_A4
VCC
ISA_D7
ISA_D6
ISA_D5
ISA_D4
ISA_D3
ISA_D2
ISA_D1
PIN_83
PIN_84
SOUT2
DCD2#
RI2#
IRRX2
IRTX2
CTS1#
DSR1#
RTS1#
DTR1#
SIN1
SOUT1
DCD1#
RI1#
IRRX1
IRTX1
ISA_CS#
ISA_A15
ISA_A14
ISA_A13
ISA_A12
ISA_A11
ADD_DEC0#
ADD_DEC1#
IRQA
IRQB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CTS1#
DSR1#
RTS1#
DTR1#
SIN1
SOUT1
DCD1#
RI1#
IRRX
IRTX
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SIN2
DTR2#
RTS2#
DSR2#
CTS2#
RI5#
DCD5#
VCC
SOUT5
SIN5
DTR5#
RTS5#
DSR5#
CTS5#
GND
IRQC
IRQD
GP10
GP11
GP12
GP13
RI3#
DCD3#
SOUT3
SIN3
U10
PIN_76
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
PIN_49
PIN_50
PIN_52
PIN_67
PIN_73
PIN_74
PIN_76
PIN_83
PIN_84
PIN_86
R3
4.7K
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PIN_50
PIN_49
RI3#
DCD3#
SOUT3
SIN3
DTR3#
RTS3#
DSR3#
CTS3#
IRQ10
IRQ11
PIN_41
PIN_39
PIN_33
RI4#
DCD4#
SOUT4
SIN4
DTR4#
RTS4#
DSR4#
CTS4#
RI6#
DCD6#
SOUT6
SIN6
DTR6#
RTS6#
DSR6#
CTS6#
SD0
R1 on: UART 6 addr:0x238 IRQ11/F;
off:UART 6 disabled.
R7 on: UART 5 addr:0x338 IRQ10/E;
off:UART 5 disabled.
R3 on: UART 4 addr:0x2e8 IRQ9; off:UART 4 disabled.
R6 on: UART 3 addr:0x3e8 IRQ5; off:UART 3 disabled.
R10 on : UART 2 addr:0x2f8 irq4; R9 on and R10 off: UART 2 addr:0x2e0 IRQ4;
R9 off and R10 off:UART 2 disabled.
R13 on : UART 1 addr:0x3f8 irq3; R12 on and R13 off: UART 1 addr:0x3e0 IRQ3;
R12 off and R13 off:UART 1 disabled.
R5 on: Watch Dog Timer enabled and setting to 10 second when the clock input
is 24Mhz. If the clock input is 48Mhz , the timer is setting to 5 second.
off :disabled.
R2 On:LPC interface; Off:ISA intreface
R8
R4
R11
Address
Entry Key
On:1
0
0
0
0x4e/0x4f
0x77
Off:0
0
0
1
0x2e/0x2f
0x77
0
1
0
0x4e/0x4f
0xa0
VCC3V
VCC3V
4.7K
PCIRST#
PME#
WDT_OUT#
SA3
SA2
SA1
SA0
IOR#
IOW#
SA10
SA9
SA8
SA7
SA6
SA5
SA4
CLK24IN
R2
4.7K
PIN_52
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CTS2#
DSR2#
RTS2#
DTR2#
SIN2
SOUT2
DCD2#
RI2#
R1
PIN_41
C1
0.1U
VCC3V
PIN_39
VCC3V
PIN_33
RI5#
DCD5#
SOUT5
SIN5
DTR5#
RTS5#
DSR5#
CTS5#
IRQ5
IRQ9
PIN_67
C2
0.1U
SD1
SD2
SD3
SD4
SD5
SD6
SD7
0
1
1
0x2e/0x2f
0xa0
1
0
0
0x4e/0x4f
0x87
1
0
1
0x2e/0x2f
0x87
1
1
0
0x4e/0x4f
0x67
1
1
1
0x2e/0x2f
0x67
Title
Feature Integration Technology Inc.
Size
B
Date:
-56-
Document Number
F81218D f or ISA
Tuesday , January 06, 2004
Rev
0.2
Sheet
1
of
2
August, 2007
V0.33P
F81218
U2
VCC5V
RTS1#
DTR1#
C3
0.1USOUT1
RI1#
CTS1#
DSR1#
SIN1
DCD1#
20
16
15
13
19
18
17
14
12
11
U3
VCC
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
1
5
6
8
2
3
4
7
9
10
+12V
VCC5V
RTS1
DTR1
SOUT1RI1
CTS1
DSR1
SIN1DCD1
P1
RI1
DTR1
CTS1
SOUT1RTS1
SIN1DSR1
DCD1
-12V
RTS4#
DTR4#
SOUT4
RI4#
C4
0.1U CTS4#
DSR4#
SIN4
DCD4#
5
9
4
8
3
7
2
6
1
20
16
15
13
19
18
17
14
12
11
DB9
RS232
(SOP20)
20
16
15
13
19
18
17
14
12
11
VCC
(UART1)
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
1
5
6
8
2
3
4
7
9
10
+12V
VCC5V
RTS2
DTR2
SOUT2RI2
CTS2
DSR2
SIN2DCD2
P3
RI2
DTR2
CTS2
SOUT2RTS2
SIN2DSR2
DCD2
-12V
RTS5#
DTR5#
SOUT5
C6
0.1U RI5#
CTS5#
DSR5#
SIN5
DCD5#
5
9
4
8
3
7
2
6
1
20
16
15
13
19
18
17
14
12
11
DB9
RTS3#
DTR3#
SOUT3
C7
0.1U RI3#
CTS3#
DSR3#
SIN3
DCD3#
16
15
13
19
18
17
14
12
11
VCC
(UART2)
-12V
5
6
8
2
3
4
7
9
10
+12V
RTS4
DTR4
SOUT4RI4
CTS4
DSR4
SIN4DCD4
P2
RI4
DTR4
CTS4
SOUT4RTS4
SIN4DSR4
DCD4
-12V
5
9
4
8
3
7
2
6
1
DB9
(UART4)
VCC
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
1
5
6
8
2
3
4
7
9
10
+12V
RTS5
DTR5
SOUT5RI5
CTS5
DSR5
SIN5DCD5
P4
RI5
DTR5
CTS5
SOUT5RTS5
SIN5DSR5
DCD5
-12V
5
9
4
8
3
7
2
6
1
DB9
(UART5)
U7
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
RS232
(SOP20)
GND
1
RS232
(SOP20)
U6
20
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
U5
+12V
RS232
(SOP20)
VCC5V
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
RS232
(SOP20)
U4
VCC5V
RTS2#
DTR2#
SOUT2
C5
0.1U RI2#
CTS2#
DSR2#
SIN2
DCD2#
VCC
1
5
6
8
2
3
4
7
9
10
+12V
VCC5V
RTS3
DTR3
SOUT3RI3
CTS3
DSR3
SIN3DCD3
P5
RI3
DTR3
CTS3
SOUT3RTS3
SIN3DSR3
DCD3
-12V
RTS6#
DTR6#
SOUT6
RI6#
C8
0.1U CTS6#
DSR6#
SIN6
DCD6#
5
9
4
8
3
7
2
6
1
20
16
15
13
19
18
17
14
12
11
DB9
VCC
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
RS232
(SOP20)
(UART3)
1
5
6
8
2
3
4
7
9
10
+12V
RTS6
DTR6
SOUT6RI6
CTS6
DSR6
SIN6DCD6
P6
RI6
DTR6
CTS6
SOUT6RTS6
SIN6DSR6
DCD6
-12V
5
9
4
8
3
7
2
6
1
DB9
(UART6)
VCC3V
JP1
1
2
3
4
5
IRRX
IRTX
C9
HEADER 5
0.1U
Title
Feature Integration Technology Inc.
(IrDA)
Size
B
Date:
-57-
Document Number
UART and IrDA
Tuesday , September 16, 2003
Rev
0.2
Sheet
2
of
2
August, 2007
V0.33P