FREESCALE 68HC05P9A

CT
OR
, IN
C.2
006
Freescale Semiconductor, Inc.
68HC05P9A
SPECIFICATION
ON
DU
Freescale Semiconductor, Inc...
(General Release)
LE
SE
MIC
 December 18, 1995
AR
CH
IVE
DB
YF
RE
ES
CA
CSIC MCU Design Group
Oak Hill, Texas
For More Information On This Product,
Go to: www.freescale.com
HC05P9AGRS/D
REV 2.0
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Section
Title
CT
OR
, IN
C.2
006
TABLE OF CONTENTS
Page
MIC
ON
DU
Features .......................................................................................................... 1-1
Mask Options .................................................................................................. 1-2
MCU Structure ................................................................................................ 1-3
Pin Assignments ............................................................................................. 1-4
Signal Description ........................................................................................... 1-4
VDD and VSS ............................................................................................... 1-4
IRQ ............................................................................................................. 1-4
OSC1 and OSC2 ........................................................................................ 1-5
RESET ........................................................................................................ 1-5
TCMP .......................................................................................................... 1-5
PA0 through PA7 ........................................................................................ 1-5
SDO/PB5, SDI/PB6, and SCK/PB7 ............................................................ 1-6
PC0 through PC7 ........................................................................................ 1-6
PD5 and TCAP/PD7 ................................................................................... 1-6
Input/Output Programming .............................................................................. 1-6
SE
1.1
1.2
1.3
1.4
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
1.6
CA
ROM ................................................................................................................ 2-3
ROM Security Feature .................................................................................... 2-3
RAM ................................................................................................................ 2-3
ES
2.1
2.2
2.3
LE
SECTION 2
MEMORY
IVE
DB
YF
Accumulator (A) .............................................................................................. 3-1
Index Register (X) ........................................................................................... 3-1
Condition Code Register (CCR) ...................................................................... 3-1
H — Half Carry ........................................................................................... 3-1
I — Interrupt ................................................................................................ 3-2
N — Negative ............................................................................................. 3-2
Z — Zero ..................................................................................................... 3-2
C — Carry/Borrow ...................................................................................... 3-2
Stack Pointer (SP) ........................................................................................... 3-2
Program Counter (PC) .................................................................................... 3-3
CH
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
3.5
RE
SECTION 3
CENTRAL PROCESSING UNIT
AR
Freescale Semiconductor, Inc...
SECTION 1
GENERAL DESCRIPTION
Rev. 2.0
iii
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Section
Title
CT
OR
, IN
C.2
006
TABLE OF CONTENTS
Page
SECTION 4
INTERRUPTS
Hardware Controlled Interrupt Sequence ........................................................ 4-2
Timer Interrupt ................................................................................................. 4-3
External Interrupt ............................................................................................. 4-4
Optional External Interrupts (PA0-PA7) ........................................................... 4-6
Software Interrupt (SWI) ................................................................................. 4-6
ON
Power-On Reset (POR) .................................................................................. 5-1
RESET Pin ...................................................................................................... 5-1
Computer Operating Properly (COP) Reset .................................................... 5-1
MIC
5.1
5.2
5.3
DU
SECTION 5
RESETS
SECTION 6
LOW POWER MODES
LE
SE
STOP Instruction.............................................................................................. 6-1
Stop Mode ....................................................................................................... 6-1
Halt Mode......................................................................................................... 6-2
WAIT Instruction............................................................................................... 6-2
CA
6.1
6.2
6.3
6.2
ES
SECTION 7
SIMPLE SERIAL INPUT/OUTPUT PORT
8.1
8.2
8.3
8.4
8.5
CH
IVE
DB
YF
RE
7.1
Signal Format .................................................................................................. 7-1
7.1.1
Serial Clock (SCK) ...................................................................................... 7-1
7.1.2
Serial Data Out (SDO) ................................................................................ 7-2
7.1.3
Serial Data In (SDI) ..................................................................................... 7-2
7.2
SIOP Registers ............................................................................................... 7-3
7.2.1
SIOP Control Register (SCR) ..................................................................... 7-3
7.2.2
SIOP Status Register (SSR) ....................................................................... 7-4
7.2.3
SIOP Data Register (SDR) ......................................................................... 7-5
SECTION 8
TIMER
Counter ........................................................................................................... 8-2
Output Compare Register ............................................................................... 8-3
Input Capture Register .................................................................................... 8-4
Timer Control Register (TCR) $12 .................................................................. 8-5
Timer Status Register (TSR) $13 .................................................................... 8-6
AR
Freescale Semiconductor, Inc...
4.1
4.2
4.3
4.4
4.5
MC68HC05P9A
Rev. 2.0
iv
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Section
8.6
8.7
Title
CT
OR
, IN
C.2
006
TABLE OF CONTENTS
Page
Timer During Wait Mode ................................................................................. 8-7
Timer During Stop Mode ................................................................................. 8-7
SECTION 9
COMPUTER OPERATING PROPERLY (COP)
Resetting The COP ......................................................................................... 9-1
COP During Wait Mode ................................................................................... 9-1
COP During Stop Mode .................................................................................. 9-1
MIC
ON
Conversion Process ....................................................................................... 10-1
A/D Status and Control Register (ADSCR) .................................................... 10-2
A/D Data Register (ADDR)............................................................................. 10-3
A/D Converter During Wait Mode................................................................... 10-4
A/D Converter During Stop or Halt Mode....................................................... 10-4
SE
10.1
10.2
10.3
10.4
10.5
DU
SECTION 10
ANALOG-TO-DIGITAL (A/D) CONVERTER
CA
LE
SECTION 11
SELF-CHECK MODE
ES
SECTION 12
INSTRUCTION SET
CH
IVE
DB
YF
RE
12.1 Addressing Modes ........................................................................................ 12-1
12.1.1 Inherent ..................................................................................................... 12-1
12.1.2 Immediate ................................................................................................. 12-2
12.1.3 Direct ........................................................................................................ 12-2
12.1.4 Extended ................................................................................................... 12-2
12.1.5 Indexed, No Offset .................................................................................... 12-2
12.1.6 Indexed, 8-Bit Offset ................................................................................. 12-2
12.1.7 Indexed, 16-Bit Offset ............................................................................... 12-3
12.1.8 Relative ..................................................................................................... 12-3
12.2 Instruction Types ........................................................................................... 12-4
12.2.1 Register/Memory Instructions ................................................................... 12-4
12.2.3 Read-Modify-Write Instructions ................................................................ 12-5
12.2.4 Jump/Branch Instructions ......................................................................... 12-5
12.2.5 Bit Manipulation Instructions ..................................................................... 12-7
12.2.6 Control Instructions ................................................................................... 12-7
12.3 Instruction Set Summary ............................................................................... 12-8
AR
Freescale Semiconductor, Inc...
9.1
9.2
9.3
Rev. 2.0
v
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Section
Title
CT
OR
, IN
C.2
006
TABLE OF CONTENTS
Page
SECTION 13
ELECTRICAL SPECIFICATIONS
Maximum Ratings ......................................................................................... 13-1
Thermal Characteristics ................................................................................ 13-1
DC Electrical Characteristics ......................................................................... 13-2
A/D Converter Characteristics........................................................................ 13-4
SIOP Timing................................................................................................... 13-5
Control Timing................................................................................................ 13-6
ON
28-Pin Plastic Dual In-Line Package (Case 710-02) ..................................... 14-1
28-Pin Small Outline Integrated Circuit Package (Case 751F-04) ................ 14-2
MIC
14.1
14.2
DU
SECTION 14
MECHANICAL SPECIFICATIONS
SECTION 15
ORDERING INFORMATION
LE
SE
MCU Ordering Forms .................................................................................... 15-1
Application Program Media ........................................................................... 15-2
ROM Program Verification ............................................................................ 15-3
ROM Verification Units (RVUs) ..................................................................... 15-3
CH
IVE
DB
YF
RE
ES
CA
15.1
15.2
15.3
15.4
AR
Freescale Semiconductor, Inc...
13.1
13.2
13.3
13.4
13.4
13.5
MC68HC05P9A
Rev. 2.0
vi
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Title
Page
Block Diagram ........................................................................................... 1-3
Pin Assignments ........................................................................................ 1-4
Port A Pullup Option .................................................................................. 1-5
I/O Circuitry ................................................................................................ 1-7
2-1
2-2
Memory Map .............................................................................................. 2-1
I/O Registers for the MC68HC05P9A ........................................................ 2-2
4-1
4-2
Hardware Interrupt Flowchart .................................................................... 4-3
IRQ Function Block Diagram ...................................................................... 4-4
5-1
Power-On Reset and RESET .................................................................... 5-2
6-1
STOP/WAIT Flowcharts ............................................................................. 6-3
7-1
7-2
7-3
7-4
7-5
SIOP Block Diagram .................................................................................. 7-1
Serial I/O Port Timing ................................................................................ 7-2
SIOP Control Register ............................................................................... 7-3
SIOP Status Register ................................................................................. 7-4
SIOP Data Register ................................................................................... 7-5
8-1
8-2
8-3
Timer Block Diagram ................................................................................. 8-2
Timer Control Register ............................................................................... 8-5
Timer Status Register ................................................................................ 8-6
10-1
10-2
A/D Status and Control Register (ADSCR)............................................... 10-2
A/D Data Register (ADDR) ....................................................................... 10-3
11-1
Self-Check Circuit .................................................................................... 12-2
13-1
13-2
13-3
13-4
13-5
SIOP Timing Diagram .............................................................................. 13-5
STOP Recovery Timing ........................................................................... 13-7
External Interrupt Timing ......................................................................... 13-7
Power-On Reset Timing .......................................................................... 13-8
External Reset Timing ............................................................................. 13-8
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
1-1
1-2
1-3
1-4
AR
Freescale Semiconductor, Inc...
Figure
CT
OR
, IN
C.2
006
LIST OF FIGURES
Rev. 2.0
vii
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
MC68HC05P9A
Rev. 2.0
viii
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Table
Title
CT
OR
, IN
C.2
006
LIST OF TABLES
Page
1-1
I/O Pin Functions ............................................................................................. 1-7
4-1
Vector Address for Interrupts and Reset ......................................................... 4-2
10-1 A/D Input Selection ........................................................................................ 10-3
Register/Memory Instructions ....................................................................... 12-4
Read-Modify-Write Instructions ..................................................................... 12-5
Jump and Branch Instructions ....................................................................... 12-6
Bit Manipulation Instructions ......................................................................... 12-7
Control Instructions ....................................................................................... 12-7
Instruction Set Summary ............................................................................... 12-8
Opcode Map ................................................................................................ 12-14
13-1
13-2
13-3
13-4
13-5
13-6
13-7
DC Electrical Characteristics (VDD = 5 V) ..................................................... 13-2
DC Electrical Characteristics (VDD = 3.3 V) .................................................. 13-3
A/D Converter Characeristics......................................................................... 13-4
SIOP Timing (VDD = 5 V) .............................................................................. 13-5
SIOP Timing (VDD = 3.3 V) ........................................................................... 13-5
Control Timing (VDD = 5 V) ........................................................................... 13-6
Control Timing (VDD = 3.3 V) ........................................................................ 13-6
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
12-1
12-2
12-3
12-4
12-5
12-6
12-7
AR
Freescale Semiconductor, Inc...
11-1 Self-Check Results ........................................................................................ 11-1
Rev. 2.0
ix
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
MC68HC05P9A
Rev. 2.0
x
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
MIC
Features
Low Cost
•
HC05 Core
•
28-Pin Package
•
On-Chip Oscillator with RC or Crystal/Ceramic Resonator Mask Options
•
2112 Bytes of User ROM Including 16 User Vector Locations
•
ROM Security Feature
•
128 Bytes of On-Chip RAM
•
16-Bit Timer
•
20 Bidirectional I/O Lines, One Input-Only Line
•
Mask Programmable Keyscan (Pullups and Interrupt) on Eight Port Pins
(PA0 through PA7)
•
Two Port Pins with High Current Drive Capability (PC0, PC1)
•
User Mode
•
Four-Channel 8-Bit A/D Converter
•
IVE
DB
YF
RE
ES
CA
LE
SE
•
CH
1.1
ON
DU
The MC68HC05P9A is a 28-pin device based on the MC68HC05P9. The memory
map includes 2112 bytes of user ROM and 128 bytes of RAM. The MCU has two
8-bit input/output (I/O) ports, A and C. Port B has three I/O pins and port D has
two pins, one that is I/O and the other input only. The MC68HC05P9A includes a
four-channel 8-bit analog-to-digital (A/D) converter, a simple serial I/O peripheral
(SIOP), and an on-chip mask programmable computer operating properly (COP)
watchdog circuit.
AR
Freescale Semiconductor, Inc...
SECTION 1
GENERAL DESCRIPTION
Self-Check Mode
GENERAL DESCRIPTION
Rev. 2.0
1-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Power-Saving Stop and Wait Modes
•
STOP Conversion to Halt Mode (Mask Option)
•
Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger Mask
Option
•
Simple Serial Input/Output Port
•
Mask Option Selectable Watchdog Timer (COP)
CT
OR
, IN
C.2
006
Freescale Semiconductor, Inc...
1.2
•
Mask Options
DU
There are 13 mask options on the MC68HC05P9A:
CLOCK (RC or Crystal)
•
IRQ (Edge-Sensitive Only or Edge- and Level-Sensitive)
•
SIOP (MSB or LSB First)
•
COP Watchdog Timer (Enable/Disable)
•
Keyscan Pullups and Interrupts on Port A (Enable/Disable by Pin).
•
Stop Instruction (Option to Convert to Halt)
CA
LE
SE
MIC
ON
•
NOTE
YF
RE
ES
All mask options and the user ROM are programmed on the 04E layer in
fabrication.
AR
CH
IVE
DB
Negative true signals like RESET and IRQ will be denoted with an
overline.
GENERAL DESCRIPTION
1-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
1.3
MCU Structure
CT
OR
, IN
C.2
006
Figure 1-1 shows the structure of the MC68HC05P9A.
OSC1 OSC2
TIMER
SYSTEM
PA6
PROGRAM
COUNTER
HIGH
PROGRAM
COUNTER
LOW
AN0
VRH
PC2
PC3/AN3
PC4/AN2
PC5/AN1
PC6/AN0
PORT C I/O LINES
AN1
PC1
PORT C REGISTER
AN2
PC0
PC7/VRH
ALU
CA
SERIAL
I/O PORT
(SIOP)
A/D CONVERTER
CPU
AN3
DATA DIRECTION REGISTER
DU
ON
MIC
STACK
POINTER
ES
SDO
SDI
RE
SCK
2112 X 8
USER ROM
128 X 8
RAM
240 X 8
SELFCHECK
Figure 1-1. Block Diagram
AR
CH
IVE
DB
YF
SCK/PB7
PORT B REG
SDI/PB6
DATA DIR REG
PA7
CONDITION
CODE
REGISTER
SE
PA5
INDEX
REGISTER
CPU
CONTROL
LE
PA4
ACCUMULATOR
DATA DIRECTION REGISTER
PA3
PORT A REGISTER
PORT A I/O LINES
PA1
PA2
IRQ
PORT D
REGISTER
DATA DIR
REGISTER
TCAP/PD7
PORT D I/O LINES
PD5
COP
SYSTEM
RESET
PA0
PORT B I/O LINES
Freescale Semiconductor, Inc...
TCMP
SDO/PB5
INTERNAL
PROCESSOR OSCILLATOR
AND DIVIDE
CLOCK
BY 2
GENERAL DESCRIPTION
Rev. 2.0
1-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
1.4
Pin Assignments
CT
OR
, IN
C.2
006
1
IRQ
2
PA7
3
PA6
4
PA5
5
PA4
6
PA3
7
PA2
8
PA1
9
PA0
10
SDO/PB5
11
SDI/PB6
12
SCK/PB7
13
VSS
14
28
VDD
27
26
OSC1
25
TCAP/PD7
24
TCMP
23
22
PD5
PC0
21
PC1
DU
RESET
PC2
18
PC4/AN2
17
PC5/AN1
16
PC6/AN0
15
PC7/VRH
MIC
ON
20
19
PC3/AN3
LE
SE
OSC2
Signal Description
ES
1.5
CA
Figure 1-2. Pin Assignments
YF
RE
The following paragraphs provide a description of the signals.
1.5.2 IRQ
IVE
DB
1.5.1 V
and V
DD
SS
Power is supplied to the microcontroller through VDD and VSS. VDD is the power
supply and VSS is ground.
CH
This pin has a mask option that provides two different choices of interrupt
triggering sensitivity. The IRQ pin contains an internal Schmitt trigger as part of its
input to improve noise immunity. Refer to SECTION 3 CENTRAL PROCESSING
UNIT for more detail.
AR
Freescale Semiconductor, Inc...
The MC68HC05P9A pin assignments are shown in Figure 1-2.
GENERAL DESCRIPTION
1-4
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
1.5.3 OSC1 and OSC2
CT
OR
, IN
C.2
006
These pins provide control input for an on-chip clock oscillator circuit. A crystal, a
ceramic resonator, a resistor/capacitor combination, or an external signal
connects to these pins and provides a system clock. A mask option selects either
a crystal/ceramic resonator or a resistor/capacitor as the frequency determining
element. The oscillator frequency is two times the internal bus rate.
DU
This active low pin is used to reset the MCU to a known start-up state by pulling
RESET low. The RESET pin contains an internal Schmitt trigger as part of its
input to improve noise immunity.
ON
1.5.5 TCMP
MIC
This pin provides an output for the output compare feature of the on-chip timer
system.
SE
1.5.6 PA0 through PA7
RE
ES
CA
LE
Port A is an 8-bit bidirectional port which does not share any of its pins with other
subsystems. The port A data register is at $0000, and the data direction register is
at $0004. Reset does not affect the data registers, but clears the data direction
registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the
corresponding port bit to output mode. Port A has mask option enabled pullup
devices and interrupt capability by pin. For a detailed description of I/O
programming, refer to 1.6 Input/Output Programming.
CH
IVE
PA0
VDD
Mask Option
DDR Bit
IRQ
Schmitt
Trigger
DB
YF
VDD
AR
Freescale Semiconductor, Inc...
1.5.4 RESET
Normal Port
Circuitry
To Interrupt
Logic
From all other Port A pins
Figure 1-3. Port A Pullup Option
GENERAL DESCRIPTION
Rev. 2.0
1-5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
1.5.7 SDO/PB5, SDI/PB6, and SCK/PB7
CT
OR
, IN
C.2
006
Port B is a 3-bit bidirectional port. These pins are shared with the SIOP
subsystem. Refer to SECTION 7 SIMPLE SERIAL INPUT/OUTPUT PORT for a
detailed description of the SIOP. The address of the port B data register is $0001
and the data direction register is at address $0005. Reset does not affect the data
registers, but clears the data direction registers, thereby returning the ports to
inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.
ON
DU
Port C, as an 8-bit shared function port, shares five of its pins with the A/D
converter. When the A/D converter is not enabled, PC7–PC0 form an 8-bit
general-purpose bidirectional I/O port. The contents of data direction register C
(DDRC) determine whether each pin is an input or an output.
CA
LE
SE
MIC
When the A/D converter is enabled, PC7 becomes VRH, and PC6–PC3 become
AN0–AN3 (analog inputs 0–3). The values of CH1 and CH0 in the A/D status and
control register (ADSCR) select one of the four pins as the input to the A/D
converter. When the A/D converter is enabled a digital read of port C gives a
logical zero from the selected analog input pin. A digital read of port C’s remaining
pins gives their correct digital values. VRH is the positive (high) reference voltage
for the A/D converter. VSS is the negative (low) reference voltage. A reset turns off
the A/D converter and configures port C as a general-purpose I/O port. See
SECTION 10 ANALOG-TO-DIGITAL (A/D) CONVERTER.
YF
RE
ES
The address of the port C data register is $0002 and the data direction register is
at address $0006. Reset does not affect the data registers, but clears the data
direction registers, thereby returning the ports to inputs. Writing a one to a DDR
bit sets the corresponding port bit to output mode. Two of the port C pins, PC0 and
PC1, have a higher current drive capability. See SECTION 13 ELECTRICAL
SPECIFICATIONS.
DB
1.5.9 PD5 and TCAP/PD7
CH
IVE
Port D is a 2-bit port. PD5 is I/O and TCAP/PD7 is input-only shared with the timer
input capture. The address of the port D data register is $0003 and the data
direction register is at address $0007. Reset does not affect the data registers, but
clears the data direction registers, thereby returning the ports to inputs. Writing a
one to a DDR bit sets the corresponding port bit to output mode. The TCAP/PD7
pin controls the input capture feature for the on-chip programmable timer. This pin
can be read at any time even if the TCAP function is enabled.
AR
Freescale Semiconductor, Inc...
1.5.8 PC0 through PC2, PC3/AN3, PC4/AN2, PC5/AN1, PC6/AN0, PC7/VRH
GENERAL DESCRIPTION
1-6
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
1.6
Input/Output Programming
CT
OR
, IN
C.2
006
DU
At power-on or reset, all DDRs are cleared, which configures all pins as inputs.
The data direction registers are capable of being written to or read by the
processor. During the programmed output state, a read of the data register
actually reads the value of the output data latch and not the I/O pin. For further
information, see Table 1-1 and Figure 1-4.
ON
Table 1-1. I/O Pin Functions
DDR
I/O Pin Function
0
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in an output mode. The output data latch is read.
LE
SE
MIC
R/W
ES
CA
R/W is an internal signal.
YF
RE
Data Direction
Register Bit
Latched Output
Data Bit
Output
I/O
Pin
Input
Reg
Bit
Input
I/O
CH
IVE
DB
Internal
HC05
Connections
AR
Freescale Semiconductor, Inc...
Port pins may be programmed as inputs or outputs under software control. The
direction of the pins is determined by the state of the corresponding bit in the port
data direction register (DDR). Each I/O port has an associated DDR. Any I/O
port pin is configured as an output if its corresponding DDR bit is set to a logic
one. A pin is configured as an input if its corresponding DDR bit is cleared to a
logic zero.
Figure 1-4. I/O Circuitry
GENERAL DESCRIPTION
Rev. 2.0
1-7
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
GENERAL DESCRIPTION
1-8
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
SECTION 2
MEMORY
I/O
32 Bytes
$0020
User ROM (Page Zero)
48 Bytes
$0050
Unused (48 Bytes)
DU
$0000
ON
Freescale Semiconductor, Inc...
The MC68HC05P9A has an eight Kbyte memory map, consisting of user ROM,
user RAM, self-check ROM, and I/O. See Figure 2-1 and Figure 2-2.
$0080
0000
0032
0080
0128
MIC
RAM
128 Bytes
SE
↑
0256
User ROM
2048 Bytes
RE
ES
CA
LE
$0100
Stack
64 Bytes
2304
Unused
5632 Bytes
AR
CH
IVE
DB
YF
$900
$1F00
$1FE0
$1FF0
$1FFF
Self-Check ROM
240 Bytes
Self-Check Vectors
User Vectors
16 Bytes
7936
8160
8176
8191
Figure 2-1. Memory Map
MEMORY
Rev. 2.0
2-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
7
6
CT
OR
, IN
C.2
006
DATA
ADDRESS
$0000 to $001F
5
$00 PORT A DATA
$01 PORT B DATA
$02 PORT C DATA
$03 PORT D DATA
0
$04 PORT A DDR
$05 PORT B DDR
3
2
1
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
$0A SERIAL CTRL
0
SPE
0
MSTR
0
0
0
0
$0B SERIAL STAT
SPF
DCOL
0
0
0
0
0
0
$12 TIMER CONTROL
ICIE
TOIE
0
0
0
IEDG
OLVL
$13 TIMER STATUS
ICF
OCF
TOF
0
0
0
0
0
ADRC
ADON
0
0
0
CH1
CH0
DU
0
CA
$07 PORT D DDR
$08 UNUSED
SE
$0D UNUSED
$0E UNUSED
LE
$0F UNUSED
$10 UNUSED
$11 UNUSED
$15 CAPTURE LOW
$1C UNUSED
$1D ADDR
CH
$1B DUAL TM LOW
IVE
$1A DUAL TM HIGH
DB
$17 COMPARE LOW
$19 COUNTER LOW
ES
YF
$16 COMPARE HIGH
$18 COUNTER HIGH
OCIE
RE
$14 CAPTURE HIGH
$1E ADSCR
MIC
$0C SERIAL DATA
ON
$09 UNUSED
AR
Freescale Semiconductor, Inc...
$06 PORT C DDR
4
CCF
$1F RESERVED
Figure 2-2. I/O Registers for the MC68HC05P9A
MEMORY
2-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
2.1
ROM
2.2
CT
OR
, IN
C.2
006
The user ROM consists of 48 bytes of page zero ROM from $0020 to $004F, 2048
bytes of ROM from $0100 to $08FF, and 16 bytes of user vectors from $1FF0 to
$1FFF. The self-check ROM and vectors are located from $1F00 to $1FEF.
ROM Security Feature
RAM
DU
2.3
SE
MIC
ON
The user RAM consists of 128 bytes of a shared stack area. The stack begins at
address $00FF. The stack pointer can access 64 bytes of RAM in the range
$00FF to $00C0.
NOTE
CH
IVE
DB
YF
RE
ES
CA
LE
Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking
from an interrupt or subroutine call.
AR
Freescale Semiconductor, Inc...
A security feature has been incorporated into the MC68HC05P9A to help prevent
external reading of code in the ROM. Placing unique customer code at ROM
locations $0028-$002F aids in keeping customer developed software proprietary.
MEMORY
Rev. 2.0
2-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
MEMORY
2-4
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
SECTION 3
CENTRAL PROCESSING UNIT
3.1
Accumulator (A)
ON
DU
The accumulator is a general purpose 8-bit register used to hold operands and
results of arithmetic calculations or data manipulations.
7
0
Index Register (X)
SE
3.2
MIC
A
CA
LE
The index register is an 8-bit register used for the indexed addressing value to
create an effective address. The index register also may be used as a temporary
storage area.
7
0
3.3
RE
ES
X
Condition Code Register (CCR)
CCR
H
I
N
Z
C
CH
IVE
DB
YF
The CCR is a 5-bit register in which four bits are used to indicate the results of the
instruction just executed, and the fifth bit indicates whether interrupts are masked.
These bits can be tested individually by a program, and specific actions can be
taken as a result of their state. Each bit is explained in the following paragraphs.
3.3.1 H — Half Carry
AR
Freescale Semiconductor, Inc...
This section describes the five CPU registers. CPU registers are not part of the
memory map.
This bit is set during ADD and ADC operations to indicate that a carry occurred
between bits 3 and 4.
CENTRAL PROCESSING UNIT
Rev. 2.0
3-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
3.3.2 I — Interrupt
CT
OR
, IN
C.2
006
When this bit is set, timer and external interrupts are masked (disabled). If an
interrupt occurs while this bit is set, the interrupt is latched and processed as soon
as the interrupt bit is cleared.
3.3.3 N — Negative
DU
3.3.4 Z — Zero
ON
When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation was zero.
MIC
3.3.5 C — Carry/Borrow
Stack Pointer (SP)
CA
3.4
LE
SE
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit
(ALU) occurred during the last arithmetic operation. This bit is also affected
during bit test and branch instructions and during shifts and rotates.
RE
ES
The stack pointer contains the address of the next free location on the stack.
During an MCU reset or the reset stack pointer (RSP) instruction, the stack
pointer is set to location $00FF. The stack pointer is then decremented as data is
pushed onto the stack and incremented as data is pulled from the stack.
CH
IVE
DB
YF
When accessing memory, the seven most significant bits are permanently set to
0000011. These seven bits are appended to the six least significant register bits
to produce an address within the range of $00FF to $00C0. Subroutines and
interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the
stack pointer wraps around and loses the previously stored information. A
subroutine call occupies two locations on the stack; an interrupt uses five
locations.
12
0
7
0
0
0
0
1
0
1
SP
AR
Freescale Semiconductor, Inc...
When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation was negative.
CENTRAL PROCESSING UNIT
3-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
3.5
Program Counter (PC)
CT
OR
, IN
C.2
006
The program counter is a 13-bit register that contains the address of the next byte
to be fetched.
12
0
PC
Freescale Semiconductor, Inc...
NOTE
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
The HC05 CPU core is capable of addressing a 64 Kbyte memory
map. For this implementation, however, the addressing registers
are limited to an 8 Kbyte memory map.
CENTRAL PROCESSING UNIT
Rev. 2.0
3-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
CENTRAL PROCESSING UNIT
3-4
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
SECTION 4
INTERRUPTS
ON
DU
Interrupts cause the processor to save register contents on the stack and to set
the interrupt mask (I bit) to prevent additional interrupts. The RTI instruction
causes the register contents to be recovered from the stack and normal
processing to resume.
NOTE
LE
SE
MIC
Unlike RESET, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is complete.
ES
CA
The current instruction is the one already fetched and being
operated on.
DB
YF
RE
When the current instruction is complete, the processor checks all pending
hardware interrupts. If interrupts are not masked (CCR I bit clear) and if the
corresponding interrupt enable bit is set, the processor proceeds with interrupt
processing; otherwise, the next instruction is fetched and executed.
IVE
If both an external interrupt and a timer interrupt are pending at the end of an
instruction execution, the external interrupt is serviced first. The SWI is executed
the same as any other instruction, regardless of the I-bit state.
CH
Table 4-1 lists vector addresses for all interrupts including reset.
AR
Freescale Semiconductor, Inc...
The MCU can be interrupted four different ways: the two maskable hardware
interrupts (IRQ and timer), the non-maskable software interrupt instruction (SWI),
and by the optional external asynchronous interrupt on each port A pin (enabled
by pullup mask option).
INTERRUPTS
Rev. 2.0
4-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
CT
OR
, IN
C.2
006
Flag Name
Interrupts
CPU Interrupt
Vector Address
N/A
N/A
Reset
RESET
$1FFE-$1FFF
N/A
N/A
Software
SWI
$1FFC-$1FFD
N/A
N/A
External Interrupt
IRQ
$1FFA-$1FFB
TSR
ICF
Timer Input Capture
TIMER
$1FF8-$1FF9
TSR
OCF
Timer Output Capture
TIMER
$1FF8-$1FF9
TSR
TOF
Timer Overflow
TIMER
$1FF8-$1FF9
Hardware Controlled Interrupt Sequence
DU
4.1
Register
MIC
ON
The following three functions (RESET, STOP, and WAIT) are not interrupts in the
strictest sense. However, they are acted upon in a similar manner. Flowcharts for
hardware interrupts are shown in Figure 4-1, and for STOP and WAIT in Figure 61. A discussion is provided below.
LE
SE
1. RESET — A low input on the RESET input pin causes the program to
vector to its starting address, which is specified by the contents of
memory locations $1FFE and $1FFF. The I bit in the condition code
register also is set. Much of the MCU is configured to a known state
during this type of reset as described in SECTION 5 RESETS.
ES
CA
2. STOP — The STOP instruction causes the oscillator to be turned off and
the processor to "sleep" until an external interrupt (IRQ) or reset
occurs.See 6.1.1 Stop Mode.
CH
IVE
DB
YF
RE
3. WAIT or HALT — The WAIT or HALT instruction causes all processor
clocks to stop, but leaves the timer clock running. This rest state of the
processor can be cleared by reset, an external interrupt (IRQ), or timer
interrupt. These individual interrupts have no special wait vectors. See
6.1.2 Halt Mode.
AR
Freescale Semiconductor, Inc...
Table 4-1. Vector Address for Interrupts and Reset
INTERRUPTS
4-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
CT
OR
, IN
C.2
006
From
RESET
Is
I Bit
Set
Y
N
Clear IRQ
Request
Latch
Y
DU
Freescale Semiconductor, Inc...
IRQ
External
Interrupt
Timer
Internal Interrupt
MIC
Y
N
ES
CA
LE
SE
Fetch
Next
Instruction
Execute
Instruction
ON
N
Stack
PC, X, A, CC
Set
I Bit
Load PC From:
IRQ: $1FFA-$1FFB
Timer: $1FF8-$1FF9
DB
YF
RE
Complete
Interrupt
Routine
and Execute
RTI
Timer Interrupt
CH
4.2
IVE
Figure 4-1. Hardware Interrupt Flowchart
AR
Three different timer interrupt flags cause a timer interrupt when they are set and
enabled. The interrupt flags are in the timer status register (TSR), and the enable
bits are in the timer control register (TCR). Any of these interrupts will vector to
the same interrupt service routine, located at the address specified by the
contents of memory location $1FF8 and $1FF9.
INTERRUPTS
Rev. 2.0
4-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
4.3
External Interrupt
CT
OR
, IN
C.2
006
The IRQ pin drives an asynchronous interrupt to the CPU. An edge detector flipflop is latched on the falling edge of IRQ. If either the output from the internal edge
detector flip-flops or the level on the IRQ pin is low, a request is synchronized to
the CPU to generate the IRQ interrupt. If the edge-sensitive only mask 0ption is
selected, the output of the internal edge detector flip-flop is sampled and the input
level on the IRQ pin is ignored. The interrupt service routine address is specified
by the contents of memory locations $1FFA and $1FFB. A block diagram of the
IRQ function is shown in Figure 4-2.
MIC
ON
DU
The internal interrupt latch is cleared nine PH2 clock cycles after the
interrupt is recognized (after location $1FFA is read). Therefore,
another external interrupt pulse can be latched during the IRQ
service routine.
NOTE
ES
CA
LE
SE
When the edge- and level-sensitive mask option is selected, the
voltage applied to the IRQ pin must return to the high state before
the RTI instruction in the interrupt service routine is executed to
avoid the processor re-entering the IRQ service routine.
TO BIH & BIL
INSTRUCTION
SENSING
RE
IRQ PIN
DB
YF
PA0
DDRA0
PA0 IRQ INHIBIT
(MASK OPTION)
VDD
IRQ
LATCH
R
TO IRQ
PROCESSING
IN CPU
IVE
PA7
DDRA7
PA7 IRQ INHIBIT
(MASK OPTION)
CH
RST
IRQ VECTOR FETCH
MASK OPTION
(IRQ LEVEL)
AR
Freescale Semiconductor, Inc...
NOTE
Figure 4-2. IRQ Function Block Diagram
INTERRUPTS
4-4
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
CT
OR
, IN
C.2
006
The IRQ pin is one source of an IRQ interrupt and a mask option can also enable
the port A pins (PA0 thru PA7) to act as other IRQ interrupt sources. These
sources are all combined into a single ORing function to be latched by the IRQ
latch.
1. Falling edge on the IRQ pin with all enabled port A interrupt pins at a
high level.
ON
DU
2. Falling edge on any enabled port A interrupt pin with all other enabled
port A interrupt pins and the IRQ pin at a high level.
SE
1. Low level on the IRQ pin.
MIC
If level sensitivity is chosen, the active high state of the IRQ input can also activate
an IRQ request to the CPU to generate the IRQ interrupt sequence. This makes
the IRQ interrupt sensitive to the following cases:
LE
2. Falling edge on the IRQ pin with all enabled port A interrupt pins at a
high level.
CA
3. Low level on any enabled port A interrupt pin.
ES
4. Falling edge on any enabled port A interrupt pin with all enabled port A
interrupt pins on the IRQ pin at a high level.
CH
IVE
DB
YF
RE
This interrupt is serviced by the interrupt service routine located at the address
specified by the contents of $1FFA and $1FFB. The IRQ latch is automatically
cleared by entering the interrupt service routine.
AR
Freescale Semiconductor, Inc...
Any enabled IRQ interrupt source sets the IRQ latch on the falling edge of the IRQ
pin or a port A pin if port A interrupts have been enabled. If edge-only sensitivity is
chosen by a mask option, only the IRQ latch output can activate a request to the
CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt
sensitive to the following cases:
INTERRUPTS
Rev. 2.0
4-5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
4.4
Optional External Interrupts (PA0-PA7)
CT
OR
, IN
C.2
006
The IRQ interrupt can be triggered by the inputs on the PA0 thru PA7 port pins if
enabled by individual mask options. With pullup enabled, each port A pin can
activate the IRQ interrupt function and the interrupt operation will be the same as
for inputs to the IRQ pin. Once enabled by mask option, each individual port A pin
can be disabled as an interrupt source if its corresponding DDR bit is configured
for output mode.
ON
DU
The BIH and BIL instructions apply to the output of the logic OR
function of the enabled PA0 thru PA7 interrupt pins and the IRQ pin.
The BIH and BIL instructions do not exclusively test the state of the
IRQ pin.
NOTE
Software Interrupt (SWI)
LE
4.5
SE
MIC
If enabled, the PA0 thru PA7 pins will cause an IRQ interrupt only if
these individual pins are configured as inputs.
CH
IVE
DB
YF
RE
ES
CA
The SWI is an executable instruction and a non-maskable interrupt. It is executed
regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts
enabled), SWI executes after interrupts which were pending when the SWI was
fetched but before interrupts generated after the SWI was fetched. The interrupt
service routine address is specified by the contents of memory locations $1FFC
and $1FFD.
AR
Freescale Semiconductor, Inc...
NOTE
INTERRUPTS
4-6
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
SECTION 5
RESETS
Power-On Reset (POR)
DU
5.1
MIC
ON
An internal reset is generated on power-up to allow the internal clock generator to
stabilize. The power-on reset is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage.
RESET Pin
LE
5.2
SE
There is a 4064 internal processor clock cycle (tcyc) oscillator stabilization delay
after the oscillator becomes active. If the RESET pin is low at the end of this 4064cycle delay, the MCU will remain in the reset condition until RESET goes high.
Computer Operating Properly (COP) Reset
RE
5.3
ES
CA
The MCU is reset when a logic zero is applied to the RESET input for a period of
one and one-half machine cycles (tcyc).
IVE
DB
YF
The MCU contains a watchdog timer that automatically times out if not reset
(cleared) within a specific time by a program reset sequence. If the COP
watchdog timer is allowed to time-out, an internal reset is generated to reset the
MCU. Because the internal RESET signal is used, the MCU comes out of a COP
reset in the same operating mode it was in when the COP time-out was
generated.
The COP reset function is enabled or disabled by a mask option.
CH
Refer to SECTION 9 COMPUTER OPERATING PROPERLY (COP) for more
information on the COP.
AR
Freescale Semiconductor, Inc...
The MCU can be reset three ways: by the initial power-on reset function, by an
active low input to the RESET pin, and by a computer operating properly (COP)
watchdog-timer timeout.
RESETS
Rev. 2.0
5-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
V
V
DD
OSC1
DD
VDDR
Threshold (1-2 V Typical)
2
t
OXOV
4064 t
cyc
t
cyc
1FFF
New
PC
Internal
Data
1
Bus
New
PCH
New
PCL
Op
Code
1FFE
1FFE
1FFE
ON
1FFE
MIC
Internal
Address
1
Bus
DU
Internal
1
Clock
SE
t
RESET
1FFE
1FFF
New
PC
PCH
PCL
PCL
Op
PCH
Code
RL
3
CA
LE
NOTES:
1. Internal timing signal and bus information not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
CH
IVE
DB
YF
RE
ES
Figure 5-1. Power-On Reset and RESET
AR
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
t
RESETS
5-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
STOP Instruction
MIC
6.1
ON
DU
The MC68HC05P9A is capable of running in a low-power mode in each of its
configurations. The WAIT and STOP instructions provide two modes that reduce
the power required for the MCU by stopping various internal clocks and/or the onchip oscillator. The STOP and WAIT instructions are not normally used if the COP
watchdog timer is enabled. The stop conversion mask option is used to modify the
behavior of the STOP instruction from stop mode to halt mode. The flow of the
stop, halt, and wait modes is shown in Figure 6-1.
CA
LE
SE
The STOP instruction can result in one of two modes of operation, depending on
the stop conversion mask option. If the stop conversion is not chosen, the STOP
instruction will behave like a normal STOP instruction in the MC68HC05 Family
and place the MCU in the stop mode. If the stop conversion is chosen, the STOP
instruction will behave like a WAIT instruction (with the exception of a variable
delay at startup) and place the MCU in the halt mode.
6.1.1 Stop Mode
YF
RE
ES
Execution of the STOP instruction without conversion to halt places the MCU in its
lowest power consumption mode. In the stop mode the internal oscillator is turned
off, halting all internal processing, including the COP watchdog timer. Execution
of the STOP instruction automatically clears the I bit in the condition code register
so that the IRQ external interrupt is enabled. All other registers and memory
remain unaltered. All input/output lines remain unchanged.
NOTE
CH
IVE
DB
The MCU can be brought out of the stop mode only by an IRQ external interrupt
or an externally generated RESET. When exiting the stop mode, the internal
oscillator will resume after a 4064 PH2 clock cycle oscillator stabilization delay.
Execution of the STOP instruction without conversion to halt (via
mask option) will cause the oscillator to stop, and therefore disable
the COP watchdog timer. If the COP watchdog timer is used, the
stop mode should be changed to the halt mode by selecting the
appropriate mask option.
AR
Freescale Semiconductor, Inc...
SECTION 6
LOW POWER MODES
LOW POWER MODES
Rev. 2.0
6-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
6.1.2 Halt Mode
CT
OR
, IN
C.2
006
Execution of the STOP instruction with the conversion to halt places the MCU in
this low-power mode. Halt mode consumes the same amount of power as wait
mode. (Both halt and wait modes consume more power than stop mode.)
SE
MIC
ON
DU
If the 16-bit timer interrupt is enabled, the processor will exit the halt mode and
resume normal operation. The halt mode can also be exited when an IRQ external
interrupt or external RESET occurs. When exiting the halt mode, the PH2 clock
will resume after a delay of one to 4064 PH2 clock cycles. This varied delay time
is the result of the halt mode exit circuitry testing the oscillator stabilization delay
timer (a feature of the stop mode), which has been free-running (a feature of the
wait mode).
NOTE
WAIT Instruction
ES
6.2
CA
LE
The halt mode is not intended for normal use. This feature is
provided to keep the COP watchdog timer active in the event a
STOP instruction is inadvertently executed.
IVE
DB
YF
RE
The WAIT instruction places the MCU in a low-power mode, which consumes
more power than the stop mode. In wait mode, the PH2 clock is halted,
suspending all processor and internal bus activity. Internal timer clocks remain
active, permitting interrupts to be generated from the 16-bit timer and reset to be
generated from the COP watchdog timer. Execution of the WAIT instruction
automatically clears the I bit in the condition code register enabling the IRQ
external interrupt. All other registers, memory, and input/output lines remain in
their previous state.
CH
If the 16-bit timer interrupt is enabled, it will cause the processor to exit the wait
mode and resume normal operation. The 16-bit timer may be used to generate a
periodic exit from the wait mode. The wait mode may also be exited when an IRQ
external interrupt or RESET occurs.
AR
Freescale Semiconductor, Inc...
In halt mode the PH2 clock is halted, suspending all processor and internal bus
activity. Internal timer clocks remain active, permitting interrupts to be generated
from the 16-bit timer or a reset to be generated from the COP watchdog timer.
Execution of the STOP instruction automatically clears the I bit in the condition
code register enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.
LOW POWER MODES
6-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
HALT
STOP
TO HALT
MASK
CT
OR
, IN
C.2
006
STOP
EXTERNAL OSCILLATOR ACTIVE
AND
INTERNAL TIMER CLOCK ACTIVE
Y
N
STOP INTERNAL PROCESSOR
CLOCK,
CLEAR I-BIT IN CCR
STOP INTERNAL PROCESSOR
CLOCK,
CLEAR I-BIT IN CCR
Y
IRQ
EXTERNAL
INTERRUPT?
Y
SE
Y
Y
COP
INTERNAL
RESET?
Y
Y
TIMER
INTERNAL
INTERRUPT?
N
Y
COP
INTERNAL
RESET?
N
RE
RESTART INTERNAL
PROCESSOR CLOCK
IRQ
EXTERNAL
INTERRUPT?
N
N
ES
N
Y
EXTERNAL
RESET?
N
N
CA
END OF
STABILIZATION
DELAY?
Y
N
TIMER
INTERNAL
INTERRUPT?
RESTART EXTERNAL OSCILLATOR,
RESTART STABILIZATION DELAY
LE
N
MIC
N
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I-BIT IN CCR
N
IRQ
EXTERNAL
INTERRUPT?
ON
Y
DU
Y
EXTERNAL
RESET?
EXTERNAL OSCILLATOR
ACTIVE AND
INTERNAL TIMER
CLOCK ACTIVE
Figure 6-1. STOP/WAIT Flowcharts
CH
IVE
DB
YF
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT
a. STACK
b. SET I BIT
c. VECTOR TO INTERRUPT ROUTINE
AR
Freescale Semiconductor, Inc...
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
RESET STARTUP DELAY
EXTERNAL
RESET?
WAIT
LOW POWER MODES
Rev. 2.0
6-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
LOW POWER MODES
6-4
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
SECTION 7
SIMPLE SERIAL INPUT/OUTPUT PORT
DU
RESET
MIC
ON
R Q
D
C
SE
8-BIT SHIFT REGISTER
SDO
SCK
SDI
MSB/LSB MASK OPTION
LE
DATA BUS
Signal Format
RE
7.1
ES
CA
Figure 7-1. SIOP Block Diagram
YF
The following paragraphs describe the SIOP signal format.
DB
7.1.1 Serial Clock (SCK)
CH
IVE
The state of SCK between transmissions and prior to enabling the SIOP must be
logic one. The first falling edge of SCK signals the beginning of a transmission.
At this time, the first bit of received data is accepted at the SDI pin and the first bit
of transmitted data is presented at the SDO pin. Data is captured at the SDI pin
on the rising edge of SCK. Subsequent falling edges shift the data and accept or
present the next bit. The transmission is ended upon the eighth rising edge of
SCK. The maximum frequency of SCK in slave mode is equal to E (bus clock)
divided by four. That is, for a 4-MHz oscillator input, E becomes 2 MHz and the
maximum SCK frequency is 0.5 MHz. There is no minimum SCK frequency.
AR
Freescale Semiconductor, Inc...
This device includes a simple synchronous serial I/O port. The SIOP is a three
wire master/slave system including serial clock (SCK), serial data input (SDI), and
serial data output (SDO). A mask programmable option determines whether the
SIOP is MSB or LSB first.
SIMPLE SERIAL INPUT/OUTPUT PORT
Rev. 2.0
7-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
CT
OR
, IN
C.2
006
In master mode, the format is identical except that the SCK pin is an output and
the shift clock now originates internally. The master mode transmission frequency
is fixed at E/4.
ON
DU
A mask programmable option will be included to allow data to be transmitted in
either MSB first format or LSB first format. In either case, the state of the SDO pin
always will reflect the value of the first bit received on the previous transmission if
there was one. Prior to enabling the SIOP, PB5 can be initialized to determine the
beginning state if necessary. While the SIOP is enabled, PB5 can not be used as
a standard output since that pin is coupled to the last stage of the serial shift
register. On the first falling edge of SCK, the first data bit to be shifted out is
presented to the output pin.
7.1.3 Serial Data In (SDI)
CA
LE
SE
MIC
The SDI pin becomes an input as soon as the SIOP is enabled. New data may be
presented to the SDI pin on the falling edge of SCK. Valid data must be present at
least 100 ns before the rising edge of the clock and remain valid for 100 ns after
the edge.
ES
SCK
BIT 1
RE
SDO
BIT 1
BIT 3
BIT 7
BIT 8
BIT 2
BIT 3
BIT 7
BIT 8
YF
SDI
BIT 2
CH
IVE
DB
Figure 7-2. Serial I/O Port Timing
AR
Freescale Semiconductor, Inc...
7.1.2 Serial Data Out (SDO)
SIMPLE SERIAL INPUT/OUTPUT PORT
7-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
7.2
SIOP Registers
7.2.1 SIOP Control Register (SCR)
CT
OR
, IN
C.2
006
The following paragraphs describe the SIOP registers.
$0A
0
SPE
0
MSTR
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
DU
Figure 7-3. SIOP Control Register
CA
LE
SE
MIC
ON
SPE — Serial Peripheral Enable
When set, this bit enables the serial I/O port and initializes the port B DDR such
that PB5 (SDO) is output, PB6 (SDI) is input and PB7 (SCK) is input (slave
mode only). The port B DDR can be altered subsequently as the application
requires and the port B data register (except for PB5) can be manipulated as
usual. However, these actions could affect the transmitted or received data.
When SPE is cleared, port B reverts to standard parallel I/O without affecting
the port B data register or DDR. SPE is readable and writable any time but
clearing SPE while a transmission is in progress will abort the transmission,
reset the bit counter, and return port B to its normal I/O function. Reset clears
this bit.
CH
IVE
DB
YF
RE
ES
MSTR — Master Mode
When set, this bit configures the SIOP for master mode. This means that the
transmission is initiated by a write to the data register and the SCK pin
becomes an output providing a synchronous data clock at a fixed rate of E (bus
clock) divided by four. While the device is in master mode, the SDO and SDI
pins do not change function. These pins behave exactly as they would in slave
mode. Reset clears this bit and configures the SIOP for slave operation.
MSTR may be set at any time regardless of the state of SPE. Clearing MSTR
will abort any transmission in progress.
AR
Freescale Semiconductor, Inc...
This register is located at address $000A and contains two bits.
SIMPLE SERIAL INPUT/OUTPUT PORT
Rev. 2.0
7-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
7.2.2 SIOP Status Register (SSR)
$0B
SPIF
DCOL
0
0
0
0
0
0
RESET:
CT
OR
, IN
C.2
006
This register is located at address $000B and contains only two bits.
0
0
0
0
0
0
0
0
Figure 7-4. SIOP Status Register
ON
DU
Freescale Semiconductor, Inc...
SPIF — Serial Peripheral Interface Flag
This bit is set upon occurrence of the last rising clock edge and indicates that a
data transfer has taken place. It has no effect on any further transmissions and
can be ignored without problem. SPIF is cleared by reading the SSR with SPIF
set followed by a read or write of the serial data register. If it is cleared before
the last edge of the next byte, it will be set again. Reset clears this bit.
SE
MIC
DCOL — Data Collision
This is a read-only status bit which indicates that an invalid access to the data
register has been made. This can occur any time after the first falling edge of
SCK and before SPIF is set. A read or write of the data register during this time
will result in invalid data being transmitted or received.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
DCOL is cleared by reading the status register with SPIF set followed by a read
or write of the data register. If the last part of the clearing sequence is done
after another transmission has been started, DCOL will be set again. If the
DCOL bit is set and the SPIF is not set, clearing the DCOL requires turning the
SIOP off then turning it back on. Reset also clears this bit.
SIMPLE SERIAL INPUT/OUTPUT PORT
7-4
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
7.2.3 SIOP Data Register (SDR)
CT
OR
, IN
C.2
006
This register is located at address $000C and is both the transmit and receive
data register. This system is not double buffered and any write to this register will
destroy the previous contents. The SDR can be read at any time, but if a
transmission is in progress the results may be ambiguous. Writes to the SDR
while a transmission is in progress can cause invalid data to be transmitted and/or
received. This register can be read and written only when the SIOP is enabled
(SPE=1).
$0C
U
Freescale Semiconductor, Inc...
RESET:
U
U
U
U
U
U
U
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Figure 7-5. SIOP Data Register
SIMPLE SERIAL INPUT/OUTPUT PORT
Rev. 2.0
7-5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
SIMPLE SERIAL INPUT/OUTPUT PORT
7-6
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
DU
The timer consists of a 16-bit, software-programmable counter driven by a fixed
divide-by-four prescaler. This timer can be used for many purposes, including
input waveform measurements while simultaneously generating an output
waveform. Pulse widths can vary from several microseconds to many seconds.
Refer to Figure 8-1 for a timer block diagram.
SE
MIC
ON
Each specific functional segment (capability) is represented by two registers.
These registers contain the high and low byte of that functional segment.
Generally, accessing the low byte of a specific timer function allows full control of
that function; however, an access of the high byte inhibits that specific timer
function until the low byte also is accessed.
NOTE
CH
IVE
DB
YF
RE
ES
CA
LE
The I bit in the CCR should be set while manipulating both the high
and low byte register of a specific timer function to ensure that an
interrupt does not occur.
AR
Freescale Semiconductor, Inc...
SECTION 8
TIMER
TIMER
Rev. 2.0
8-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Internal Bus
High
Byte
Internal
Processor
Clock
Low
Byte
8-Bit
Buffer
/4
High
Byte
Low
Byte
16-Bit Free
Running
Counter
$18
$19
Counter
Alternate
Register
$1A
$1B
Overflow
Detect
Circuit
Timer
Status
Reg.
MIC
ON
Output
Compare
Circuit
ICF OCF TOF $13
High Low
Byte Byte
DU
Output
Compare
Register
Input
Capture
Register
$14
$15
Edge
Detect
Circuit
Output
Level
Reg.
C
RESET
SE
Timer
Control
ICIE OCIE TOIE IEDG OLVL Reg.
$12
D Q
CLK
LE
Interrupt
Circuit
Output Edge
Level
Input
(TCMP) (TCAP)
Counter
RE
8.1
ES
CA
Figure 8-1. Timer Block Diagram
IVE
DB
YF
The key element in the programmable timer is a 16-bit, free-running counter or
counter register, preceded by a prescaler that divides the internal processor clock
by four. The prescaler gives the timer a resolution of 2.0 microseconds if the
internal bus clock is 2.0 MHz. The counter is incremented during the low portion
of the internal bus clock. Software can read the counter at any time without
affecting its value.
CH
The double-byte, free-running counter can be read from either of two locations,
$18-$19 (counter register) or $1A-$1B (counter alternate register). A read from
only the least significant byte (LSB) of the free-running counter ($19, $1B)
receives the count value at the time of the read. If a read of the free-running
counter or counter alternate register first addresses the most significant byte
(MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value
remains fixed after the first MSB read, even if the user reads the MSB several
AR
Freescale Semiconductor, Inc...
$16
$17
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
TIMER
8-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
CT
OR
, IN
C.2
006
times. This buffer is accessed when reading the free-running counter or counter
alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter alternate
register, if the MSB is read, the LSB also must be read to complete the sequence.
Output Compare Register
MIC
8.2
ON
DU
The free-running counter is configured to $FFFC during reset and is always a
read-only register. During a power-on reset, the counter is also preset to $FFFC
and begins running after the oscillator start-up delay. Because the free-running
counter is 16 bits preceded by a fixed divided-by-four prescaler, the value in the
free-running counter repeats every 262,144 internal bus clock cycles. When the
counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt can also
be enabled when counter rollover occurs by setting its interrupt enable bit (TOIE).
CA
LE
SE
The 16-bit output compare register is made up of two 8-bit registers at locations
$16 (MSB) and $17 (LSB). The output compare register is used for several
purposes, such as indicating when a period of time has elapsed. All bits are
readable and writable and are not altered by the timer hardware or reset. If the
compare function is not needed, the two bytes of the output compare register can
be used as storage locations.
DB
YF
RE
ES
The output compare register contents are compared with the contents of the freerunning counter continually, and if a match is found, the corresponding output
compare flag (OCF) bit is set and the corresponding output level (OLVL) bit is
clocked to an output level register. The output compare register values and the
output level bit should be changed after each successful comparison to establish
a new elapsed timeout. An interrupt can also accompany a successful output
compare provided the corresponding interrupt enable bit (OCIE) is set.
CH
IVE
After a processor write cycle to the output compare register containing the MSB
($16), the output compare function is inhibited until the LSB ($17) is also written.
The user must write both bytes (locations) if the MSB is written first. A write made
only to the LSB ($17) will not inhibit the compare function. The free-running
counter is updated every four internal bus clock cycles. The minimum time
required to update the output compare register is a function of the program rather
than the internal hardware.
AR
Freescale Semiconductor, Inc...
The counter alternate register differs from the counter register in one respect:
Aread of the counter register MSB can clear the timer overflow flag (TOF).
Therefore, the counter alternate register can be read at any time without the
possibility of missing timer overflow interrupts due to clearing of the TOF.
The processor can write to either byte of the output compare register without
affecting the other byte. The output level (OLVL) bit is clocked to the output level
register regardless of whether the output compare flag (OCF) is set or clear.
TIMER
Rev. 2.0
8-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8.3
Input Capture Register
CT
OR
, IN
C.2
006
Two 8-bit registers, which make up the 16-bit input capture register, are read-only
and are used to latch the value of the free-running counter after the corresponding
input capture edge detector senses a defined transition. The level transition which
triggers the counter transfer is defined by the corresponding input edge bit
(IEDG). Reset does not affect the contents of the input capture register.
Freescale Semiconductor, Inc...
The result obtained by an input capture will be one more than the value of the
free-running counter on the rising edge of the internal bus clock preceding the
external transition. This delay is required for internal synchronization. Resolution
is one count of the free-running counter, which is four internal bus clock cycles.
ON
DU
The free-running counter contents are transferred to the input capture register on
each proper signal transition regardless of whether the input capture flag (ICF) is
set or clear. The input capture register always contains the free-running counter
value that corresponds to the most recent input capture.
SE
MIC
After a read of the input capture register ($14) MSB, the counter transfer is
inhibited until the LSB ($15) is also read. This characteristic causes the time used
in the input capture software routine and its interaction with the main program to
determine the minimum pulse period.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
A read of the input capture register LSB ($15) does not inhibit the free-running
counter transfer since they occur on opposite edges of the internal bus clock.
TIMER
8-4
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8.4
Timer Control Register (TCR) $12
$12
RESET:
ICIE
OCIE
TOIE
0
0
0
0
0
CT
OR
, IN
C.2
006
The TCR is a read/write register containing five control bits. Three bits control
interrupts associated with the timer status register flags ICF, OCF, and TOF.
0
0
IEDG
OLVL
0
0
0
0
ICIE — Input Capture Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
ON
DU
OCIE — Output Compare Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
MIC
TOIE — Timer Overflow Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
ES
CA
LE
SE
IEDG — Input Edge
Value of input edge determines which level transition on TCAP pin will trigger
free-running counter transfer to the input capture register
1 = Positive edge
0 = Negative edge
Reset does not affect the IEDG bit (U=unaffected).
YF
RE
OLVL — Output Level
Value of output level is clocked into output level register by the next successful
output compare and will appear on the TCMP pin
1 = High output
0 = Low output
CH
IVE
DB
Bits 2, 3, and 4 — Not used
Always read zero
AR
Freescale Semiconductor, Inc...
Figure 8-2. Timer Control Register
TIMER
Rev. 2.0
8-5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8.5
Timer Status Register (TSR) $13
$13
RESET:
ICF
OCF
TOF
0
U
U
U
0
CT
OR
, IN
C.2
006
The TSR is a read-only register containing three status flag bits.
0
0
0
0
0
0
0
0
Figure 8-3. Timer Status Register
DU
Freescale Semiconductor, Inc...
ICF — Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture
edge detector
0 = Flag cleared when TSR and input capture low register ($15) are
accessed
MIC
ON
OCF — Output Compare Flag
1 = Flag set when output compare register contents match the freerunning counter contents
0 = Flag cleared when TSR and output compare low register ($17) are
accessed
CA
ES
Bits 0-4 — Not used
Always read zero
LE
SE
TOF — Timer Overflow Flag
1 = Flag set when free-running counter transition from $FFFF to $0000
occurs
0 = Flag cleared when TSR and counter low register ($19) are accessed
RE
Accessing the timer status register satisfies the first condition required to clear
status bits. The remaining step is to access the register corresponding to the
status bit.
DB
YF
A problem can occur when using the timer overflow function and reading the freerunning counter at random times to measure an elapsed time. Without
incorporating the proper precautions into software, the timer overflow flag could
unintentionally be cleared if:
IVE
1. The timer status register is read or written when TOF is set, and
CH
2. The LSB of the free-running counter is read but not for the purpose of
servicing the flag.
AR
The counter alternate register at address $1A and $1B contains the same value
as the free-running counter (at address $18 and $19); therefore, this alternate
register can be read at any time without affecting the timer overflow flag in the
timer status register.
TIMER
8-6
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8.6
Timer During Wait or Halt Mode
Timer During Stop Mode
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
In the stop mode, the timer stops counting and holds the last count value if stop is
exited by an interrupt. If RESET is used, the counter is forced to $FFFC. During
stop, if at least one valid input capture edge occurs at the TCAP pin, the input
capture detect circuit is armed. This does not set any timer flags wake up the
MCU, but when the MCU does wake up, there is an active input capture flag and
data from the first valid edge that occurred during the stop mode. If RESET is
used to exit stop mode, then no input capture flag or data remains, even if a valid
input capture edge occurred.
AR
Freescale Semiconductor, Inc...
8.7
CT
OR
, IN
C.2
006
The CPU clock halts during the wait or halt mode, but the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit the wait
mode.
TIMER
Rev. 2.0
8-7
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
TIMER
8-8
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
Resetting The COP
ON
9.1
DU
This device includes a watchdog COP feature as a mask option. The COP is
implemented with an 18-bit ripple counter. This provides a timeout period of 64
milliseconds at a bus rate of 2 MHz. If the COP should timeout, a system reset
will occur and the device will be re-initialized in the same fashion as a power-on
reset (POR) or external reset.
COP During Wait or Halt Mode
LE
9.2
SE
MIC
Preventing a COP reset is done by writing a zero to the COPR bit. This action will
reset the counter and begin the timeout period again. The COPR bit is bit 0 of
address $1FF0. A read of address $1FF0 will access the user-defined ROM data
at that location.
COP During Stop Mode
RE
9.3
ES
CA
The COP will continue to operate normally during wait or halt mode. The software
should pull the device out of wait or halt mode periodically and reset the COP by
writing a logic zero to the COPR bit to prevent a COP reset.
NOTE
CH
IVE
DB
YF
Stop mode disables the oscillator circuit and thereby turns the clock off for the
entire device. The COP counter will be reset when stop mode is entered. If a
reset is used to exit stop mode, the COP counter will be reset after the 4064
cycles of delay after stop mode. If an IRQ is used to exit stop mode, the COP
counter will not be reset after the 4064-cycle delay and will have that many cycles
already counted when control is returned to the program.
The halt mode is not intended for normal use. This feature is
provided to keep the COP watchdog timer active in the event a
STOP instruction is inadvertently executed.
AR
Freescale Semiconductor, Inc...
SECTION 9
COMPUTER OPERATING PROPERLY (COP)
COMPUTER OPERATING PROPERLY (COP)
Rev. 2.0
9-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
COMPUTER OPERATING PROPERLY (COP)
9-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
SECTION 10
ANALOG-TO-DIGITAL (A/D) CONVERTER
10.1
Conversion Process
ON
DU
The A/D conversion process is ratiometric, using two reference voltages, VRH and
VSS. Conversion accuracy is guaranteed only if VRH is equal to VDD.
SE
MIC
A multiplexer selects one of four analog input channels (AN3, AN2, AN1, or AN0)
for sampling. A comparator successively compares the output of an internal
digital-to-analog (D/A) converter to the sampled analog input. Control logic
changes the D/A converter input one bit at a time, starting with the most
significant bit (MSB), until the D/A converter output matches the sampled analog
input. The conversion is monotonic and has no missing codes.
ES
CA
LE
An analog input voltage equal to VRH converts to digital $FF; an input voltage
greater than VRH converts to $FF with no overflow. An analog input voltage equal
to VSS converts to digital $00. For ratiometric conversions, the source of each
analog input should use VRH as the supply voltage and be referenced to VSS.
CH
IVE
DB
YF
RE
Pins PC6–PC3 are the four inputs to the multiplexer. Each channel of conversion
takes 32 internal clock cycles, and the clock frequency must be equal to or greater
than 1 MHz. If the internal clock frequency is less than 1 MHz, the A/D internal RC
oscillator (nominally 1.5 MHz) must be used for the A/D conversion clock. Make
this selection by setting the ADRC bit in the A/D status and control register to
logical one.
AR
Freescale Semiconductor, Inc...
This section describes the four-channel, 8-bit, multiplexed input, successiveapproximation A/D converter.
ANALOG-TO-DIGITAL (A/D) CONVERTER
Rev. 2.0
10-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
10.2
A/D Status and Control Register (ADSCR)
$001E
RESET:
CCF
ADRC
ADON
0
0
0
0
0
CT
OR
, IN
C.2
006
The A/D status and control register contains a status flag and four writable control
bits.
0
0
CH1
CH0
0
0
0
0
Figure 10-1. A/D Status and Control Register (ADSCR)
MIC
ON
DU
Freescale Semiconductor, Inc...
CCF — Conversion Complete Flag
This read-only bit is automatically set when an analog-to-digital conversion is
complete, and a new result can be read from the A/D data register. CCF is
automatically cleared when a new conversion begins or when either the A/D
status and control register or the A/D data register is accessed. Writing to or
reading the A/D status and control register or the A/D data register starts a new
conversion sequence. Data from the previous conversion is overwritten
regardless of the state of the CCF bit. While CCF is a logical zero, the
requested A/D result is not yet available in the A/D data register.
DB
YF
RE
ES
CA
LE
SE
ADRC — A/D RC Oscillator Control
When the RC oscillator is turned on, it requires a time (tADRC) to stabilize, and
results can be inaccurate during this time. If the internal clock rate is above 1
MHz, the ARDC bit should be cleared.
1 = Internal RC oscillator drives A/D converter
0 = Internal clock drives A/D converter
When the internal RC oscillator is being used as the A/D converter clock, two
limitations apply:
1. Because of the frequency tolerance of the RC oscillator and its
asynchronism with the internal clock, the conversion complete flag (CCF)
must be used to determine when a conversion sequence has been
completed.
2. The conversion process runs at the nominal 1.5 MHz rate, but the
conversion results must be transferred to the A/D data register
synchronously with the internal clock; therefore, the conversion process
is limited to a maximum of one channel every internal clock cycle.
AR
CH
IVE
ADON — A/D On
When the A/D is turned on, it requires a time (tADON) for the current sources to
stabilize. During this time, results can be inaccurate.
1 = A/D converter enabled
0 = A/D converter disabled
Bits 4–2 — Not Used
These bits are not used and read logical zero out of reset. Logical zeros must
be written to these bits when writing the A/D status and control register.
ANALOG-TO-DIGITAL (A/D) CONVERTER
10-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
CH1–CH0 — Channel Select
CT
OR
, IN
C.2
006
These bits select one of the four A/D inputs (AN3, AN2, AN1, or AN0) for
conversion. Refer to Table 10-1).
Input Selected
00
AN0, Port C Bit 6
01
AN1, Port C Bit 5
10
AN2, Port C Bit 4
11
AN3, Port C Bit 3
DU
CH1:CH0
ON
To prevent excess power dissipation, do not use a port C pin as an analog input
and a digital input at the same time.
MIC
Using one of the port C pins as the A/D converter input does not affect the ability
to use the remaining port C pins as digital inputs.
A/D Data Register (ADDR)
CA
10.3
LE
SE
Performing a digital read of a port C pin that is selected as an analog input returns
a logical zero.
$001D
RE
ES
The A/D data register is a read-only register that contains the result of the most
recent A/D conversion. This register is updated each time the conversion
complete flag (CCF) is set in the A/D status and control register.
Bit 7
5
4
3
2
1
Bit 0
A/D DATA REGISTER NOT AFFECTED BY RESET
YF
RESET:
6
A/D Converter During Wait Mode
IVE
10.4
DB
Figure 10-2. A/D Data Register (ADDR)
CH
The A/D converter continues to operate normally while the MCU is in wait mode. If
the A/D converter is not being used, clear the ADON and ADRC bits in the A/D
status and control register to decrease power consumption during wait mode.
AR
Freescale Semiconductor, Inc...
Table 10-1. A/D Input Selection
ANALOG-TO-DIGITAL (A/D) CONVERTER
Rev. 2.0
10-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
10.5
A/D Converter During Stop or Halt Mode
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
Stop or halt mode disables the comparator and charge pump and aborts any
conversion in progress or pending. When the MCU leaves stop mode, the built-in
delay for oscillator startup allows enough time for the A/D circuits to stabilize.
Therefore, no software delays are needed after exiting from stop mode. When the
MCU leaves halt mode, a software delay is needed since the MCU may exit from
halt mode after only one internal clock cycle.
ANALOG-TO-DIGITAL (A/D) CONVERTER
10-4
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
SECTION 11
SELF-CHECK MODE
SE
MIC
ON
DU
The self-check mode is entered on the rising edge of RESET if the IRQ pin is
driven to double the supply voltage and the TCAP/PD7 pin is at logic one. RESET
must be held low for 4064 cycles after POR or for a time tRL for any other reset.
After reset, the I/O, RAM, ROM, timer, and SIOP are tested. Self-check results
(using LED’s as monitors) are shown in Table 11-1. It is not recommended that the
user code use any of the self-check code. The self-check code is subject to
change at any time to improve testability or manufacturability.
PC1
0
0
Bad I/O
1
0
Bad RAM
1
1
Bad Timer
0
0
Bad ROM
0
1
Bad Serial
RE
0
YF
1
Flashing
DB
REMARKS
1
ES
0
1
PC0
CA
PC2
LE
Table 11-1. Self-Check Results
All Others
Good Device
Bad Device
CH
IVE
0 indicates LED is on; 1 indicates LED is off.
AR
Freescale Semiconductor, Inc...
The self-check program resides at mask ROM locations $1F00 to $1FEF. This
program is designed to check the part’s functionality with a minimum of support
hardware. The COP subsystem is disabled in the self-check mode so that
routines that feed the COP do not exist in the self-check program.
SELF-CHECK MODE
Rev. 2.0
11-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
CT
OR
, IN
C.2
006
VDD
VTST
10 KΩ
IRQ
PA7
PA6
PA5
PA3
PA2
PA1
PA0
SDO/PB5
SDI/PB6
SCK/PB7
3
4
5
6
7
27
OSC1
26
OSC2
25
TCAP/PD7
24
TCMP
23
PD5
22
8
21
9
10 KΩ
10 MΩ
20 pF 20 pF
PC1
PC2
20
10
19
11
18
12
13
14
17
16
15
PC3
PC4
PC5
PC6
PC7
LE
CA
VDD = 5.0 V
VTST = 10.0 V
4 MHz
PC0
SE
VSS
2
VDD
470 Ω
VDD
10 KΩ
CH
IVE
DB
YF
RE
ES
Figure 11-1. Self-Check Circuit
AR
Freescale Semiconductor, Inc...
PA4
28
1
DU
1 µf
ON
RESET
MIC
4.7 KΩ
VDD
SELF-CHECK MODE
11-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
SECTION 12
INSTRUCTION SET
12.1
Addressing Modes
ON
DU
The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
execute an instruction. The eight addressing modes are the following:
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
YF
RE
ES
CA
LE
SE
MIC
•
DB
12.1.1 Inherent
CH
IVE
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry flag (SEC) and increment accumulator (INCA).
Inherent instructions require no memory address and are one byte long.
AR
Freescale Semiconductor, Inc...
This section describes the M68HC05P9A addressing modes and instruction
types.
INSTRUCTION SET
Rev. 2.0
12-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
12.1.2 Immediate
CT
OR
, IN
C.2
006
Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the first byte, and the
immediate data value is the second byte.
ON
DU
Direct instructions can access any of the first 256 memory addresses with two
bytes. The first byte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are three-byte instructions that use
direct addressing to access the operand and relative addressing to specify a
branch destination.
MIC
12.1.4 Extended
SE
Extended instructions use only three bytes to access any address in memory. The
first byte is the opcode; the second and third bytes are the high and low bytes of
the operand address.
ES
12.1.5 Indexed, No Offset
CA
LE
When using the Motorola assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.
DB
YF
RE
Indexed instructions with no offset are one-byte instructions that can access data
with variable addresses within the first 256 memory locations. The index register
contains the low byte of the conditional address of the operand. The CPU
automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
IVE
Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or I/O location.
CH
12.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are two-byte instructions that can access data
with variable addresses within the first 511 memory locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the conditional address of the operand. These instructions can access
locations $0000–$01FE.
AR
Freescale Semiconductor, Inc...
12.1.3 Direct
INSTRUCTION SET
12-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
CT
OR
, IN
C.2
006
Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the first 256 memory
locations and could extend as far as location 510 ($01FE). The k value is typically
in the index register, and the address of the beginning of the table is in the byte
following the opcode.
DU
Indexed, 16-bit offset instructions are three-byte instructions that can access data
with variable addresses at any location in memory. The CPU adds the unsigned
byte in the index register to the two unsigned bytes following the opcode. The sum
is the conditional address of the operand. The first byte after the opcode is the
high byte of the 16-bit offset; the second byte is the low byte of the offset. These
instructions can address any location in memory.
ON
Indexed, 16-bit offset instructions are useful for selecting the kth element in an
n-element table anywhere in memory.
SE
MIC
As with direct and extended addressing the Motorola assembler determines the
shortest form of indexed addressing.
12.1.8 Relative
RE
ES
CA
LE
Relative addressing is only for branch instructions. If the branch condition is true,
the CPU finds the conditional branch destination by adding the signed byte
following the opcode to the contents of the program counter. If the branch
condition is not true, the CPU goes to the next instruction. The offset is a signed,
two’s complement byte that gives a branching range of –128 to +127 bytes from
the address of the next location after the branch instruction.
CH
IVE
DB
YF
When using the Motorola assembler, the programmer does not need to calculate
the offset, because the assembler determines the proper offset and verifies that it
is within the span of the branch.
AR
Freescale Semiconductor, Inc...
12.1.7 Indexed, 16-Bit Offset
INSTRUCTION SET
Rev. 2.0
12-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
12.2
Instruction Types
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
DU
12.2.1 Register/Memory Instructions
CT
OR
, IN
C.2
006
•
MIC
ON
Most of these instructions use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in memory.
Table 12-1 lists the register/memory instructions.
SE
Table 12-1. Register/Memory Instructions
Instruction
Mnemonic
ADC
Add Memory Byte to Accumulator
ADD
CA
LE
Add Memory Byte and Carry Bit to Accumulator
AND
Bit Test Accumulator
BIT
ES
AND Memory Byte with Accumulator
RE
Compare Accumulator
CMP
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
IVE
Load Accumulator with Memory Byte
DB
YF
Compare Index Register with Memory Byte
CH
AR
Freescale Semiconductor, Inc...
The MCU instructions fall into the following five categories:
INSTRUCTION SET
12-4
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
12.2.2 Read-Modify-Write Instructions
CT
OR
, IN
C.2
006
These instructions read a memory location or a register, modify its contents, and
write the modified value back to the memory location or to the register. The test for
negative or zero instruction (TST) is an exception to the read-modify-write
sequence because it does not write a replacement value. Table 12-2 lists the
read-modify-write instructions.
Table 12-2. Read-Modify-Write Instructions
Arithmetic Shift Left
Mnemonic
ASL
ASR
DU
Arithmetic Shift Right
Clear Bit in Memory
ON
Set Bit in Memory
Clear
BCLR
BSET
CLR
COM
Decrement
DEC
Increment
INC
LSL
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST
RE
ES
LE
Logical Shift Right
CA
Logical Shift Left
SE
MIC
Complement (One’s Complement)
YF
12.2.3 Jump/Branch Instructions
CH
IVE
DB
Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump to subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is
met. If the test condition is not met, the branch is not performed. All branch
instructions use relative addressing.
Bit test and branch instructions cause a branch based on the state of any
readable bit in the first 256 memory locations. These three-byte instructions use a
combination of direct addressing and relative addressing. The direct address of
the byte to be tested is in the byte following the opcode. The third byte is the
signed offset byte. The CPU finds the conditional branch destination by adding the
AR
Freescale Semiconductor, Inc...
Instruction
INSTRUCTION SET
Rev. 2.0
12-5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
CT
OR
, IN
C.2
006
third byte to the program counter if the specified bit tests true. The bit to be tested
and its condition (set or clear) is part of the opcode. The span of branching is from
–128 to +127 from the address of the next location after the branch instruction.
The CPU also transfers the tested bit to the carry/borrow bit of the condition code
register. Table 12-3 lists the jump and branch instructions.
Table 12-3. Jump and Branch Instructions
Instruction
Mnemonic
Branch if Carry Bit Clear
BCC
Freescale Semiconductor, Inc...
Branch if Carry Bit Set
BCS
BEQ
Branch if Half-Carry Bit Clear
Branch if Higher
Branch if IRQ Pin High
SE
Branch if IRQ Pin Low
MIC
Branch if Higher or Same
ON
Branch if Half-Carry Bit Set
DU
Branch if Equal
Branch if Lower
BHCS
BHI
BHS
BIH
BIL
BLO
BLS
Branch if Interrupt Mask Clear
BMC
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
YF
RE
Branch if Minus
ES
CA
LE
Branch if Lower or Same
Branch if Bit Clear
BRCLR
BRN
DB
Branch Never
Branch if Bit Set
BRSET
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
IVE
Branch to Subroutine
AR
CH
BHCC
INSTRUCTION SET
12-6
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
12.2.4 Bit Manipulation Instructions
CT
OR
, IN
C.2
006
The CPU can set or clear any writable bit in the first 256 bytes of memory. Port
registers, port data direction registers, timer registers, and on-chip RAM locations
are in the first 256 bytes of memory. The CPU can also test and branch based on
the state of any bit in any of the first 256 memory locations. Bit manipulation
instructions use direct addressing. Table 12-4 lists these instructions.
Table 12-4. Bit Manipulation Instructions
Clear Bit
Mnemonic
BCLR
BRCLR
DU
Branch if Bit Clear
Branch if Bit Set
BRSET
BSET
MIC
ON
Set Bit
12.2.5 Control Instructions
LE
SE
These register reference instructions control CPU operation during program
execution. Control instructions, listed in Table 12-5, use inherent addressing.
Table 12-5. Control Instructions
CA
Instruction
ES
Clear Carry Bit
CLC
CLI
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
YF
No Operation
DB
IVE
CH
Mnemonic
RE
Clear Interrupt Mask
AR
Freescale Semiconductor, Inc...
Instruction
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
INSTRUCTION SET
Rev. 2.0
12-7
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
12.3
Instruction Set Summary
CT
OR
, IN
C.2
006
Table 12-6 is an alphabetical list of all M68HC05 instructions and shows the effect
of each instruction on the condition code register.
Opcode
A ← (A) + (M) + (C)
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
FB
2
3
4
5
4
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
F4
2
3
4
5
4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
↕ — ↕
↕
ON
DU
Add with Carry
A ← (A) + (M)
↕ — ↕
↕
SE
MIC
Add without Carry
A ← (A) ∧ (M)
Logical AND
— — ↕
Arithmetic Shift Left
(Same as LSL)
C
Arithmetic Shift Right
BCC rel
Branch if Carry Bit
Clear
IVE
DB
YF
RE
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
0
b7
— — ↕
↕
b0
C
b7
— — ↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — — — —
ff
ff
Cycles
Address
Mode
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
2
3
4
5
4
3
LE
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
F9
H I N Z C
CA
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
↕
IMM
DIR
EXT
IX2
IX1
IX
Effect on
CCR
Description
ES
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
5
3
3
6
5
5
3
3
6
5
Clear Bit n
BCS rel
Branch if Carry Bit
Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
CH
BCLR n opr
BEQ rel
AR
Freescale Semiconductor, Inc...
Source
Form
Operand
Table 12-6. Instruction Set Summary
INSTRUCTION SET
12-8
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Address
Mode
Opcode
Operand
Cycles
Table 12-6. Instruction Set Summary (Continued)
BHCC rel
Branch if Half-Carry
Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry
Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
BHS rel
Branch if Higher or
Same
BIH rel
BIL rel
Effect on
CCR
CT
OR
, IN
C.2
006
Description
H I N Z C
— — — — —
REL
24
rr
3
Branch if IRQ Pin
High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
Branch if IRQ Pin
Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
(A) ∧ (M)
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
F5 p
2
3
4
5
4
3
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
DU
PC ← (PC) + 2 + rel ? C = 0
MIC
Operation
Bit Test
Accumulator with
Memory Byte
BLO rel
Branch if Lower
(Same as BCS)
BLS rel
Branch if Lower or
Same
BMC rel
Branch if Interrupt
Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt
Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
BPL rel
Branch if Plus
BRA rel
Branch Always
ON
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
ES
CA
LE
SE
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
26
rr
3
— — — — —
REL
2A
rr
3
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
PC ← (PC) + 2 + rel ? Mn = 0
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
21
rr
3
YF
RE
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
CH
IVE
DB
BRCLR n opr rel Branch if bit n clear
BRSET n opr rel Branch if Bit n Set
AR
Freescale Semiconductor, Inc...
Source
Form
BRN rel
Branch Never
PC ← (PC) + 2 + rel ? 1 = 0
REL
INSTRUCTION SET
Rev. 2.0
12-9
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Operand
Cycles
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
— — — — 0
INH
98
— 0 — — —
INH
9A
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
F1
↕ 1
DIR
INH
INH
IX1
IX
33
43
53
63
73
↕ 1
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
F3
↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
F8
H I N Z C
BSR rel
Branch to
Subroutine
CLC
Clear Carry Bit
C←0
CLI
Clear Interrupt Mask
I←0
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
MIC
(A) – (M)
— — ↕
SE
— — 0 1 —
RE
YF
Compare Index
Register with
Memory Byte
Decrement Byte
EXCLUSIVE OR
Accumulator with
Memory Byte
↕
LE
CA
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
ES
Complement Byte
(One’s Complement)
DB
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
Compare
Accumulator with
Memory Byte
IVE
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
CH
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
ON
Set Bit n
DU
Mn ← 1
BSET n opr
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Effect on
CCR
CT
OR
, IN
C.2
006
Description
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
A ← (A) ⊕ (M)
— — ↕
— — ↕
— — ↕
— — ↕
↕ —
INSTRUCTION SET
12-10
For More Information On This Product,
Go to: www.freescale.com
Address
Mode
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
Operation
AR
Freescale Semiconductor, Inc...
Source
Form
Opcode
Table 12-6. Instruction Set Summary (Continued)
2
2
dd
ff
dd
ff
dd
ff
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Operand
Cycles
5
3
3
6
5
— — — — —
DIR
EXT
IX2
IX1
IX
BC
C dd
C hh ll
D ee ff
ff
C
EC
FC
2
3
4
3
2
— — — — —
DIR
EXT
IX2
IX1
IX
BD
C dd
D hh ll
D ee ff
ff
D
ED
FD
5
6
7
6
5
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
F6
2
3
4
5
4
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
2
3
4
5
4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
CT
OR
, IN
C.2
006
↕ —
DU
ON
SE
Load Accumulator
with Memory Byte
LE
A ← (M)
Load Index Register
with Memory Byte
Logical Shift Left
(Same as ASL)
MUL
Unsigned Multiply
CH
IVE
Logical Shift Right
NOP
dd
MIC
Jump to Subroutine
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
Opcode
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
CA
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
3C
4C
5C
6C
7C
— — ↕
PC ← Jump Address
Unconditional Jump
ES
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
Increment Byte
RE
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
YF
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
INH
INH
IX1
IX
Effect on
CCR
Description
H I N Z C
Negate Byte
(Two’s Complement)
AR
Freescale Semiconductor, Inc...
INC opr
INCA
INCX
INC opr,X
INC ,X
Operation
DB
Source
Form
Address
Mode
Table 12-6. Instruction Set Summary (Continued)
X ← (M)
— — ↕
C
0
b7
0
C
b7
— — ↕
↕
b0
— — 0
↕
↕
b0
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
No Operation
0 — — — 0
INH
42
— — ↕
DIR
INH
INH
IX1
IX
30
40
50
60
70
INH
9D
↕
↕
— — — — —
ff
ff
ff
5
3
3
6
5
5
3
3
6
5
11
ii
ff
5
3
3
6
5
2
INSTRUCTION SET
Rev. 2.0
12-11
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Opcode
39
49
59
69
79
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — — — —
INH
9C
2
↕ ↕
INH
80
6
↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
F2
2
3
4
5
4
3
C←1
— — — — 1
INH
99
2
I←1
— 1 — — —
INH
9B
2
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
B7 dd
C7 hh ll
D7 ee ff
E7 ff
F7
4
5
6
5
4
— 0 — — —
INH
8E
2
— — ↕
DIR
EXT
IX2
IX1
IX
BF dd
CF hh ll
DF ee ff
EF ff
FF
4
5
6
5
4
H I N Z C
Logical OR
Accumulator with
Memory
A ← (A) ∨ (M)
Rotate Byte Left
through Carry Bit
— — ↕
— — ↕
C
b7
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right
through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from
Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕
↕
MIC
SE
↕
↕
↕
LE
Set Carry Bit
SEI
Set Interrupt Mask
CA
SEC
A ← (A) – (M) – (C)
YF
Store Accumulator in
Memory
STOP
Stop Oscillator and
Enable IRQ Pin
M ← (A)
IVE
DB
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Index
Register In Memory
CH
— — ↕
b0
M ← (X)
ff
ff
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
INH
— — ↕
↕
ES
Subtract Memory
Byte and Carry Bit
from Accumulator
RE
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
ON
C
b7
↕
b0
Cycles
Address
Mode
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
FA
CT
OR
, IN
C.2
006
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
↕ —
IMM
DIR
EXT
IX2
IX1
IX
Effect on
CCR
Description
↕ —
AR
Freescale Semiconductor, Inc...
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Operation
DU
Source
Form
Operand
Table 12-6. Instruction Set Summary (Continued)
INSTRUCTION SET
12-12
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Opcode
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
F0
2
3
4
5
4
3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
10
— — — — —
INH
97
2
— — — — —
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
— — — — —
INH
9F
2
— ↕ — — —
INH
8F
2
Description
H I N Z C
Subtract Memory
Byte from
Accumulator
Software Interrupt
TAX
Transfer
Accumulator to
Index Register
— — ↕
↕
ON
DU
SWI
A ← (A) – (M)
Cycles
Address
Mode
↕
IMM
DIR
EXT
IX2
IX1
IX
Operation
TXA
Transfer Index
Register to
Accumulator
WAIT
Stop CPU Clock
and Enable
Interrupts
ES
CA
A ← (X)
IVE
DB
YF
RE
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
CH
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
(M) – $00
SE
Test Memory Byte
for Negative or Zero
LE
TST opr
TSTA
TSTX
TST opr,X
TST ,X
MIC
X ← (A)
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
dd
ff
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
AR
Freescale Semiconductor, Inc...
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Effect on
CCR
CT
OR
, IN
C.2
006
Source
Form
Operand
Table 12-6. Instruction Set Summary (Continued)
INSTRUCTION SET
Rev. 2.0
12-13
For More Information On This Product,
Go to: www.freescale.com
5
12-14
INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
BRSET0
0
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
BCLR7
DIR 2
5
BSET7
DIR 2
5
BCLR6
DIR 2
5
BSET6
DIR 2
5
BCLR5
DIR 2
5
BSET5
DIR 2
5
BCLR4
DIR 2
5
BSET4
DIR 2
5
BCLR3
DIR 2
5
BSET3
REL 2
3
BCC
REL 2
3
BLS
REL
3
BHI
REL
3
BRN
DIR 1
5
ASR
DIR 1
5
ROR
5
DIR 1
LSR
COMX
INH 1
3
ASRA
INH 1
3
RORA
3
INH 1
LSRA
INH 1
3
3
INH 2
3
ASRX
INH 2
3
RORX
3
6
5
5
DIR 1
CLR
DIR 1
TST
DIR 1
4
INC
DIR 1
DEC
DIR 1
5
ROL
DIR 1
5
3
3
INH 1
CLRA
INH 1
TSTA
INH 1
3
INCA
INH 1
DECA
INH 1
3
ROLA
INH 1
3
3
3
INH 2
CLRX
INH 2
TSTX
INH 2
3
INCX
INH 2
DECX
INH 2
3
ROLX
INH 2
3
IX1 1
6
6
IX1 1
6
IX1 1
IX1 1
5
CLR
TST
INC
IX1 1
DEC
IX1 1
6
ROL
ASR
5
5
IX
5
1
IX 1
5
IX
IX
4
5
IX
IX
5
10
1
TAX
1
INH 1
WAIT
INH
2
STOP
2
1
1
1
1
1
INH
2
2
INH
TXA
2
2
MSB
3
IX2 2
5
IX2 2
6
IX2 2
5
EXT 3
STX
EXT 3
5
LDX
EXT 3
4
JSR
EXT 3
6
JMP
EXT 3
3
ADD
EXT 3
4
ORA
EXT 3
4
ADC
STX
LDX
JSR
IX2 2
IX2 2
6
IX2 2
5
IX2 2
7
JMP
IX2 2
4
ADD
IX2 2
5
ORA
IX2 2
5
ADC
IX2 2
5
EOR
STA
LDA
BIT
IX2 2
5
AND
IX2 2
5
CPX
IX2 2
5
SBC
IX2 2
5
CMP
IX1 1
4
IX1 1
5
STX
LDX
JSR
IX1 1
IX1 1
5
IX1 1
4
IX1 1
6
JMP
IX1 1
3
ADD
IX1 1
4
ORA
IX1 1
4
ADC
IX1 1
4
EOR
STA
LDA
IX1 1
4
IX1 1
4
AND
IX1 1
4
CPX
IX1 1
4
SBC
IX1 1
4
CMP
BIT
4
IX1 1
4
SUB
5 Number of Cycles
MSB of Opcode in Hexadecimal
DIR 3
STX
DIR 3
4
LDX
DIR 3
3
JSR
DIR 3
5
JMP
DIR 3
2
ADD
DIR 3
3
ORA
DIR 3
3
EXT 3
4
EOR
EXT 3
4
STA
EXT 3
5
LDA
EXT 3
4
BIT
EXT 3
4
AND
EXT 3
4
CPX
EXT 3
4
SBC
EXT 3
4
CMP
5
IX2 2
5
SUB
E
IX1
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
3
DIR Number of Bytes/Addressing Mode
STX
LDX
JSR
JMP
ADD
ORA
ADC
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
CT
OR
, IN
C.2
006
ADC
0
4
EXT 3
4
SUB
D
IX2
BRSET0 Opcode Mnemonic
2
IMM 2
LDX
0
2
REL 2
2
BSR
6
IMM 2
ADD
IMM 2
2
ORA
IMM 2
2
ADC
DIR 3
3
EOR
DIR 3
3
STA
DIR 3
4
LDA
DIR 3
3
DIR 3
3
AND
DIR 3
3
CPX
DIR 3
3
SBC
DIR 3
3
CMP
BIT
3
C
EXT
Register/Memory
DIR 3
3
SUB
B
DIR
DU
IMM 2
2
EOR
2
IMM 2
LDA
IMM 2
2
BIT
IMM 2
2
AND
IMM 2
2
CPX
IMM 2
2
SBC
IMM 2
2
CMP
IMM 2
2
SUB
LSB
2
INH 2
NOP
INH
2
RSP
INH 2
2
SEI
INH 2
2
INH 2
2
SEC
INH 2
2
CLC
CLI
2
2
2
2
2
2
2
2
A
IMM
ON
MIC
INH
SWI
INH
RTS
9
INH
LSB of Opcode in Hexadecimal
CLR
TST
INC
DEC
ROL
IX
5
9
INH
6
RTI
8
INH
Control
SE
IX
5
5
IX
IX 1
5
1
IX 1
ASL/LSL
IX1 1
6
ASR
ROR
LSR
COM
NEG
7
IX
LE
IX1 1
6
ROR
6
IX1 1
IX1 1
6
COM
LSR
6
IX1 1
NEG
6
IX1
CA
INH 2
LSRX
INH 2
3
ES
RE
COMA
INH
3
MUL
11
3
INH 2
NEGX
5
INH
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
REL 2
BIH
REL
3
BIL
REL 2
3
BMS
REL 2
3
BMC
REL
3
BMI
REL 2
3
BPL
REL 2
3
BHCS
5
DIR 1
5
COM
1
YF
3
INH 1
NEGA
4
INH
Read-Modify-Write
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL
REL 2
3
BHCC
REL 2
3
BEQ
REL 2
3
BNE
REL
3
5
DIR 1
NEG
3
DIR
DB
3
BCS/BLO
DIR 2
5
BCLR2
DIR 2
5
BSET2
DIR 2
5
BCLR1
DIR 2
5
BSET1
DIR 2
5
BCLR0
DIR 2
5
REL 2
3
BRA
2
REL
IVE
BSET0
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
3
BRCLR7
3
BRSET7
3
BRCLR6
3
BRSET6
3
BRCLR5
3
BRSET5
3
BRCLR4
3
BRSET4
3
BRCLR3
3
BRSET3
3
BRCLR2
3
BRSET2
3
BRCLR1
3
BRSET1
3
1
DIR
CH
BRCLR0
3
AR
0
MSB
LSB
DIR
Bit Manipulation Branch
Table 12-7. Opcode Map
Freescale Semiconductor, Inc...
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Freescale Semiconductor, Inc.
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
SECTION 13
ELECTRICAL SPECIFICATIONS
13.1
Maximum Ratings
(Voltages referenced to VSS
DU
Input Voltage
ON
Self-Check Modes (IRQ Pin Only)
Current Drain Per Pin Excluding VDD and VSS
MIC
Operating Temperature Range
68HC05P9AP (Standard)
68HC05P9ACP (Extended)
68HC05P9AVP (Automotive)
68HC05P9AMP (Automotive)
SE
Storage Temperature Range
Symbol
Value
Unit
VDD
-0.3 to +7.0
V
VIN
VSS -0.3 to VDD +0.3
V
VIN
VSS -0.3 to
2 x VDD +0.3
V
I
25
mA
TA
TL to TH
0 to +70
-40 to +85
-40 to +105
-40 to +125
°C
Tstg
-65 to +150
°C
Thermal Characteristics
YF
13.2
RE
ES
CA
LE
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields; however, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum-rated voltages to
this high-impedance circuit. For proper operation, it is recommended that Vin and
Vout be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Reliability of operation
is enhanced if unused inputs are connected to an appropriate logic voltage level
(e.g., either VSS or VDD).
Characteristic
Value
Unit
θJA
60
71
°C/W
CH
IVE
DB
Thermal Resistance
Plastic DIP
Plastic SOIC
Symbol
AR
Freescale Semiconductor, Inc...
Rating
Supply Voltage
ELECTRICAL SPECIFICATIONS
Rev. 2.0
13-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
13.3
DC Electrical Characteristics
CT
OR
, IN
C.2
006
Table 13-1. DC Electrical Characteristics (VDD = 5 V)
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted)
Characteristic
Output Voltage
ILOAD = 10.0 µA
ILOAD = -10.0 µA
Output Low Voltage
(ILOAD = 1.6 mA) PA0-PA7, PB5-PB7, PC2-PC7, PD5, TCMP
(ILOAD = 15 mA) PC0-PC1
Max
Unit
VOL
VOH
—
VDD-0.1
—
—
0.1
—
V
VOH
VOH
VDD-0.8
VDD-0.8
—
—
—
—
V
VOL
VOL
—
—
—
—
0.4
0.4
V
VIH
0.7 × VDD
—
VDD
V
VIL
VSS
—
0.2 × VDD
V
—
—
—
3.3
1.7
1.0
TBD
TBD
TBD
mA
mA
mA
—
—
—
—
—
2
—
—
—
—
5
TBD
TBD
TBD
100
µA
µA
µA
µA
µA
IIL
—
—
± 10
µA
IOZ
—
—
±1
µA
IIN
—
—
±1
µA
RPTA
TBD
15
TBD
kΩ
COUT
CIN
—
—
—
—
12
8
pF
IDD
LE
SE
MIC
ON
Input Low Voltage
PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7,
IRQ, RESET, OSC1
Supply Current
Run (A/D Enabled)
Wait (A/D Enabled)
Wait (A/D Disabled)/Halt
Stop
25°C
0°C to +70°C
-40°C to +85°C
-40°C to +105°C
-40°C to +125°C
Typ
DU
Input High Voltage
PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7,
IRQ, RESET, OSC1
Min
CA
I/O Ports Hi-Z Leakage Current
PA0-PA7, PB5-PB7, PC0-PC2, PD5
ES
A/D Ports Hi-Z Leakage Current
PC3–PC7
Input Current
RESET, IRQ, OSC1, TCAP/PD7
YF
Capacitance
Ports (as Input or Output)
RESET, IRQ
RE
I/O Ports Switch Resistance
(Pullup Enabled PA0-PA7)
CH
IVE
DB
NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C.
3. Wait IDD: Only timer system active.
4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source (fosc= 4.2 MHz), all inputs 0.2 V from
rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD -0.2 V.
6. Wait IDD is affected linearly by the OSC2 capacitance.
AR
Freescale Semiconductor, Inc...
Output High Voltage
(ILOAD = -0.8 mA) PA0-PA7, PB5-PB7, PC2-PC7, PD5, TCMP
(ILOAD = -5.0 mA) PC0-PC1
Symbol
ELECTRICAL SPECIFICATIONS
13-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Characteristic
Output Voltage
ILOAD = 10.0 µA
ILOAD = -10.0 µA
Output High Voltage
(ILOAD = -0.2 mA) PA0-PA7, PB5-PB7, PC2-PC7,
PD5, TCMP
(ILOAD = -1.5 mA) PC0-PC1
Typ
Max
Unit
VOL
VOH
—
VDD-0.1
—
—
0.1
—
V
VDD-0.3
—
—
VDD-0.3
—
—
—
—
0.3
—
—
0.3
0.7 × VDD
—
VDD
V
VSS
—
0.2 × VDD
V
—
—
—
1.2
0.8
0.4
TBD
TBD
TBD
mA
mA
mA
—
—
—
—
—
1
—
—
—
—
3
TBD
TBD
TBD
70
µA
µA
µA
µA
µA
IIL
—
—
±10
µA
IOZ
—
—
±1
µA
IIN
—
—
±1
µA
RPTA
TBD
25
TBD
kΩ
COUT
CIN
—
—
—
—
12
8
pF
VOL
VOL
DU
VIH
Input Low Voltage
PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7,
IRQ, RESET, OSC1
MIC
ON
VIL
LE
SE
IDD
CA
I/O Ports Hi-Z Leakage Current
PA0-PA7, PB5-PB7, PC0-PC2, PD5
A/D Ports Hi-Z Leakage Current
PC3–PC7
YF
Capacitance
Ports (as Input or Output)
RESET, IRQ
RE
I/O Ports Switch Resistance
(Pullup Enabled PA0-PA7)
ES
Input Current
RESET, IRQ, OSC1, TCAP/PD7
V
V
CH
IVE
DB
NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C.
3. Wait IDD: Only timer system active.
4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source (fosc= 2.0 MHz), all inputs 0.2 V from
rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD -0.2 V.
6. Wait IDD is affected linearly by the OSC2 capacitance.
AR
Freescale Semiconductor, Inc...
Min
VOH
Input High Voltage
PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7,
IRQ, RESET, OSC1
Supply Current
Run (A/D Enabled)
Wait (A/D Enabled)
Wait (A/D Disabled)/Halt
Stop
25°C
0°C to +70°C
-40°C to +85°C
-40°C to +105°C
-40°C to +125°C
Symbol
VOH
Output Low Voltage
(ILOAD = 0.4 mA) PA0-PA7, PB5-PB7, PC2-PC7,
PD5, TCMP
(ILOAD = 6.0 mA) PC0-PC1
CT
OR
, IN
C.2
006
Table 13-2. DC Electrical Characteristics (VDD = 3.3 V)
(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted)
ELECTRICAL SPECIFICATIONS
Rev. 2.0
13-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
13.4
A/D Converter Characteristics
CT
OR
, IN
C.2
006
Table 13-3. A/D Converter Characteristics
Characteristic
Resolution
Absolute Accuracy (4.0 V > VRH > VDD)
(See Note 1)
Conversion Range
VRH
Conversion Time (Includes Sampling Time)
External Clock (XTAL)
Internal RC Oscillator (ADRC = 1)
Monotonicity
Max
Unit
8
8
Bit
—
±1–1/2
LSB
VSS
VSS
VRH
VDD
V
32
—
32
32
tAD
µs
—
100
µs
Inherent (Within Total Error)
DU
Zero Input Reading (Vin = 0 V)
Full-Scale Reading (Vin = VRH)
ON
Sample Acquisition Time (see Note 2)
External Clock (XTAL)
Internal RC Oscillator (ADRC = 1)
MIC
Input Capacitance
PC3/AN3–PC6/AN0
Analog Input Voltage
SE
Input Leakage (see Note 4)
AN0–AN3
VRH
00
01
Hex
FF
FF
Hex
12
—
12
12
tAD
µs
—
12
pF
VSS
VRH
V
—
—
±1
±1
µA
CH
IVE
DB
YF
RE
ES
CA
LE
NOTES:
1. A/D accuracy may decrease proportionately as VRH is reduced below 4.0 V.
2. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
3. tAD = tcyc if clock source is MCU.
4. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
AR
Freescale Semiconductor, Inc...
Power-Up Time
Min
ELECTRICAL SPECIFICATIONS
13-4
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
13.5 SIOP Timing
CT
OR
, IN
C.2
006
Table 13-4. SIOP Timing (VDD = 5 V)
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted)
Num.
Characteristic
Cycle Time
Master
Slave
2
Clock (SCK) Low Time
3
SDO Data Valid Time
4
SDO Hold Time
5
SDI Setup Time
6
SDI Hold Time
DU
1
Symbol
Min
Max
Unit
fop(m)
fop(s)
0.25
dc
0.25
0.25
fop
tcyc(m)
tcyc(s)
4.0
4.0
4.0
—
tcyc
tcyc
932
—
ns
tv
—
200
ns
tho
0
—
ns
ts
100
—
ns
th
100
—
ns
ON
NOTE: fop = 2.1 MHz maximum
Table 13-5. SIOP Timing (VDD = 3.3 V)
Num.
MIC
(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted)
Characteristic
2
Clock (SCK) Low Time
3
SDO Data Valid Time
4
SDO Hold Time
5
SDI Setup Time
6
SDI Hold Time
CA
Cycle Time
Master
Slave
RE
ES
1
LE
SE
Operating Frequency
Master
Slave
DB
YF
NOTE: fop = 1.0 MHz maximum
SDI
CH
SDO
IVE
SCK
AR
Freescale Semiconductor, Inc...
Operating Frequency
Master
Slave
Symbol
Min
Max
Unit
fop(m)
fop(s)
0.25
dc
0.25
0.25
fop
tcyc(m)
tcyc(s)
4.0
4.0
4.0
—
tcyc
tcyc
1980
—
ns
tv
—
400
ns
tho
0
—
ns
ts
200
—
ns
th
200
—
ns
1
2
BIT 0
BIT 1
BIT 6
4
3
BIT 0
BIT 1
BIT 7
6
BIT 6
BIT 7
5
Figure 13-1. SIOP Timing Diagram
ELECTRICAL SPECIFICATIONS
Rev. 2.0
13-5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Control Timing
CT
OR
, IN
C.2
006
13.6
Table 13-6. Control Timing (VDD = 5 V)
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted
Characteristic
Frequency of Operation
Crystal Option
External Clock Option
Internal Operating Frequency
Crystal (fosc ÷ 2)
External Clock (fosc ÷ 2)
Crystal Oscillator Startup Time
DU
Stop Recovery Startup Time (Crystal Oscillator)
RESET Pulse Width
ON
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
OSC1 Pulse Width
MIC
RC Oscillator Stabilization Time
A/D On Current Stabilization Time
Min
Max
Unit
fosc
—
dc
4.2
4.2
MHz
fop
—
dc
2.1
2.1
MHz
tcyc
480
—
ns
tOXOV
—
100
ms
tILCH
—
100
ms
tRL
1.5
—
tcyc
tILIH
125
—
ns
tILIL
*
—
tcyc
tOH, tOL
90
—
ns
tRCON
—
5
µs
tADON
—
100
µs
SE
*The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tcyc.
LE
Table 13-7. Control Timing (VDD = 3.3 V)
Characteristic
ES
Frequency of Operation
Crystal Option
External Clock Option
RE
Internal Operating Frequency
Crystal (fosc ÷ 2)
External Clock (fosc ÷ 2)
YF
Cycle Time
Crystal Oscillator Startup Time
CA
(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted
Min
Max
Unit
fosc
—
dc
2.0
2.0
MHz
fop
—
dc
1.0
1.0
MHz
tcyc
1000
—
ns
tOXOV
—
100
ms
tILCH
—
100
ms
RESET Pulse Width, Excluding Powerup
tRL
1.5
—
tcyc
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
250
—
ns
Interrupt Pulse Period
tILIL
*
—
tcyc
tOH, tOL
200
—
ns
IVE
OSC1 Pulse Width
DB
Stop Recovery Startup Time (Crystal Oscillator)
Symbol
CH
*The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tcyc.
AR
Freescale Semiconductor, Inc...
Cycle Time
Symbol
ELECTRICAL SPECIFICATIONS
13-6
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
CT
OR
, IN
C.2
006
OSC 1
t RL
RESET
t ILIH
IRQ 2
DU
IRQ 3
ON
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
1FFE
1FFE
1FFE
MIC
1FFE
1FFE
1FFF 4
SE
RESET OR INTERRUPT
VECTOR FETCH
CA
LE
NOTES:
1. Represents the internal clocking of the OSC1 pin.
2. IRQ pin edge–sensitive mask option.
3. IRQ pin level– and edge–sensitive mask option.
4. RESET vector address shown for timing example.
RE
ES
Figure 13-2. STOP Recovery Timing
t ILIH
IRQ (PIN)
DB
YF
t ILIL
RQ (MCU)
IVE
NORMALLY
USED WITH
WIRE–ORed
CONNECTION
CH
•
•
•
IRQn
Level - Sensitive Trigger Condition
If after ser vicing an interrupt the IRQ
remains low, then the next interrupt is
recognized.
t ILIH
IRQ1
Edge - Sensit ive Trigger Condition
The minimum pulse width (t ILIH ) is
either 125 ns (V DD = 5 V) or 250 ns
(VDD = 3 V). The period t ILIL should
not be less than the number of t cyc
cycles it takes to execute the interr upt
service routine plus 19 t cyc cycles.
AR
Freescale Semiconductor, Inc...
4064 t cyc
Figure 13-3. External Interrupt Timing
ELECTRICAL SPECIFICATIONS
Rev. 2.0
13-7
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
VDD
CT
OR
, IN
C.2
006
t VDDR
VDD THRESHOLD (TYPICALLY 1-2 V)
SC1 PIN
INTERNAL
ADDRESS
BUS
1FFE
1FFE
1FFE
1FFE
1FFE
ON
1FFE
DU
INTERNAL
CLOCK
1FFF
NEW
PCH
NEW
PCL
MIC
INTERNAL
DATA
BUS
SE
NOTES:
1. Internal clock, internal address bus, and internal data bus signals are not available externally.
2. An internal POR reset is triggered as V
rises through a threshold (typically 1-2 V).
DD
CA
LE
Figure 13-4. Power-On Reset Timing
RE
ES
NTERNAL
CLOCK
NTERNAL
DDRESS
BUS
1FFE
YF
1FFE
DB
NTERNAL
DATA
BUS
1FFE
1FFE
NEW
PCH
1FFF
NEW PC
NEW
PCL
DUMMY
NEW PC
OP
CODE
RESET
IVE
t RL
CH
NOTES:
1. Internal clock, internal address bus, and internal data bus signals are not available externally.
2. The next rising edge of the internal processor clock after the rising edge of RESET initiates the reset sequence.
AR
Freescale Semiconductor, Inc...
4064 t cyc
Figure 13-5. External Reset Timing
ELECTRICAL SPECIFICATIONS
13-8
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
SECTION 14
MECHANICAL SPECIFICATIONS
28-Pin Plastic Dual In-Line Package (Case 710-02)
15
MIC
28
ON
DU
14.1
B
14
A
C
G
F
K
M
J
°
°
°
°
CH
IVE
DB
YF
RE
ES
D
L
CA
H
LE
N
SE
1
! ! ! #! %% !
$" ! ! ! ! ! !
! ! # ! "
AR
Freescale Semiconductor, Inc...
This section describes the dimensions of the dual in-line package (DIP) and small
outline integrated circuit (SOIC) MCU packages.
MECHANICAL SPECIFICATIONS
Rev. 2.0
14-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
28-Pin Small Outline Integrated Circuit Package (Case 751F-04)
-A28
15
14X
-B1
P
14
28X D
!
C
-T-
-T-
G
Freescale Semiconductor, Inc...
! ! %
! !
! " !" $" !" ! "
!" #
!" !! $ ! $" !
!
M
R X 45°
26X
CT
OR
, IN
C.2
006
14.2
F
J
°
°
°
°
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
K
MECHANICAL SPECIFICATIONS
14-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC0P9A
Rev. 2.0
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
SECTION 15
ORDERING INFORMATION
This section contains instructions for ordering custom-masked ROM MCUs.
MCU Ordering Forms
ON
DU
To initiate an order for a ROM-based MCU, first obtain the current ordering form
for the MCU from a Motorola representative. Submit the following items when
ordering MCUs:
A current MCU ordering form that is completely filled out (Contact your
Motorola sales office for assistance.)
•
A copy of the customer specification if the customer specification
deviates from the Motorola specification for the MCU
•
Customer’s application program on one of the media listed in 15.2
Application Program Media
LE
SE
MIC
•
CH
IVE
DB
YF
RE
ES
CA
The current MCU ordering form is also available through the Motorola Freeware
Bulletin Board Service (BBS). The telephone number is (512) 891-FREE. After
making the connection, type bbs in lower-case letters. Then press the return key
to start the BBS software.
AR
Freescale Semiconductor, Inc...
15.1
ORDERING INFORMATION
Rev. 2.0
15-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
15.2
Application Program Media
CT
OR
, IN
C.2
006
Freescale Semiconductor, Inc...
Please deliver the application program to Motorola in one of the following media:
•
Macintosh1 3 1/2-inch diskette (double-sided 800K or double-sided
high-density 1.4M)
•
MS-DOS2 or PC-DOSTM3 3 1/2-inch diskette (double-sided 720K or
double-sided high-density 1.44M)
•
MS-DOS or PC-DOSTM 5 1/4-inch diskette (double-sided doubledensity 360K or double-sided high-density 1.2M)
DU
Use positive logic for data and addresses.
ON
When submitting the application program on a diskette, clearly label the diskette
with the following information:
Customer name
•
Customer part number
•
Project or product name
•
File name of object code
•
Date
•
Name of operating system that formatted diskette
•
Formatted capacity of diskette
ES
CA
LE
SE
MIC
•
DB
YF
RE
On diskettes, the application program must be in Motorola’s S-record format (S1
and S9 records), a character-based object file format generated by M6805 cross
assemblers and linkers.
NOTE
AR
CH
IVE
Begin the application program at the first user ROM location.
Program addresses must correspond exactly to the available
on-chip user ROM addresses as shown in the memory map. Write
$00 in all non-user ROM locations or leave all non-user ROM
locations blank. Refer to the current MCU ordering form for
additional requirements. Motorola may request pattern resubmission if non-user areas contain any non-zero code.
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft Corporation.
3. PC-DOS is a trademark of International Business Machines Corporation.
ORDERING INFORMATION
15-2
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
CT
OR
, IN
C.2
006
If the memory map has two user ROM areas with the same address, then write
the two areas in separate files on the diskette. Label the diskette with both file
names.
In addition to the object code, a file containing the source code can be included.
Motorola keeps this code confidential and uses it only to expedite ROM pattern
generation in case of any difficulty with the object code. Label the diskette with the
file name of the source code.
ROM Program Verification
DU
The primary use for the on-chip ROM is to hold the customer’s application
program. The customer develops and debugs the application program and then
submits the MCU order along with the application program.
SE
MIC
ON
Motorola inputs the customer’s application program code into a computer program
that generates a listing verify file. The listing verify file represents the memory
map of the MCU. The listing verify file contains the user ROM code and may also
contain non-user ROM code, such as self-check code. Motorola sends the
customer a computer printout of the listing verify file along with a listing verify
form.
CA
LE
To aid the customer in checking the listing verify file, Motorola will program the
listing verify file into customer-supplied blank preformatted Macintosh or DOS
disks. All original pattern media are filed for contractual purposes and are not
returned.
ROM Verification Units (RVUs)
YF
15.4
RE
ES
Check the listing verify file thoroughly, then complete and sign the listing verify
form and return the listing verify form to Motorola. The signed listing verify form
constitutes the contractual agreement for the creation of the custom mask.
CH
IVE
DB
After receiving the signed listing verify form, Motorola manufactures a custom
photographic mask. The mask contains the customer’s application program and is
used to process silicon wafers. The application program cannot be changed after
the manufacture of the mask begins. Motorola then produces 10 MCUs, called
RVUs, and sends the RVUs to the customer. RVUs are usually packaged in
unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are not tested
to environmental extremes because their sole purpose is to demonstrate that the
customer’s user ROM pattern was properly implemented. The 10 RVUs are free of
charge with the minimum order quantity. These units are not to be used for
qualification or production. RVUs are not guaranteed by Motorola Quality
Assurance.
AR
Freescale Semiconductor, Inc...
15.3
ORDERING INFORMATION
Rev. 2.0
15-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
GENERAL RELEASE SPECIFICATION
ORDERING INFORMATION
15-4
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
CT
OR
, IN
C.2
006
RoHS-compliant and/or Pb- free versions of Freescale products have the functionality
and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
CA
LE
SE
MIC
ON
DU
For information on Freescale.s Environmental Products program, go to
http://www.freescale.com/epp.
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
CH
IVE
DB
YF
RE
ES
Home Page:
www.freescale.com
email:
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
(800) 521-6274
480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064, Japan
0120 191014
+81 2666 8080
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor
Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
(800) 441-2447
303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com
AR
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Motorola, Inc., 1995
For More Information On This Product,
Go to: www.freescale.com
HC05P9AGRS/D