DRV120 www.ti.com SLVSBG3A – JUNE 2012 – REVISED AUGUST 2012 POWER SAVING CURRENT CONTROLLED SOLENOID DRIVER Check for Samples: DRV120 FEATURES 1 • • • • • Integrated MOSFET With PWM to Control Solenoid Current – Integrated Sense Resistor for Regulating Solenoid Current Fast Ramp-Up of Solenoid Current to Guarantee Activation Solenoid Current is Reduced in Hold Mode for Lower Power and Thermal Dissipation Peak Current, Keep Time at Peak Current, Hold Current and PWM Clock Frequency Can Be Set Externally. They Can Also Be Operated at Nominal Values Without External Components. Internal Supply Voltage Regulation – Up to 28-V External Supply • • • Protection – Thermal Shutdown – Under Voltage Lockout (UVLO) – Maximum Ramp Time – Optional STATUS Output Operating Temperature Range: -40ºC to 105ºC 8-Pin and 14-Pin TSSOP Package Options APPLICATIONS • • Electromechanical Driver: Solenoids, Valves, Relays White Goods, Solar, Transportation DESCRIPTION The DRV120 is a PWM current driver for solenoids. It is designed to regulate the current with a well controlled waveform to guarantee activation and to reduce power dissipation at the same time. The solenoid current is ramped up fast to ensure opening of the valve or relay. After the initial ramping, solenoid current is kept at peak value to ensure the correct operation, after which it is reduced to a lower hold level in order to avoid thermal problems and reduce power dissipation. The peak current duration is set with an external capacitor. The current ramp peak and hold levels, as well as PWM frequency can independently be set with external resistors. External setting resistors can also be omitted, if the default values for the corresponding parameters are suitable for the application. DRV120 can operate from external 6-V to 28-V supply. ORDERING INFORMATION (1) ORDERABLE PART NUMBER PACKAGE (2) (1) (2) TOP-SIDE MARKING (TSSOP-8) - PW Reel of 2000 DRV120PWR 120 (TSSOP-14) - PW Reel of 2000 DRV120APWR 120A For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated DRV120 SLVSBG3A – JUNE 2012 – REVISED AUGUST 2012 www.ti.com TYPICAL APPLICATION Figure 1. Default Configuration With 8-Pin TSSOP Option Figure 2. External Parameter Setting for 14-Pin TSSOP Option 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV120 DRV120 www.ti.com SLVSBG3A – JUNE 2012 – REVISED AUGUST 2012 DEVICE INFORMATION Functional Block Diagram Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV120 3 DRV120 SLVSBG3A – JUNE 2012 – REVISED AUGUST 2012 www.ti.com Table 1. TERMINAL FUNCTIONS PIN (8-PIN PW) (1) PIN (14-PIN PW) NC 6 1, 6, 9, 10, 14 KEEP 1 2 Keep time set PEAK 2 3 Peak current set HOLD - 4 Hold current set OSC 3 5 PWM frequency set VIN 4 7 6-V to 28-V supply GND 5 8 Ground OUT 7 11 Controlled current sink STATUS - 12 Open drain fault indicator EN 8 13 Enable NAME (1) DESCRIPTION No connect In the 8-pin package, the HOLD pin is not bonded out. For this package, the HOLD mode is configured to default (internal) settings. xxx xxx PW PACKAGE 8-PIN (TOP VIEW) 4 PW PACKAGE 14-PIN (TOP VIEW) KEEP 1 8 EN NC 1 14 NC PEAK 2 7 OUT KEEP 2 13 EN OSC 3 6 NC PEAK 3 12 STATUS VIN 4 5 GND HOLD 4 11 OUT OSC 5 10 NC NC 6 9 NC VIN 7 8 GND Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV120 DRV120 www.ti.com SLVSBG3A – JUNE 2012 – REVISED AUGUST 2012 ABSOLUTE MAXIMUM RATINGS (1) (2) VIN VALUE UNIT –0.3 to 28 V Voltage range on EN, STATUS, PEAK, HOLD, OSC, SENSE, RAMP –0.3 to 7 V Voltage range on OUT –0.3 to 28 V Input voltage range ESD rating HBM (human body model) 2000 CDM (charged device model) 500 V TJ Operating virtual junction temperature range –40 to 125 °C Tstg Storage temperature range –65 to 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM IOUT Average solenoid DC current VIN Supply voltage 6 12 CIN Input capacitor 1 4.7 L Solenoid inductance TA Operating ambient temperature MAX UNIT 125 mA 26 V µF 1 H -40 105 °C THERMAL INFORMATION DRV120 THERMAL METRIC Junction-to-ambient thermal resistance (1) θJA (2) DRV120 PW PW 8 PINS 14 PINS 183.8 122.6 θJCtop Junction-to-case (top) thermal resistance 69.2 51.2 θJB Junction-to-board thermal resistance (3) 112.6 64.3 ψJT Junction-to-top characterization parameter (4) 10.4 6.5 ψJB Junction-to-board characterization parameter (5) 110.9 63.7 N/A N/A θJCbot (1) (2) (3) (4) (5) (6) Junction-to-case (bottom) thermal resistance (6) UNITS °C/W The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV120 5 DRV120 SLVSBG3A – JUNE 2012 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS VIN = 14 V, TA = -40°C to 105°C, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Standby current EN = 0, VIN = 14 V 100 150 Quiescent current EN = 1, VIN = 14 V 300 400 1.7 2.5 Ω 20 25 kHz µA CURRENT DRIVER ROUT OUT to GND resistance IOUT = 200 mA fPWM PWM frequency OSC = GND DMAX Maximum PWM duty cycle 100 % DMIN Minimum PWM duty cycle 9 % tD Start-up delay 15 Delay between EN going high until driver enabled (1), fPWM = 20 kHz 25 50 µs CURRENT CONTROLLER, INTERNAL SETTINGS IPEAK Peak current PEAK = GND 160 200 240 mA IHOLD Hold current HOLD = GND 40 50 60 mA CURRENT CONTROLLER, EXTERNAL SETTINGS tKEEP (2) Externally set keep time at peak current IPEAK Externally set peak current IHOLD Externally set hold current fPWM Externally set PWM frequency CKEEP = 1 µF 75 RPEAK = 50 kΩ 250 RPEAK = 200 kΩ 83 RHOLD = 50 kΩ 100 RHOLD = 200 kΩ 33 ROSC = 50 kΩ 60 ROSC = 200 kΩ 20 ms mA mA kHz LOGIC INPUT LEVELS (EN) VIL Input low level VIH Input high level 1.65 1.3 REN Input pull-up resistance 350 V V 500 kΩ LOGIC OUTPUT LEVELS (STATUS) VOL Output low level Pull-down activated, ISTATUS = 2 mA IIL Output leakage current Pull-down deactivated, V(STATUS) = 5 V 0.3 V 1 µA UNDERVOLTAGE LOCKOUT VUVLO Undervoltage lockout threshold 4.6 V THERMAL SHUTDOWN TTSD Junction temperature shutdown threshold 160 °C TTSU Junction temperature startup threshold 140 °C (1) (2) 6 Logic HIGH between 4 V and 7 V. Note: absolute max voltage rating is 7 V. Either internal or external tKEEP time setting is selected to be activated during manufacturing of production version of DRV120. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV120 DRV120 www.ti.com SLVSBG3A – JUNE 2012 – REVISED AUGUST 2012 FUNCTIONAL DESCRIPTION DRV120 controls the current through the solenoid as shown in Figure 3. Activation starts when EN pin voltage is pulled high either by an external driver or internal pull-up. In the beginning of activation, DRV120 allows the load current to ramp up to the peak value IPEAK and it regulates it at the peak value for the time, tKEEP, before reducing it to IHOLD. The load current is regulated at the hold value as long as the EN pin is kept high. The initial current ramp-up time depends on the inductance and resistance of the solenoid. Once EN pin is driven to GND, DRV120 allows the solenoid current to decay to zero. ISOLENOID IPEAK IHOLD t tKEEP EN t Figure 3. Typical Current Waveform Through the Solenoid tKEEP is set externally by connecting a capacitor to the KEEP pin. A constant current is sourced from the KEEP pin that is driven into an external capacitor resulting in a linear voltage ramp. When the KEEP pin voltage reaches 75 mV, the current regulation reference voltage, VREF, is switched from VPEAK to VHOLD. Dependency of tKEEP from the external capacitor size can be calculated by: ésù tKEEP éës ùû = CKEEP éëF ùû × 75 × 103 ê ú ëF û (1) The current control loop regulates, cycle-by-cycle, the solenoid current by using an internal current sensing resistor and MOSFET switch. During the ON-cycle, current flows from OUT pin to GND pin through the internal switch as long as voltage over current sensing resistor is less than VREF. As soon as the current sensing voltage is above VREF, the internal switch is immediately turned off until the next ON-cycle is triggered by the internal PWM clock signal. In the beginning of each ON-cycle, the internal switch is turned on and stays on for at least the time determined by the minimum PWM signal duty cycle, DMIN. IPEAK and IHOLD depend on fixed resistance values RPEAK and RHOLD as shown in Figure 4. If the PEAK pin is connected to ground or if RPEAK is below 33.33 kΩ (typ value), then IPEAK is at its default value (internal setting). The IPEAK value can alternatively be set by connecting an external resistor to ground from the PEAK pin. For example, if a 50-kΩ (= RPEAK) resistor is connected between PEAK and GND, then the externally set IPEAK level will be 250 mA. If RPEAK = 200 kΩ is, then the externally set IPEAK level will be 83 mA. HOLD current external setting, IHOLD, works in the same way, but current levels are 40% of the IPEAK. External settings for IPEAK and IHOLD are independent of each other. IPEAK and IHOLD values can be calculated by using the formula below. 250mA IPEAK = × 66.67kW ;66.67kW < RPEAK < 550kW RPEAK (2) I HOLD = 100mA × 66.67kW ;66.67kW < RHOLD < 250kW RHOLD (3) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV120 7 DRV120 SLVSBG3A – JUNE 2012 – REVISED AUGUST 2012 www.ti.com Figure 4. PEAK and HOLD Mode Current Settings 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV120 DRV120 www.ti.com SLVSBG3A – JUNE 2012 – REVISED AUGUST 2012 Frequency of the internal PWM clock signal, PWMCLK, that triggers each ON-cycle can be adjusted by external resistor, ROSC, connected between OSC and GND. Frequency as a function of resistor value is shown in Figure 5. Default frequency is used when OSC is connected to GND directly. PWM frequency as a function of external fixed adjustment resistor value (greater than 66.67 kΩ) is given below. 60kHz fPWM = × 66.67kW ;66.67kW < ROSC < 2MW ROSC (4) Figure 5. PWM Clock Frequency Setting Open-drain STATUS output is deactivated if either under voltage lockout or thermal shutdown blocks have triggered. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV120 9 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) DRV120APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV120PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DRV120APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DRV120PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV120APWR TSSOP PW 14 2000 367.0 367.0 35.0 DRV120PWR TSSOP PW 8 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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