54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS450 – MARCH 1987 – REVISED APRIL 1993 • • • • • 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE (TOP VIEW) Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C ESD Protection Exceeds 2000 V, MIL STD-883C Method 3015 Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2CLK 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1CLK 1K 1J 1CLR VCC 2CLR 2J 2K 54AC11109 . . . FK PACKAGE (TOP VIEW) 1J 1CLR NC VCC 2CLR • description These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops by tying the J and K inputs together. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2J 2K NC 2CLK 2PRE 1Q GND NC 2Q 2Q 1K 1CLK NC 1PRE 1Q NC – No internal connection The 54AC11109 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74AC11109 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE (each gate) INPUTS PRE CLR CLK L H X H L X OUTPUTS J K Q Q X X H L X X H H† H L L X X X L H† H H ↑ L L L H H ↑ H L H H ↑ L H Q0 Q0 H H ↑ H H H L Toggle H H L X X Q0 Q0 † This configuration is nonstable; that is, it will not persist when either PRE or CLR returns to its inactive (high) level. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS450 – MARCH 1987 – REVISED APRIL 1993 logic symbol† 1 1PRE 1J 1CLK 1K 14 15 1CLR 7 2J 2CLK 2K 10 1Q C1 9 3 1Q 1K R S 6 2J 8 11 2CLR 2 1J 16 13 2PRE S 2Q C2 5 2Q 2K R † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS450 – MARCH 1987 – REVISED APRIL 1993 recommended operating conditions 54AC11109 VCC Supply voltage VIH VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL Low-level input voltage VI VO MAX 3 5 5.5 Input transition rise or fall rate TA Operating free-air temperature 3 5 5.5 3.15 UNIT V V 3.85 0.9 0.9 1.35 1.35 1.65 1.65 VCC VCC 0 ∆t /∆v MAX 3.15 VCC = 3 V VCC = 4.5 V Low-level output current NOM 2.1 0 High-level output current MIN 2.1 VCC = 4.5 V VCC = 5.5 V Output voltage IOL NOM 3.85 Input voltage IOH 74AC11109 MIN 0 VCC VCC 0 –4 –4 – 24 – 24 VCC = 5.5 V VCC = 3 V – 24 – 24 12 12 VCC = 4.5 V VCC = 5.5 V 24 24 24 24 V V V mA mA 0 10 0 10 ns / V – 55 125 – 40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = – 50 µA VOH IOH = – 4 mA IOH = – 24 mA A IOH = – 50 mA† IOH = – 75 mA† TA = 25°C TYP MAX 54AC11109 74AC11109 MIN MIN MAX 3V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 3V 2.58 2.4 2.48 4.5 V 3.94 3.7 3.8 5.5 V 4.94 4.7 4.8 IOL = 12 mA MAX UNIT V 3.85 5.5 V IOL = 24 mA II ICC MIN 5.5 V IOL = 50 µA VOL VCC 3.85 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 V IOL = 50 mA† IOL = 75 mA† 5.5 V VI = VCC or GND VI = VCC or GND, 5.5 V ± 0.1 ±1 ±1 µA 5.5 V 4 80 40 µA 1.65 5.5 V IO = 0 1.65 Ci VI = VCC or GND 5V 3.5 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF 2–3 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS450 – MARCH 1987 – REVISED APRIL 1993 timing requirements, VCC = 3.3 V ± 0.3 V (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency 0 PRE or CLR low tw Pulse duration tsu Setup time before CLK↑ th Hold time after CLK↑ 70 54AC11109 74AC11109 MIN MAX MIN MAX 0 70 0 70 5 5 5 CLK low or CLK high 7.2 7.2 7.2 Data high or low 5.5 5.5 5.5 PRE or CLR inactive 2.5 2.5 2.5 0 0 0 UNIT MHz ns ns ns timing requirements, VCC = 5 V ± 0.5 V (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency 0 tw Pulse duration tsu Setup time, time before CLK↑ th Hold time, after CLK↑ 100 54AC11109 74AC11109 MIN MAX MIN MAX 0 100 0 100 PRE or CLR low 4 4 4 CLK low or CLK high 5 5 5 4.5 4.5 2.5 2 2 2 0 0 0 Data high or low PRE or CLR inactive UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q MIN TA = 25°C TYP MAX 54AC11109 74AC11109 MIN MIN MAX 70 MAX 70 100 70 1.5 6.5 9 1.5 10.5 1.5 9.9 1.5 8 12.6 1.5 14.4 1.5 13.7 1.5 8 11.4 1.5 13.5 1.5 12.7 1.5 7.5 10.5 1.5 12.7 1.5 11.8 UNIT MHz ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q TA = 25°C MIN TYP MAX 54AC11109 74AC11109 MIN MIN MAX 100 MAX 100 125 100 1.5 4.5 6.5 1.5 7.6 1.5 7.1 1.5 5 8.6 1.5 10.2 1.5 9.6 1.5 5.5 7.9 1.5 9.4 1.5 8.8 1.5 5 7.3 1.5 8.6 1.5 8.1 UNIT MHz ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 2–4 TEST CONDITIONS Power dissipation capacitance per gate POST OFFICE BOX 655303 CL = 50 pF, • DALLAS, TEXAS 75265 f = 1 MHz TYP UNIT 32 pF 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS450 – MARCH 1987 – REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION From Output Under Test tw CL = 50 pF (see Note A) VCC 500 Ω Input 50% 50% 0V VOLTAGE WAVEFORMS LOAD CIRCUIT VCC Input (see Note B) Timing Input (see Note B) VCC 50% 0V th tsu Data Input 50% 50% 0V tPHL tPLH In-Phase Output 50% VCC VCC 50% 50% tPLH tPHL 0V Out-of-Phase Output VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS450 – MARCH 1987 – REVISED APRIL 1993 2–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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