TI 74AC11646

74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
•
•
•
•
•
•
DW PACKAGE
(TOP VIEW)
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity
at 125°C
OE
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
DIR
description
The 74AC11646 consists of bus transceiver
circuits, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the input bus or from the internal
registers. Data on the A or B bus is clocked
into the registers on the low-to-high transition of
the appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental busmanagement functions that can be performed with
the 74AC11646.
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
CLKAB
SAB
B1
B2
B3
B4
VCC
VCC
B5
B6
B7
B8
CLKBA
SBA
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),
A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The 74AC11646 is characterized for operation from – 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
1
OE
L
14
DIR
L
15
SBA
L
27
SAB
X
16
28
CLKAB CLKBA
X
X
BUS B
BUS A
BUS A
BUS B
SCAS079A – JULY 1987 – REVISED APRIL 1993
1
OE
L
28
16
CLKAB CLKBA
X
↑
X
↑
↑
↑
27
SAB
X
X
X
15
SBA
X
X
X
STORAGE FROM
A, B, OR A AND B
1
OE
L
L
15
SBA
X
BUS B
14
DIR
L
H
28
CLKAB
X
L
16
CLKBA
L
X
27
SAB
X
H
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
2–2
27
SAB
L
BUS A
BUS B
BUS A
14
DIR
X
X
X
16
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
1
OE
X
X
H
28
CLKAB
X
14
DIR
H
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SBA
H
X
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
FUNCTION TABLE
INPUTS
OE
DIR
X
X
DATA I/O
OPERATION OR FUNCTION
CLKAB
CLKBA
SAB
SBA
A1 THRU A8
B1 THRU B8
X
↑
X
X
X
X
X
↑
X
X
Input
Unspecified†
Unspecified†
Input
Store A,, B unspecified†
Store B, A unspecified†
H
X
↑
↑
X
X
H
X
L
L
X
X
Input
Input disabled
Input
Input disabled
Store A and B data
Isolation, hold storage
L
L
X
X
X
L
L
L
X
L
X
H
Output
Output
Input
Input
Real-time B data to A bus
Stored B data to A bus
L
H
X
X
L
X
L
H
L
X
H
X
Input
Input
Output
Output
Real-time A data to B bus
Stored A data to B bus
† The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs.
logic symbol‡
1
OE
DIR
CLKBA
SBA
CLKAB
SAB
A1
14
16
G3
3 EN1 [BA]
3 EN2 [AB]
C4
15
G5
28
27
2
C6
G7
≥1
1
6D
A2
A3
A4
A5
A6
A7
A8
5
7
1
4D
5
20
B1
1
≥1
2
7
3
25
4
24
5
23
10
20
11
19
12
18
13
17
B2
B3
B4
B5
B6
B7
B8
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–3
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
logic diagram (positive logic)
OE
DIR
CLKBA
SBA
CLKAB
SAB
1
14
16
15
28
27
One of Eight
Channels
1D
C1
A1
2
26
B1
1D
C1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2–4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
recommended operating conditions
VCC
Supply voltage
VIH
High-level input voltage
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
MIN
NOM
MAX
3
5
5.5
V
3.85
VCC = 3 V
VCC = 4.5 V
0.9
Low-level input voltage
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
1.35
VCC = 5.5 V
Low-level output current
∆t /∆v
Input transition rise or fall rate
TA
Operating free-air temperature
V
2.1
3.15
VIL
IOL
UNIT
V
1.65
VCC
VCC
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
V
V
–4
– 24
mA
– 24
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
12
24
mA
24
0
10
ns/ V
– 40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = – 50 µA
VOH
3V
2.9
2.9
4.5 V
4.4
4.4
5.4
5.4
2.58
2.48
4.5 V
3.94
3.8
IOH = – 24 mA
A
5.5 V
4.94
IOH = – 75 mA†
5.5 V
IOL = 12 mA
IOL = 24 mA
ICC
Ci
MIN
3V
IOL = 50 µA
II
IOZ‡
TA = 25°C
MIN
TYP
MAX
5.5 V
IOH = – 4 mA
VOL
VCC
MAX
UNIT
V
4.8
3.85
3V
0.1
0.1
4.5 V
0.1
0.1
5.5 V
0.1
0.1
3V
0.36
0.44
4.5 V
0.36
0.44
5.5 V
0.36
0.44
V
IOL = 75 mA†
5.5 V
5.5 V
± 0.1
±1
µA
A or B ports
VI = VCC or GND
VO = VCC or GND
5.5 V
± 0.5
±5
µA
VI = VCC or GND,
VI = VCC or GND
8
80
µA
OE or DIR
Control pins
IO = 0
1.65
5.5 V
5V
4.5
Cio
A or B ports
VO = VCC or GND
5V
12
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
pF
pF
2–5
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 2)
TA = 25°C
MIN
MAX
0
MAX
UNIT
0
65
MHz
fclock
tw
Clock frequency
Pulse duration, CLK high or low
7.7
7.7
ns
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
6.5
6.5
ns
1
1
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
65
MIN
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 2)
TA = 25°C
MIN
MAX
fclock
tw
Clock frequency
0
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
Pulse duration, CLK high or low
Hold time, A or B after CLKAB↑ or CLKBA↑
100
MIN
MAX
UNIT
0
100
MHz
5
5
ns
4.5
4.5
ns
1
1
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
65
A or B
B or A
OE
A or B
OE
A or B
CLKBA or CLKAB
A or B
SBA or SAB†
(A or B high)
A or B
SBA or SAB†
(A or B low)
A or B
DIR
A or B
MIN
MAX
65
MHz
1.5
9.1
12.1
1.5
13.8
1.5
10.7
13.4
1.5
14.5
1.5
13
16.4
1.5
18.7
1.5
16.1
20.4
1.5
21.8
1.5
7.9
9.6
1.5
10.3
1.5
7.2
8.9
1.5
9.6
1.5
11.8
15
1.5
17
1.5
13.7
16.8
1.5
18.3
1.5
9.8
12.9
1.5
14.4
1.5
12
14.5
1.5
15.8
1.5
10.7
13.8
1.5
15.4
1.5
12.4
15
1.5
16.4
1.5
13.7
17.1
1.5
19.4
1.5
16.8
21
1.5
23.6
1.5
7.9
9.7
1.5
DIR
A or B
tPLZ
1.5
7.3
9.1
1.5
† These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
10.5
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
2–6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
9.9
ns
ns
ns
ns
ns
ns
ns
ns
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
100
A or B
B or A
OE
A or B
OE
A or B
CLKBA or CLKAB
A or B
SBA or SAB†
(A or B high)
A or B
SBA or SAB†
(A or B low)
A or B
DIR
A or B
DIR
A or B
MIN
MAX
100
UNIT
MHz
1.5
5.5
7.9
1.5
8.8
1.5
6.3
8.9
1.5
9.8
1.5
7.8
10.7
1.5
12
1.5
8.5
11.9
1.5
13.1
1.5
5.9
8.4
1.5
8.9
1.5
5.9
7.7
1.5
8.3
1.5
7
9.7
1.5
11
1.5
8.2
11
1.5
12.2
1.5
5.9
8.4
1.5
9.4
1.5
7.2
9.8
1.5
10.7
1.5
6.3
8.9
1.5
9.9
1.5
7.3
9.9
1.5
11
1.5
8.4
11.2
1.5
12.6
1.5
9.1
12.3
1.5
13.7
1.5
6.3
8.2
1.5
8.7
1.5
5.7
7.5
1.5
8.1
ns
ns
ns
ns
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
Power dissipation capacitance per transceiver
TEST CONDITIONS
Outputs enabled
Outputs disabled
POST OFFICE BOX 655303
pF
CL = 50 pF,
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
59
15
UNIT
pF
2–7
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
500 Ω
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
Timing Input
(see Note B)
0V
tw
50%
th
tsu
VCC
Input
VCC
50%
50%
VCC
50%
50%
Data Input
0V
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
VCC
Input
(see Note B)
50%
50%
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
VCC
VOH
50% VCC
VOL
Output
Waveform 2
S1 at GND
(see Note C)
50%
50%
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
tPLH
tPHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
2–8
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• DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  1998, Texas Instruments Incorporated