TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com 1-A Step Down Converter in 2 x 2 QFN Package Check for Samples: TPS62590 FEATURES DESCRIPTION • • • • • • • The TPS62590 device is a high efficiency synchronous step down converter, optimized for battery powered portable applications. It provides up to 1000-mA output current from batteries, such as single Li-Ion or other common chemistry AA and AAA cells. 1 2 Output Current up to 1000 mA Input Voltage Range from 2.5 V to 5.5 V Output Voltage Accuracy in PWM mode ±2.5% Typ. 15-μA Quiescent Current 100% Duty Cycle for Lowest Dropout Available in a 2 × 2 × 0.8 mm QFN Package For Improved Features Set, See TPS62290 The TPS62590 family operates at 2.25-MHz fixed switching frequency and enters a Power Save Mode operation at light load currents to maintain a high efficiency over the entire load current range. APPLICATIONS • • • • With an input voltage range of 2.5 V to 5.5 V, the device is targeted to power a large variety of portable handheld equipment or POL applications. Portable Handheld WLAN Low Power DSP Supply POL The Power Save Mode is optimized for low output voltage ripple. For low noise applications, the device can be forced into fixed frequency PWM mode by pulling the MODE pin high. In the shutdown mode the current consumption is reduced to less than 1 µA. The TPS62590 allows the use of small inductors and capacitors to achieve a small solution size. The TPS62590 is available in a 2-mm × 2-mm 6-pin QFN package. Empty para 2.5 V to 5.5 V 4 CIN 10mF 2 VIN SW 1 EN FB 3 GND 6 100 L 2.2 mH R1 C1 COUT R2 10mF VI = 5 V 80 0.75 V to VIN 22pF MODE PwrPAD 90 VOUT Efficiency - % TPS62590DRV 5 VI N VI = 4.2 V 70 60 VI = 3.8 V 50 40 30 VOUT = 3.3 V, MODE = GND, 20 10 Typical Application 0 0.0001 0.001 0.01 0.1 IO - Output Current - A 1 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2011, Texas Instruments Incorporated TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. ORDERING INFORMATION (1) TA PART NUMBER OUTPUT VOLTAGE (2) PACKAGE (3) PACKAGE DESIGNATOR ORDERING PACKAGE MARKING TPS62590 adjustable QFN 2 x 2 DRV TPS62590DRV OAL –40°C to 85°C (1) (2) (3) The DRV (2-mm x 2-mm 6-terminal QFN) packages are available in tape on reel. Add R suffix to order quantities of 3000 parts per reel (TPS62590DRVR), and T suffix to order quantities with 250 parts per reel (TPS62590DRVT) . Contact TI for other fixed output voltage options For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Input voltage range (2) VI –0.3 to VIN +0.3, ≤ 7 Voltage range at EN, MODE Peak output current Internally limited HBM Human body model 2 CDM Charge device model 1 Machine model 200 V Maximum operating junction temperature –40 to 125 Tstg Storage temperature range –65 to 150 (2) (3) A kV TJ (1) V –0.3 to 7 Voltage on SW ESD rating (3) UNIT –0.3 to 7 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF capacitor discharged directly into each pin. THERMAL INFORMATION THERMAL METRIC (1) TPS62590 θJA Junction-to-ambient thermal resistance 69.4 θJCtop Junction-to-case (top) thermal resistance 79.8 θJB Junction-to-board thermal resistance 38.7 ψJT Junction-to-top characterization parameter 1.3 ψJB Junction-to-board characterization parameter 39.1 θJCbot Junction-to-case (bottom) thermal resistance 9.0 (1) UNITS DRV (6 PINS) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS MIN VIN NOM MAX UNIT 2.5 5.5 V Output voltage range for adjustable voltage 0.75 VIN V TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C 2 Supply voltage Copyright © 2009–2011, Texas Instruments Incorporated TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for condition VIN = EN = 3.6V. External components CIN = 10μF 0603, COUT = 10μF 0603, L = 2.2μH, refer to parameter measurement information. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VI Input voltage range IO Output current IQ Operating quiescent current ISD Shutdown current UVLO Undervoltage lockout threshold 2.5 5.5 VIN 2.7 V to 5.5 V 1000 VIN 2.5 V to 2.7 V 600 V mA IO = 0 mA, PFM mode enabled (MODE = GND) device not switching, See (1) 15 μA IO = 0 mA, switching with no load (MODE = VIN) PWM operation, VO = 1.8 V, VIN = 3 V 3.8 mA 0.5 μA EN = GND Falling 1.85 Rising 1.95 V ENABLE, MODE VIH High level input voltage, EN, MODE 2.5 V ≤ VIN ≤ 5.5 V 1 VIN VIL Low level input voltage, EN, MODE 2.5 V ≤ VIN ≤ 5.5 V 0 0.4 II Input bias current, EN, MODE EN, MODE = GND or VIN 0.01 1 V V μA POWER SWITCH RDS(on) ILIMF TSD High-side MOSFET on-resistance Low-side MOSFET on-resistance 250 VIN = VGS = 3.6 V, TA = 25°C mΩ 190 Forward current limit MOSFET high-side and low-side VIN = VGS = 3.6 V Thermal shutdown Increasing junction temperature 140 Thermal shutdown hysteresis Decreasing junction temperature 20 1.19 1.4 1.68 A °C OSCILLATOR fSW Oscillator frequency 2.5 V ≤ VIN ≤ 5.5 V 2.25 MHz OUTPUT VO Adjustable output voltage range Vref Reference voltage 0.75 VI 600 VFB(PWM) Feedback voltage MODE = VIN, PWM operation, 2.5 V ≤ VIN ≤ 5.5 V, See (2) VFB(PFM) Feedback voltage PFM mode MODE = GND, device in PFM mode, +1% voltage positioning active, See (1) –2.5% 0% tStart Up Start-up time tRamp VO ramp-up time Time to ramp from 5% to 95% of VO 250 Leakage current into SW pin VI = 3.6 V, VI = VO = VSW, EN = GND, See (3) 0.1 (1) (2) (3) 2.5% 1% Time from active EN to reach 95% of VO Ilkg mV –1 Load regulation V 500 %/A μs μs 1 μA In PFM mode, the internal reference voltage is set to typ. 1.01 × Vref . See the parameter measurement information. For VIN = VO + 1 V In fixed output voltage versions, the internal resistor divider network is disconnected from FB pin. Copyright © 2009–2011, Texas Instruments Incorporated 3 TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com PIN ASSIGNMENTS DRV PACKAGE (TOP VIEW) 1 SW MODE FB 2 3 D 6 PA 5 r we 4 Po GND VIN EN TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION VIN 5 PWR VIN power supply pin. GND 6 PWR GND supply pin EN 4 I SW 1 OUT This is the switch pin and is connected to the internal MOSFET switches. Connect the external inductor between this terminal and the output capacitor. FB 3 I Feedback Pin for the internal regulation loop. Connect the external resistor divider to this pin. In case of fixed output voltage option, connect this pin directly to the output capacitor MODE 2 I MODE pin = high forces the device to operate in fixed-frequency PWM mode. Mode pin = low enables the Power Save Mode with automatic transition from PFM mode to fixed-frequency PWM mode. PwPd ( PowerPAD™) This is the enable pin of the device. Pulling this pin to low forces the device into shutdown mode. Pulling this pin to high enables the device. This pin must be terminated. Must be soldered to achieve appropriate power dissipation. Should be connected to GND. FUNCTIONAL BLOCK DIAGRAM VIN EN Thermal Shutdown Current Limit Comparator Softstart VOUT RAMP CONTROL VIN High Side Reference 0.6 V VREF PFM Comp FB VREF MODE Undervoltage Lockout 1.8 V MODE Error Amp Control Stage Gate Driver Anti Shoot-Through SW VREF Integrator FB Zero-Pole AMP. PWM Comp . GND Low Side Sawtooth Generator 4 2.25 MHz Oscillator Current Limit Comparator GND Copyright © 2009–2011, Texas Instruments Incorporated TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION TPS62590DRV VIN VIN L 2.2 mH EN CIN 10mF VOUT SW FB MODE GND PwPd R1 C1 22pF COUT R2 10mF Table 2. List of Components: COMPONENT REFERENCE PART NUMBER MANUFACTURER VALUE CIN GRM188R60J106M Murata 10 μF, 6.3V. X5R Ceramic COUT GRM188R60J106M Murata 10 μF, 6.3V. X5R Ceramic Murata 22 pF, Ceramic Coilcraft 2.2 μH, 110mΩ C1 L1 LPS3015 R1, R2 Values depending on the programmed output voltage TYPICAL CHARACTERISTICS Table 3. Table Of Graphs FIGURE Efficiency vs Output Voltage VOUT = 1.8 V (Power Save Mode) Figure 1 vs Output Voltage VOUT = 1.8 V (Forced PWM Mode) Figure 2 vs Output Voltage VOUT = 3.3 V (Power Save Mode) Figure 3 vs Output Voltage VOUT = 3.3 V (Forced PWM Mode) Figure 4 vs Output Current VOUT = 1.8 V (Forced PWM Mode) Figure 5 vs Output Current VOUT = 1.8 V (Power Save Mode) Figure 6 vs Output Current VOUT = 3.3 V (Forced PWM Mode) Figure 7 vs Output Current VOUT = 3.3 V (Power Save Mode) Figure 8 PFM Load Transient Figure 9 PFM Line Transient Figure 10 PWM Load Transient Figure 11 PWM Line Transient Figure 12 Typical Operation – PFM Mode Figure 13 Typical Operation – PWM Mode Figure 14 Shutdown Current into VIN vs. Input Voltage Figure 15 Quiescent Current vs Input Voltage Figure 16 Static Drain-Source On-State Resistance vs Input Voltage Output Voltage Transient Behavior Copyright © 2009–2011, Texas Instruments Incorporated Figure 17 Figure 18 5 TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 VI = 2.7 V 90 90 VI = 3.6 V 80 60 VI = 3.3 V 70 Efficiency - % Efficiency - % 70 80 VI = 4.5 V VI = 5 V 50 40 30 10 0 0.0001 0.001 0.01 IO - Output Current - A 0.1 0 0.001 1 0.01 0.1 IO - Output Current - A Figure 2. EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 1 100 90 VI = 5 V 80 VI = 4.2 V 70 VI = 3.8 V Efficiency - % Efficiency - % VOUT = 1.8 V, MODE = VIN, L = 2.2 mH Figure 1. 80 60 50 40 30 10 0.001 0.01 IO - Output Current - A Figure 3. 0.1 VI = 4.2 V VI = 3.8 V VI = 5 V 60 VI = 4.5 V 50 40 VOUT = 3.3 V, MODE = VIN, L = 2.2 mH 30 VOUT = 3.3 V, MODE = GND, L = 2.2 mH 20 6 VI = 4.5 V 40 10 90 0 0.0001 50 20 100 70 VI = 5 V 30 VOUT = 1.8 V, MODE = GND, L = 2.2 mH 20 VI = 2.7 V 60 20 10 1 0 0.001 0.01 0.1 IO - Output Current - A 1 Figure 4. Copyright © 2009–2011, Texas Instruments Incorporated TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 1.9 1.85 VO = 1.8 V, MODE = GND VO = 1.8 V, MODE = VI 1.88 VO - Output Voltage - V VO - Output Voltage - V 1.83 VI = 2.7 V, TA = 25°C 1.81 1.79 VI = 4.5 V, TA = 25°C VI = 3.6 V, TA = 25°C 1.86 PWM Mode PFM Mode, Voltage Positioning On 1.84 1.82 VI = 4.5 V, TA = 25°C VI = 3.6 V, TA = 25°C 1.77 1.8 VI = 2.7 V, TA = 25°C 1.75 0.00001 0.0001 0.001 0.01 IO - Output Current - A 0.1 1.78 0.00001 1 0.001 0.01 IO - Output Current - A Figure 5. Figure 6. OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 0.1 1 3.4 3.35 VO = 3.3 V, MODE = GND VO = 3.3 V, MODE = VI VI = 4.5 V, TA = 25°C 3.36 VO - Output Voltage - V 3.33 VO - Output Voltage - V 0.0001 VI = 4.5 V, TA = 25°C 3.31 VI = 4.2 V, TA = 25°C VI = 3.7 V, TA = 25°C 3.29 VI = 5 V, TA = 25°C VI = 4.2 V, TA = 25°C PFM Mode, Voltage Positioning On PWM Mode 3.28 3.24 3.27 3.25 0.00001 3.32 0.0001 0.001 0.01 IO - Output Current - A Figure 7. Copyright © 2009–2011, Texas Instruments Incorporated 0.1 1 3.2 0.00001 0.0001 0.001 0.01 IO - Output Current - A 0.1 1 Figure 8. 7 TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com PFM LOAD TRANSIENT PFM LINE TRANSIENT VIN 3.6 V, VOUT 1.8 V, IOUT 300 mA to 800 mA, MODE = GND VOUT 100 mV/Div SW 2V/Div VOUT 50 mV/Div VIN 3.6 V, VOUT 1.8 V, IOUT 50 mA to 250 mA, 250 mA MODE = GND IOUT 500 mA/Div 800 mA 300 mA IOUT 200 mA/Div 50 mA Icoil 500 mA/Div Icoil 500 mA/Div Time Base - 20 ms/Div Figure 9. Figure 10. PWM LOAD TRANSIENT PWM LINE TRANSIENT VIN 3.6 V to 4.2 V 500 mV/Div VIN 3.6 V to 4.2 V, 500 mV/Div VOUT = 1.8 V, 50 mV/Div, IOUT = 50 mA, MODE = GND VOUT = 1.8 V, 50 mV/Div, IOUT = 250 mA, MODE = GND Time Base - 100 ms/Div Figure 11. 8 Time Base - 20 ms/Div Time Base - 100 ms/Div Figure 12. Copyright © 2009–2011, Texas Instruments Incorporated TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com TYPICAL OPERATION – PFM MODE TYPICAL OPERATION – PWM MODE VIN 3.6 V, VOUT 1.8 V, IOUT 150 mA, VOUT 20 mV/Div VOUT 10 mV/Div L 2.2 mH, COUT 10 mF 0603 VIN 3.6 V, VOUT 1.8 V, IOUT 10 mA, SW 2 V/Div L 2.2 mH, COUT 10 mF 0603 SW 2 V/Div Icoil 200 mA/Div Icoil 200 mA/Div Time Base - 10 ms/Div Time Base - 10 ms/Div Figure 13. Figure 14. SHUTDOWN CURRENT INTO VIN vs INPUT VOLTAGE QUIESCENT CURRENT vs INPUT VOLTAGE 0.8 20 0.7 18 0.6 IQ – Quiescent Current – mA ISD - Shutdown Current Into VIN − mA EN = GND o TA = 85 C 0.5 0.4 0.3 0.2 o TA = -40oC TA = 25 C MODE = GND, EN = VIN, Device Not Switching o TA = 85 C 16 o TA = 25 C 14 12 o TA = -40 C 10 0.1 0 2.5 3 3.5 4 4.5 VIN − Input Voltage − V Figure 15. Copyright © 2009–2011, Texas Instruments Incorporated 5 5.5 8 2.5 3 3.5 4 4.5 5 5.5 VIN − Input Voltage − V Figure 16. 9 TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com 0.8 High Side Switching 0.7 0.6 o TA = 85 C 0.5 o TA = 25 C 0.4 0.3 0.2 0.1 0 2.5 o TA = -40 C 3 3.5 VIN − Input Voltage − V Figure 17. 10 4 4.5 5 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE RDS(on) - Static Drain-Source On-State Resistance − W RDS(on) - Static Drain-Source On-State Resistance − W STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE 0.4 Low Side Switching 0.35 0.3 o TA = 85 C 0.25 o TA = 25 C 0.2 0.15 0.1 o 0.05 0 2.5 TA = -40 C 3 3.5 4 4.5 5 VIN − Input Voltage − V Figure 18. Copyright © 2009–2011, Texas Instruments Incorporated TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com DETAILED DESCRIPTION OPERATION The TPS62590 step down converter operates with typically 2.25-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converter can automatically enter Power Save Mode and operates then in PFM mode. During PWM operation, the converter use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the High Side MOSFET switch is turned on. The current flows now from the input capacitor via the High Side MOSFET switch through the inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch if the current limit of the High Side MOSFET switch is exceeded. After a dead time preventing shoot through current, the Low-Side MOSFET rectifier is turned on and the inductor current ramps down. The current flows now from the inductor to the output capacitor and to the load. It returns to the inductor through the Low-Side MOSFET rectifier. The next cycle is initiated by the clock signal again turning off the Low-Side MOSFET rectifier and turning on the High-Side MOSFET switch. POWER SAVE MODE The Power Save Mode is enabled with MODE Pin set to low level. If the load current decreases, the converter will enter Power Save Mode operation automatically. During Power Save Mode the converter skips switching and operates with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The converter will position the output voltage +1% above the nominal output voltage typically. This voltage positioning feature minimizes voltage drops caused by a sudden load step. The transition from PWM mode to PFM mode occurs once the inductor current in the Low-Side MOSFET switch becomes zero, which indicates discontinuous conduction mode. During the Power Save Mode the output voltage is monitored with a PFM comparator. As the output voltage falls below the PFM comparator threshold of VOUT nominal +1%, the device starts a PFM current pulse. For this the High-Side MOSFET switch will turn on and the inductor current ramps up. After the On-time expires, the switch is turned off and the Low-Side MOSFET switch is turned on until the inductor current becomes zero. The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered current, the output voltage will rise. If the output voltage is equal or higher than the PFM comparator threshold, the device stops switching and enters a sleep mode with typical 15μA current consumption. If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses are generated until the PFM comparator threshold is reached. The converter starts switching again once the output voltage drops below the PFM comparator threshold. With a fast single threshold comparator, the output voltage ripple during PFM mode operation can be kept small. The PFM Pulse is time controlled, which allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value. Increasing output capacitor values and inductor values will minimize the output ripple. The PFM frequency decreases with smaller inductor values and increases with larger values. The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM mode. The Power Save Mode can be disabled through the MODE pin set to high. The converter will then operate in fixed frequency PWM mode. Dynamic Voltage Positioning This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is active in Power Save Mode and regulates the output voltage 1% higher than the nominal value. This provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. Copyright © 2009–2011, Texas Instruments Incorporated 11 TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com Output voltage Voltage Positioning Vout +1% PFM Comparator threshold Light load PFM Mode Vout (PWM) moderate to heavy load PWM Mode Figure 19. Power Save Mode Operation 100% Duty Cycle Low Dropout Operation The device starts to enter 100% duty cycle Mode once the input voltage comes close the nominal output voltage. To maintain the output voltage, the High-Side MOSFET switch is turned on 100% for one or more cycles. With further decreasing VIN the High-Side MOSFET switch is turned on completely. In this case, the converter offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: VINmin = VOmax + IOmax × RDS(on)max + RL) With: IOmax = maximum output current plus inductor ripple current RDS(on)max = maximum P-channel switch RDS(on). RL = DC resistance of the inductor VOmax = nominal output voltage plus maximum output voltage tolerance Undervoltage Lockout The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery and disables the output stage of the converter. The undervoltage lockout threshold is typically 1.85V with falling VIN. MODE SELECTION The MODE pin allows mode selection between forced PWM mode and Power Save Mode. Connecting this pin to GND enables the Power Save Mode with automatic transition between PWM and PFM mode. Pulling the MODE pin high forces the converter to operate in fixed frequency PWM mode even at light load currents. This allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads. The condition of the MODE pin can be changed during operation and allows efficient power management by adjusting the operation mode of the converter to the specific system requirements. 12 Copyright © 2009–2011, Texas Instruments Incorporated TPS62590 www.ti.com SLVS897B – JANUARY 2009 – REVISED APRIL 2011 ENABLE The device is enabled setting EN pin to high. During the start up time tStart Up the internal circuits are settled. Afterwards, the device activates the soft start circuit. The EN input can be used to control power sequencing in a system with various dc/dc converters. The EN pin can be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply rails. With EN = GND, the device enters shutdown mode. In this mode, all circuits are disabled. In fixed output voltage versions, the internal resistor divider network is disconnected from FB pin. SOFT START The TPS62590 has an internal soft start circuit that controls the ramp up of the output voltage. The output voltage ramps up from 5% to 95% of its nominal value within typical 250μs. This limits the inrush current in the converter during ramp up and prevents possible input voltage drops when a battery or high impedance power source is used. The soft start circuit is enabled within the start up time tStart Up. SHORT-CIRCUIT PROTECTION The High-Side and Low-Side MOSFET switches are short-circuit protected with maximum switch current = ILIMF. The current in the switches is monitored by current limit comparators. Once the current in the High-Side MOSFET switch exceeds the threshold of its current limit comparator, it turns off and the Low-Side MOSFET switch is activated to ramp down the current in the inductor and High-Side MOSFET switch. The High-Side MOSFET switch can only turn on again, once the current in the Low-Side MOSFET switch has decreased below the threshold of its current limit comparator. THERMAL SHUTDOWN As soon as the junction temperature TJ exceeds 140°C (typical) the device goes into thermal shutdown. In this mode, the High-Side and Low-Side MOSFETs are turned-off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis. Copyright © 2009–2011, Texas Instruments Incorporated 13 TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com APPLICATION INFORMATION L 2.2 mH TPS62590DRV 5 VIN 2.5 V to 5.5 V 4 CIN 10mF 2 VIN SW EN FB MODE GND VOUT =1.8V 1 3 R1 360kΩ Up to 1A C1 22pF R2 180kΩ 6 PwrPAD COUT 10mF Figure 20. TPS62590DRV Adjustable 1.8 V L 2.2 mH TPS62590DRV 5 VIN 3.3 V to 5.5 V 4 CIN 10mF 2 VIN SW EN FB MODE GND PwrPAD VOUT =3.3V 1 3 R1 820kΩ I OUT,max =1A C1 22pF 6 R2 182kΩ COUT 10mF Figure 21. TPS62590DRV Adjustable 3.3 V OUTPUT VOLTAGE SETTING The output voltage can be calculated to: æ R1ö÷ V OUT = VREF x çç1 + ÷ çè R2 ø÷ (1) with the internal reference voltage VREF = 0.6V typically. To minimize the current through the feedback divider network, R2 should be 180 kΩ or 360 kΩ. The sum of R1 and R2 should not exceed ~1MΩ, to keep the network robust against noise. An external feed forward capacitor C1 is required for optimum load transient response. The value of C1 should be in the range between 22pF and 33pF. Route the FB line away from noise sources, such as the inductor or the SW line. OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) The TPS62590 is designed to operate with inductors in the range of 1.5μH to 4.7μH and with output capacitors in the range of 4.7μF to 22μF. The part is optimized for operation with a 2.2μH inductor and 10μF output capacitor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. For stable operation, the L and C values of the output filter may not fall below 1μH effective inductance and 3.5μF effective capacitance. Inductor Selection The inductor value has a direct effect on the ripple current. The selected inductor has to be rated for its dc resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO. The inductor selection has also impact on the output voltage ripple in PFM mode. Higher inductor values will lead to lower output voltage ripple and higher PFM frequency, lower inductor values will lead to a higher output voltage ripple but lower PFM frequency. Equation 2 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 3. This is recommended because during heavy load transient the inductor current will rise above the calculated value. 14 Copyright © 2009–2011, Texas Instruments Incorporated TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com V 1 * OUT V DI L + VOUT L I L max + I out max ) IN f DI L (2) 2 (3) With: f = Switching Frequency (2.25MHz typical) L = Inductor Value ΔIL = Peak to Peak inductor ripple current ILmax = Maximum Inductor current A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. Accepting larger values of ripple current allows the use of low inductance values, but results in higher output voltage ripple, greater core losses, and lower output current capability. The total losses of the coil have a strong impact on the efficiency of the dc/dc conversion and consist of both the losses in the dc resistance (R(DC)) and the following frequency-dependent components: • The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) • Additional losses in the conductor from the skin effect (current displacement at high frequencies) • Magnetic field losses of the neighboring windings (proximity effect) • Radiation losses Table 4. List of Inductors 3 DIMENSIONS [mm ] INDUCTOR TYPE SUPPLIER 3 × 3 × 1.5 LPS3015 Coilcraft 3 x 3 x 1.5 LQH3NPN2R2NM0 MURATA 3.2 x 2.6 x 1.2 MIPSA3226D2R2 FDK Output Capacitor Selection The advanced fast-response voltage mode control scheme of the TPS62590 allows the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At nominal load current, the device operates in PWM mode and the RMS ripple current is calculated as: V 1 * OUT V I RMSC OUT + VOUT L IN f 1 2 Ǹ3 (4) At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: V 1 * OUT V DV OUT + VOUT L IN f ǒ8 1 Cout f Ǔ ) ESR (5) At light load currents the converter operates in Power Save Mode and the output voltage ripple is dependent on the output capacitor and inductor value. Larger output capacitor and inductor values minimize the voltage ripple in PFM mode and tighten dc output accuracy in PFM mode. Copyright © 2009–2011, Texas Instruments Incorporated 15 TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com Input Capacitor Selection The buck converter has a natural pulsating input current; therefore, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most applications, a 10-μF ceramic capacitor is recommended. The input capacitor can be increased without any limit for better input voltage filtering. Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on the input can induce ringing at the VIN pin. The ringing can couple to the output and be mistaken as loop instability or could even damage the part by exceeding the maximum ratings. Table 5. List of Capacitor CAPACITANCE TYPE SIZE SUPPLIER 10μF GRM188R60J106M69D 0603 1.6x0.8x0.8mm3 Murata LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Connect the GND Pin of the device to the Power Pad of the PCB and use this Pad as a star point. Use a common Power GND node and a different node for the Signal GND to minimize the effects of ground noise. Connect these ground nodes together to the Power Pad (star point) underneath the IC. Keep the common path to the GND PIN, which returns the small signal components and the high current of the output capacitors as short as possible to avoid ground noise. The FB line should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SW line). 16 Copyright © 2009–2011, Texas Instruments Incorporated TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com VOUT R2 GND C1 R1 COUT CIN VIN L G N D U Figure 22. Layout Copyright © 2009–2011, Texas Instruments Incorporated 17 TPS62590 SLVS897B – JANUARY 2009 – REVISED APRIL 2011 www.ti.com REVISION HISTORY NOTE: Page numbers of current version may differ from previous versions. Changes from Original (January 2009) to Revision A Page • Deleted "High Efficiency Step-down Converter" from Features ........................................................................................... 1 • Deleted "Adjustable Output Voltage Range from 0.75 V to VIN" from Features ................................................................... 1 • Deleted "2.25 MHz Fixed-Frequency Operation" from Features .......................................................................................... 1 • Deleted "Power Save Mode at Light Load Currents" from Features .................................................................................... 1 • Deleted "Voltage Positioning at Light Loads" from Features ................................................................................................ 1 • Added "For Improved Features Set, See TPS62290" to Features ....................................................................................... 1 • Deleted "Cell Phones, Smart-phones" from Applications ..................................................................................................... 1 • Deleted "PDAs, Pocket PCs" from Applications ................................................................................................................... 1 • Deleted "Portable Media Players" from Applications ............................................................................................................ 1 • Changed "Description" paragraph to clarify device operation. ............................................................................................. 1 • Changed Tape and Reel ordering information ..................................................................................................................... 2 • Added MIN and MAX values to ILIMF specification ................................................................................................................ 3 Changes from Revision A (November 2009) to Revision B • 18 Page Replaced the DISSIPATION RATINGS with the THERMAL INFORMATION Table ............................................................ 2 Copyright © 2009–2011, Texas Instruments Incorporated PACKAGE MATERIALS INFORMATION www.ti.com 16-Sep-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS62590DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS62590DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Sep-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62590DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS62590DRVT SON DRV 6 250 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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