TI TLC5903

TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
D
D
D
D
D
D
80 mA x 16 Bits and 120 mA x 8 Bits
Drive Capability and Output Counts
5 mA to 80 mA/10 mA to 120 mA Constant
Current Output Range
Constant Currency Accuracy of ±4%
(Maximum Error Between Bits)
Constant Current Output Terminals
– 0.4 V (Output Current 0 to 40 mA)
– 0.7 V (Output Current 40 to 80 mA)
256 Gray Scale Display With Pulse Width
Control 256 Steps
Brightness Adjustment
– Output Current Adjustment for 32 Steps
(Adjustment for Brightness Deviation
Between LEDs)
– 8 Steps Brightness Control by 8 Times
Speed Gray Scale Control Clock
(Brightness Adjustment for Panel)
D
D
D
D
D
D
D
D
D
D
Protection
– WDT Function
– TSD Function
Clock Synchronized 8-Bit Parallel Input
Anode Common LED Type Applied
CMOS Input Signal Level
(Schmitt-Triggered Input for All Input
Terminals)
4.5 V to 5.5 V Power Supply Voltage
15 V Maximum Output Voltage
15 MHz Maximum Data Transfer Rate
8 MHz Maximum Gray Scale Clock
Frequency
–20°C to 85°C Operating Free-Air
Temperature Range
100-Pin HTQFP Package
(PD = 4.7 W, TA = 25°C)
description
The TLC5903 is a constant current driver that incorporates shift register, data latch, and constant current
circuitry with an adjustable current value and a 256 gray scale display that uses pulse width control. The output
current can be selected at a maximum of 80 mA with 16 bits or 120 mA with 8 bits. The current value of the
constant current output is set by one external register. After this device is mounted on a printed-circuit board
(PCB), the brightness deviation between LEDs (ICs) can be adjusted by using an external data input. The
brightness control for the panel can be adjusted using the brightness adjustment circuitry. Moreover, the device
incorporates watchdog timer (WDT) circuitry, which turns the constant current output off when the scan signal
is stopped during the dynamic scanning operation, and thermal shutdown (TSD) circuitry, which turns the
constant current output off when the junction temperature exceeds the limit.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
DIN3
DIN2
DIN1
DIN0
GSCLK
BLANK
NC
RSEL
DCLK
ENABLE
NC
WDT
LATCH
DOWN
NC
NC
BOUT
GSOUT
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
HTQFP PACKAGE
(TOP VIEW)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
NC
NC
OUT4
NC
GNDLED
NC
OUT5
OUT6
NC
GNDLED
NC
OUT7
OUT8
NC
GNDLED
NC
OUT9
OUT10
NC
GNDLED
NC
OUT11
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DIN4
DIN5
DIN6
DIN7
TS_ENA
VCCLOG
NC
MODE
GNDLOG
BC_ENA
NC
OUT0
TEST1
NC
GNDLED
NC
NC
OUT1
OUT2
NC
GNDLED
NC
NC
NC
OUT3
2
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• DALLAS, TEXAS 75265
NC
DOUT5
DOUT6
DOUT7
NC
VCCANA
NC
GNDANA
WD_CAP
PV CC
IREF
OUT15
TEST2
NC
GNDLED
NC
NC
OUT14
OUT13
NC
NC
GNDLED
NC
NC
OUT12
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
functional block diagram
Shift Register and Data Latch
BC_ENA
RSEL
Brightness Control
Register
DIN0
DOUT0
DIN7
DOUT7
Enable
DCLK
DCLK
Controller
16 × 8 Bits
Shift Register
Data Latch
LATCH
MODE
GSCLK
BLANK
TS_ENA
GSOUT
8 Bits
Gray Scale
Counter
BOUT
16 × 8 Bits
Comparator
TSD
WDT
DOWN
WDT
WD_CAP
IREF
Current Reference
Circuit
16 Bits
Constant Current Driver
OUT0
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• DALLAS, TEXAS 75265
OUT15
3
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
functional block diagram for shift register and data latch
BC_ENA
1 × 8 Bits Shift Register
(Brightness Control)
1 × 8 Bits Latch
(Brightness Control)
To
8 Bits Gray Scale Counter
Current Reference
Circuitry
DIN(0–7)
RSEL
ENABLE
DCLK
16 × 8 Bits
Shift Register
(Gray Scale Data))
DCLK
Controller
Q0
Q7
Q15
MODE
16 × 8 Bits
Data Latch
(Gray Scale Data))
Q0
Q15
LATCH
Comparator
Comparator
Constant Current Driver
Comparator
Control Line
Data (8 Bits)
4
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• DALLAS, TEXAS 75265
DOUT(0–7)
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
equivalent input and output schematic diagrams
Input
VCCLOG
INPUT
GNDLOG
DOUT (0–7), GSOUT, BOUT
VCCLOG
OUTPUT
GNDLOG
DOWN
DOWN
GNDLOG
OUTn
OUTn
GNDLED
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• DALLAS, TEXAS 75265
5
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BC_ENA
85
I
Brightness control enable. When BC_ENA is low, the brightness control function is disabled. At
this time, the brightness control latch is reset to 1Fh. Output current value is 100% of the setting
value by an external resistor and the frequency division ratio of GSCLK is 1/1.
BLANK
68
I
Blank (Light off). When BLANK is high, all the output of the constant current driver is turned off.
All the output is turned on (LED on) synchronizing to the falling edge of GCLK after the next rising
edge of GCLK when BLANK goes from high to low.
57
O
Blank signal delay. BOUT is output with an addition of delay time to BLANK.
BOUT
CONDUCTIVE
PAD
package
surface
Heat sink pad
65
I
Clock input for data transfer. The input data of DIN is synchronized to the rising edge of DCLK, and
transferred to DOUT. DCLK is valid at the rising edge after ENABLE goes low.
DIN7–DIN0
70,71,72,73,
76,77,78,79
I
Input for shift register for both gray scale data and brightness control. It is 8 bits parallel data.
DOUT0–DOUT7
47,48,49,51,
52,53,54,55
O
Output for shift register for both gray scale data and brightness control.
DOWN
60
O
Shutdown. DOWN is configured as an open collector. It goes low when the constant current output
is shut down by the WDT or TSD function.
ENABLE
64
I
Data transfer enable. When ENABLE is high, data is not transferred.
GNDANA
43
GNDLED
5,10,15,20,29,
36,90,96
GNDLOG
84
GSCLK
69
I
Clock input for gray scale. The gray scale display is accomplished by lighting the LED until the
number of GSCLK counted is equal to the data latched.
GSOUT
56
O
Clock delay for gray scale. GSOUT is output with the addition of delay time to GSCLK
IREF
40
I
Constant current control setting. LED current is set to the desired value by connecting an external
resistor between IREF and GND. The 38 times current is compared to current across an external
resistor sink on the output terminal.
LATCH
61
I
Latch. When LATCH is high, data on the shift register goes through latch. When LATCH is low, data
is latched. Accordingly, if data on the shift register is changed during LATCH high, this new value
is latched.
MODE
83
I
8/16 bits select. When MODE is high, 16 bits output is selected. When MODE is low, 8 bits output
is selected.
87,93,94,100,
3,7,8,12,13,17,
18,22,26,32,
33,39
O
Constant current output
DCLK
OUT0–OUT15
Analog ground. (Internally connected to GNDLOG and GNDLED)
LED driver ground (Internally connected to GNDANA and GNDLOG)
Logic ground. (Internally connected to GNDANA and GNDLED)
PVCC
41
RSEL
66
I
Shift register latch switching. When RSEL is low, the shift register and latch for gray scale are
selected. When RSEL is high, the shift register and latch for brightness control are selected.
88,38
I
TEST. Factory test terminal. TEST should be connected to GND for normal operation.
TS_ENA
80
I
TSD (Thermal shutdown) enable. When TS_ENA is high, TSD is enabled. When TS_ENA is low,
TSD is disabled.
VCCANA
45
Analog power supply voltage
VCCLOG
81
Logic power supply voltage
TEST1, TEST2
6
LED driver power supply voltage
WD_CAP
42
I
WDT detection time adjustment. The capacitor for WDT detection time adjustment is connected
between WD_CAP and GND. When WD_CAP is directly connected to GND, the WDT function
is disabled.
WDT
62
I
WDT scan input. By applying a scan signal to this terminal, the scan signal can be monitored and
constant current output can be turned off. LED is protected from damage from burning when the
scan signal is stopped during the constant period. The scan signal should be applied to this
terminal by connecting WD_CAP to GND even though no WDT function is used.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
Function Tables
Truth Table (Data)
BC_ENA
ENABLE
DCLK
RSEL
LATCH
MODE
L
X
X
X
X
X
No change
DOUT0 – DOUT7
Data latch for brightness control is set to 1Fh.
OPERATION/FUNCTION
X
H
X
X
X
X
No change
Data transfer for gray scale and brightness
control does not occur.
X
L
↑
H
X
X
Shift register for
brightness control
Data of DIN0 to DIN7 is clocked into the shift
register for brightness control.
X
L
↑
L
X
H
Data for shift register
before 16 bytes (written
before 16 times)
Data of DIN0 to DIN7 is clocked into the first byte
of the shift register for gray scale data.
X
L
↑
L
X
L
Shift register for gray
scale before 8 bytes
(written before 8 times)
Data of DIN0 to DIN7 is clocked into the first byte
of the shift register for gray scale data.
H
X
X
H
H
X
No change
Shift register for brightness control goes through
data latch for brightness control.
X
X
X
L
H
X
No change
Shift register for gray scale goes through data
latch for gray scale.
H
X
X
X
L
X
No change
The value for shift register selected by RSEL is
latched.
Truth Table (Display/Protection)
BLANK
GSCLK
MODE
WDT
WD_CAP
TS_ENA
H
X
X
X
X
X
Off
Hi–Z
X
16 bits operation mode. The output is turned on if
all the gray scale data is not zero on the falling edge
of GCLK after next rising edge of GCLK when
BLANK goes from high to low. Each output turns off
on the falling edge of GSCLK, corresponding to
each gray scale data.
Hi–Z
Hi–Z
L
L
↓
H
X
X
OUT0~15
DOWN
L
↓
L
X
X
X
8 bits operation mode. The output is turned on if all
the gray scale data is not zero on the falling edge
of GCLK after next rising edge of GCLK when
BLANK goes from high to low. Each output turns off
on the falling edge of GSCLK corresponding to
each gray scale data.
L
X
X
CLK
capacitor
X
Turn off if the level of WDT is not changed within the
time set by a capacitor connected to WD_CAP.
L
X
X
CLK
L
X
WDT function is disabled.
Hi–Z
L
X
X
CLK
H
X
WDT function is disabled.
Hi–Z
L
X
X
X
X
H
Turn off if junction temperature exceeds the limit.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
L
OPERATION/
FUNCTION
Recover when
the level of
WDT changes.
Set TS_ENA to
low for recovery
7
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
absolute maximum ratings (see Note 1)†
Logic supply voltage, VCC(LOG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Supply voltage for constant current circuit, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Analog supply voltage, VCC(ANA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Output current (DC), IOL(C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 mA
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC(LOG) 0.3 V
Output voltage range, VO(OUTn), VO(BOUT) and VO(GSOUT) . . . . . . . . . . . . . . . . . –0.3 V to VCC(LOG) 0.3 V
Output voltage range, VO(OUTn) and VO(DOWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.3 V
Continuous total power dissipation at (or below) TA = 25_C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 W
Operating free air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GNDLOG terminal.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C.
recommended operating conditions
dc characteristics over recommended ranges of operating free-air temperature,
VCC(LOG) = VCC(ANA) = PVCC = 4.5 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Logic supply voltage, VCC(LOG)
4.5
5
5.5
V
Supply voltage for constant current circuit,
PVCC
4.5
5
5.5
V
Analog power supply, VCC(ANA)
4.5
5
5.5
V
–0.3
0
0.3
V
–0.3
0
0.3
V
VCC(LOG)
0.2 VCC(LOG)
V
Voltage between VCC, V(DEF1)
(see Note 3)
Voltage between GND, V(DEF2)
(see Note 3)
V(DEF1) =
VCC(LOG) – VCC(ANA)
VCC(LOG) – PVCC, VCC(ANA) – PVCC
V(DEF2) =
GND(LOG) – GND(ANA)
GND(LOG) – GNDLED, GND(ANA) –
GND(LED)
High-level input voltage, VIH
0.8 VCC(LOG)
Low-level input voltage, VIL
High-level output current, IOH
Low-level output current,, IOL
Constant output current, IOL(C)
GND(LOG)
VCC(LOG) = 4.5 V, DOUT0 to DOUT7,
BOUT, GSOUT
–1
VCC(LOG) = 4.5 V, DOUT0 to DOUT7,
BOUT, GSOUT
1
VCC(LOG) = 4.5 V, DOWN
OUT0 to OUT15
NOTE 3: Each voltage is supplied by a single power supply, not a separated power supply.
8
Á
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
mA
5
5
mA
80
mA
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
recommended operating conditions (continued)
ac characteristics over recommended ranges of operating free-air temperature,
VCC(LOG) = VCC(ANA) = PVCC = 4.5 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DCLK clock frequency,
frequency f(DCLK)
MIN
TYP
15
At cascade operation
10
DCLK pulse duration (high or low level), tw(h)/tw(l)
20
8
Frequency division ratio 1/1, TA = 25°C,
VCC(LOG) = VCC(ANA) = PVCC = 5 V
GSCLK pulse duration (high or low level), tw(h)/tw(l)
15
LAT pulse duration (high or low level) tw(h)
50
LATCH
MHz
ns
50
Rise/fall time, tr/tf
MHz
ns
5
WDT pulse duration (high or low level), tw(h)/tw(l)
MHz
MHz
50
WDT clock frequency, f(WDT)
UNIT
ns
Frequency division ratio 1/1
GSCLK clock frequency, f(GSCLK)
MAX
At single operation
ns
100
ns
Setup time,, tsu
DINn – DCLK
LATCH – DCLK
BLANK – GSCLK
ENABLE – DCLK
LATCH – GSCLK
RSEL – DCLK
RSEL – LATCH
10
15
20
15
10
10
20
ns
Hold time,, tn
DINn – DCLK
LATCH – DCLK
ENABLE – DCLK
RSEL – DCLK
RSEL – LATCH
15
30
20
20
20
ns
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• DALLAS, TEXAS 75265
9
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
electrical characteristics, MIN/MAX: VCC(LOG) = VCCANA = PVCC = 4.5 V to 5.5 V, TA = –20°C to 85°C
TYP: VCC(LOG) = VCC(ANA) = PVCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level
II
TEST CONDITIONS
IOH = –1 mA, DOUT0 to DOUT7,
GSOUT, BOUT
Input current
Supply current (analog)
Supply current (constant current driver)
IOL(C1)
Constant output current
IOL(C2)
Data transfer,
GSCLK = 1 MHz
DCLK = 15 MHz,
LED turns on,
UNIT
V
0.5
V
0.5
±1
Input signal is static, TS_ENA = H,
WD_CAP = OPEN
I(LOG)
MAX
VCC(LOG)
–0.5V
IOL = 5 mA DOWN
VI = VCC(LOG) or GND(LOG)
Supply current (logic)
I(PVCC)
TYP
IOL = 1 mA, DOUT0 to DOUT7, GSOUT,
BOUT
output voltage
g
I(OG)
I(ANA)
MIN
µA
1
mA
18
30
R(IREF) = 590 Ω
3
5
LED turns off,
R(IREF) = 590 Ω
3
5
R(IREF) = 1180 Ω,
LED turn off
15
20
R(IREF) = 590 Ω,
LED turn off
30
40
VO = 1 V,
R(IREF) = 1180 Ω,
16 bits output turns on
25
35
VO = 1 V,
R(IREF) = 590 Ω,
16 bits output turns on
50
70
mA
mA
VO = 1 V,
R(IREF) = 1180 Ω
V(IREF) = 1.24 V,
35
40
45
mA
VOUT = 1 V,
R(IREF) = 590 Ω
V(IREF) = 1.24 V,
70
80
90
mA
R(IREF) = 590 Ω,
10
µA
Ilkg
Constant output leakage current
VO = 15 V,
LED turns off
∆IOL(C)
Constant output current error between bit
VCC(LOG) = VCC(ANA) = PVCC = 5 V,
V(IREF) = 1.24 V,
R(IREF) = 590 Ω,
All bits turns on,
VO= 1 V
±1%
±4%
I∆OL(C1)
Changes in constant output current
depend on supply voltage
V(IREF) = 1.24 V
±1%
±4%
V
I∆OL(C2)
Changes in constant output current
depend on output voltage
V(IREF) = 1.24 V,
R(IREF) = 1180 Ω,
1 bit output turns on, VO = 1 V to 3 V
±1%
±2%
V
T(tsd)
TSD detection temperature (thermal
shutdown circuit)
Junction temperature
150
160
170
°C
T(wdt)
WDT detection time (watchdog timer
circuit)
No external capacitor
1
3
8
ms
V(IREF)
Voltage reference
BC_ENA = L,
10
POST OFFICE BOX 655303
R(IREF) = 590 Ω
• DALLAS, TEXAS 75265
1.24
V
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
switching characteristics, CL = 15 pF
PARAMETER
TEST CONDITIONS
MIN
DOUT
tr
tf
OUT
Rise time
Propagation delay time
30
250
13
30
BOUT
13
30
DOUT
8
20
150
GSOUT
10
25
BOUT
10
25
8
15
BLANK ↑ – OUT0
350
500
GSCLK ↓ – OUT0
350
500
OUTn+1 – OUTn
td
MAX
12
GSOUT
OUT
Fall time
TYP
DCLK ↑ – DOUT
15
30
50
GSCLK – GSOUT
10
25
50
BLANK – BOUT
10
25
50
UNIT
ns
ns
ns
timing requirements
100%
90%
VIH OR VOH
100%
VIH OR VOH
50%
10%
0%
VIL OR VOL
tr
0%
VIL OR VOL
tf
td
100%
VIH
100%
VIH OR VOH
50%
50%
0%
VIL
tw(h)
0%
VIL OR VOL
tw(l)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
PRINCIPLES OF OPERATION
constant current output selection by user (80 mA × 16 bits or 120 mA × 8 bits)
When the MODE terminal is set to high, the output is selected as 80 mA × 16 bits. When the MODE terminal
is set to low, the output is selected as 120 mA × 8 bits. By this setting, the internal shift register and latch are
changed. Note that two constant output terminals, such as OUT0 to OUT1 and OUT2 to OUT3, should be tied
when the 8-bits output is selected.
MODE
OUTPUT
H
80 mA x 16 bits
L
120 mA x 8 bits
setting for constant current value
On the constant current output terminals (OUT0 to OUT15), approximately 38 times the current which flows
through the external resistor, R(IREF) (connected between IREF and GND), can flow. The external resistor value
is calculated using the following equation:
^
I (OUTn)(mA)
38 1.24(V)
R (IREF)(k )
W
(1)
More current flows if IREF is connected directly to GND.
shift register latch for gray scale data
The shift register latch for the gray scale data is configured with 8 × 8 bits each at the 8 bit mode, and configured
with 16 x 8 bits each at the 16-bit mode. By setting RSEL to low, the shift register latch for the gray scale data
is selected. The data structure shows that DIN0 corresponds to LSB, and DIN7 to MSB. This results in 28 = 256
steps gray scale. The latched data is compared to GSCLK (clock for gray scale) counts, and the constant current
output continues to turn on until these values are equal.
shift register latch for brightness control
The shift register latch for brightness control is 1 × 8 bits each. The data input terminal and latch terminal are
common to the shift register latch for the gray scale data. By setting RSEL to low, the shift register latch for the
gray scale data is selected, and by setting RSEL to high, the shift register latch for brightness control is selected.
If the brightness control function is not used, the BC_ENA terminal should be pulled low. Since the brightness
control latch is reset to the initial value of 00011111h, it is not necessary to write data to the shift register latch
for brightness control. When power is up, latch data is undetermined. Data should be written to the shift register
latch when the brightness control function is used. Also, rewriting the latch value for brightness control is
inhibited when the LED is turned on.
RSEL
12
SHIFT REGISTER LATCH SELECTED
L
Shift register latch for gray scale data
H
Shift register latch for brightness control
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
PRINCIPLES OF OPERATION
write data to both shift register latches
The shift register latch is selected using the RSEL terminal. The data input method is the same for both shift
register latches. The data is applied to DIN0 to DIN7 input terminal in 8-bits data and transferred synchronizing
to DCLK. The data of DIN0 to DIN7 is transferred by the directions from OUT0 to OUT15 synchronizing to DCLK.
The shift register for brightness control is 1-bit length resulting in one time of DCLK input. The shift register for
the gray scale data is 8-bits length at 8-bit mode resulting in eight times DCLK, and the 16-bit length at 16-bit
mode results in 16 times the DCLK input. At the number of DCLK input for each case, output data appears on
DOUT0 to DOUT7. When LATCH goes from low to high, data is latched internally. Then, when LATCH goes
low, data is held. RSEL switching should be done when DCLK and LATCH are low.
brightness control latch configuration
The brightness control latch is configured as DIN0 corresponds to LSB, and DIN7 to MSB. The lower 5 bits are
assigned for output current adjustment, and the upper 3 bits are for a frequency division ratio setting of GSCLK.
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
MSB
⋅⋅⋅⋅
⋅⋅⋅⋅
⋅⋅⋅⋅
⋅⋅⋅⋅
⋅⋅⋅⋅
⋅⋅⋅⋅
LSB
0†
0
0
1
1
1
1
1
Frequency division ratio setting of GSCLK
Output current setting
† BC_ENA is low.
output current adjustment – brightness adjustment between ICs
By using the lower 5 bits of the brightness control latch, the output current can be adjusted in 32 steps. When
the output current is set to 100% of the external resistor at 11111h of the latched value, it is adjusted as 1 step
or 32 steps of 1.6% current ratio between 100% and 51.6%. By using this function, the brightness control
between modules (ICs) can be adjusted, sending the desired data externally even if ICs are mounted on a PCB.
When BC_ENA is pulled low, the latch is reset to the initial value of 00011111h, and the output current is set to
100%.
CODE
CURRENT RATIO (%)
20 (mA)
80 (mA)
MSB 00000 LSB
51.6
10.3
41.3
VIREF (TYP)
0.64
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
11110
98.4
19.7
78.7
1.22
11111†
100
20.0
80.0
1.24
† BC_ENA is low.
frequency division ratio setting for GSCLK(clock for gray scale) – panel brightness adjustment
By using the upper 3 bits of the brightness control latch, GSCLK can be divided into a frequency division ratio
of 1/1 to 1/8. If GSCLK is set to 8 times the speed of the frequency (256 × 8 = 2048) during the horizontal scanning
time, the brightness can be adjusted to 8 steps by selecting the frequency division ratio. Thus, the total panel
brightness can be adjusted at once and applied to the brightness of day or night. When BC_ENA is pulled low,
GSCLK is not divided. When BC_ENA is pulled high, the brightness can be adjusted as shown in the following
table.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
PRINCIPLES OF OPERATION
frequency division ratio setting for GSCLK(clock for gray scale) – panel brightness adjustment
(continued)
CODE
FREQUENCY DIVISION RATIO
RELATIVE BRIGHTNESS RATIO
(%)
MSB 000 LSB†
1/1
12.5
001
1/2
25.0
010
1/3
37.5
011
1/4
50.0
100
1/5
62.5
101
1/6
75.0
110
1/7
87.5
111
1/8
100
† BC_ENA is low.
constant output current operation
The constant current output turns on (sink constant current) if all the gray scale data latched into the gray scale
latch is not zero on the falling edge of GCLK after the next rising edge of GCLK when BLANK goes from high
to low. After that, the number of the falling edge is counted by the 8-bit gray scale counter. Output counted that
corresponds to the gray scale data is turned off (stop to sink constant current). If the shift register for gray scale
is updated during LATCH high, data on the gray scale data latch is also updated, affecting the number of gray
scale constant current output. Accordingly, during the on state of constant current output, LATCH is kept to low
and the gray scale data latch is held. When unconnected constant current output terminals exist, the operation
is complete after writing zero (data for LED turn off) to the corresponding gray scale data latch. If this action is
not completed, the supply current (I(PVCC)) in the constant current driver portion increases.
protection
This device incorporates WDT and TSD functions. In the WDT or TSD functions, the current output is stopped
(Logic portion is still operating). By monitoring the DOWN terminal, these failures are detected immediately.
Since DOWN output is configured as an open collector, outputs of multiple ICs are brought together.
WDT
When the scan signal is stopped during a fixed period in the dynamic scanning operation, the constant current
output is turned off, preventing the LED from burning damage. The time detected can be set using the external
capacitor(C1). The typical value is approximately 3 ms without a capacitor, 33 ms with a 1000 pF capacitor, and
300 ms with a 0.01 µF capacitor. Once the scan signal is applied again, the abnormal status is released and
normal operation is resumed. During static operation, the WDT function is disabled, connecting WD_CAP to
GND. The scan signal should be applied to the WDT terminal even though the WDT function is not used.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
PRINCIPLES OF OPERATION
WDT Operational Time
T (ms) ≅ 3+0.03 × C1 (pF)
3000
t – Time – ms
TLC5903
Scan Signal
300
WDT
WD_CAP
C1
33
Figure 2. WDT Usage Example
3
103
0
104
105
C1 – External Capacitor – pF
Figure 1. WDT Operational Time
TSD (thermal shutdown)
When the junction temperature exceeds the limit, TSD functions and turns the constant current output off. When
TSD is used, TS_ENA is pulled high. When TSD is not used, TS_ENA is pulled low. To recover to normal
operation, the power supply is turned off or TS_ENA is pulled low.
noise reduction
concurrent switching noise reduction
The concurrent switching noise has the potential to occur when multiple outputs turn on or off at the same time.
To prevent this noise, the device has delay output terminals such as GSOUT, BOUT for GSCLK, and BLANK
respectively. Connecting these outputs to the GSCLK and BLANK terminals of the next stage IC allows
differences in the switching time between ICs to be made. When GSCLK is output to GSOUT through the device,
duty is changed, so that the number of stages to be connected will be limited to a maximum of 10 at
GSCLK = 4 MHz.
output slope
The on and off time of the constant current output at an output current of 80 mA is approximately 150 ns and
250 ns respectively. It is effective in reducing the concurrent switching noise that occurs when multiple outputs
turn on or off at the same time.
delay between constant current output
The constant current output has a delay time of approximately 5 ns by two outputs. This means approximately
35 ns delay time exists between OUT0 and OUT15. This time difference by delay is effective for reduction of
concurrent switching noise as well as output slope. This delay time has the same value at 8-bits or 16-bits
operation mode.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
PRINCIPLES OF OPERATION
noise reduction (continued)
power supply
VCCLOG, VCCANA, and PVCC are supplied by a single power supply to minimize voltage differences between
these terminals.
The bypass capacitor is located between power supply and GND to eliminate the variation of power supply
voltage.
GND
Although GNDLOG, GNDANA, and GNDLED are internally tied together, these terminals should be externally
connected to reduce noise influence.
heat sink pad
4.7
3.2
2.4
1.40
0
–20
Output Voltage (Constant Current) – V
PD – Total Power Dissipation – W
The heat sink pad should be connected to GND to eliminate the noise influence since it is connected to the
bottom side of the IC chip. Also, the desired thermal effect is obtained by connecting this pad to the PCB pattern
with better thermal conductivity.
0
25
85
TA – Free-Air Temperature – °C
NOTES: A. IC is mounted on PCB.
PCB size: 102 × 76 × 1.6 [mm3], four layers with internal two layer having plane. The thermal pad is soldered to PCB pattern of
10 mm2. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C.
VCCLOG = VCCANA = PVCC = 5 V, IOL(C) = 80 mA, ICC is typical value
B. Consider thermal characteristics when selecting the material for the PCB, since the temperature will rise around the thermal pad.
Figure 3. Power Rating – Free Temperature Range
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
PRINCIPLES OF OPERATION
90
80
Conditions : V O
IOL(C) – mA
70
+ 1 V, V
V
(mA) 0
R
(kW) 0
I
(IREF)
I OL(C)
60
40
(IREF)(V)
W
(IREF)(k
R (IREF)
50
+ 1.24 V
38
47
OL(C)(mA)
NOTE: The output current is at 16 bit output.
When at 8-bit output, it will be the sum current of two
outputs. This sum current should be set up with the range
of 10 mA to 120 mA. The resistor, R(IRF), should be located
as close as possible to IREF terminal to eliminate the noise
influence.
30
20
10
0
0.1
1
R(IREF) – kΩ
10
Figure 4. Current on Constant Current Output vs External Resistor
100
IOL(C) – mA
90
80
RIREF = 590 Ω
70
RIREF = 670 Ω
60
RIREF = 780 Ω
50
RIREF = 940 Ω
40
RIREF = 1.18 k Ω
30
RIREF = 1.57 k Ω
Ω
RIREF = 2.35 k Ω
20
minimum voltage applied
RIREF = 4.70 k Ω
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VO – Output Voltage –V
NOTE: VCCLOG = VCCANA = PVCC = 5 V, TA = 25°C.
Figure 5. Current on Constant Current Output vs Voltage Applied To Constant Current Output Terminal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
ENABLE
t su (ENABLE–DCLK)
1/f(DCLK)
th(ENABLE–DCLK)
DCLK
ÎÎ
ÎÎ
ÎÎÎÎ
ÎÎ
ÎÎ
t h (DIN–DCLK)
D00_A
DIN7
D70_A
twh (DCLK)
D01_A
D02_A
D0E_A
D0F_A
D00_B
D01_B
D0E_B
D0F_B
D00_C
D01_C
D02_C
D71_A
D72_A
D7E_A
D7F_A
D70_B
D71_B
D7E_B
D7F_B
D70_C
D71_C
D72_C
th (LATCH–DCLK)
t su(LATCH–DCLK)
LATCH
twh (LATCH)
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎÎ
ÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎ
ÎÎ
td (DCLK–DOUT)
DOUT0
D00_A
D01_A
D0E_A
D0F_A
D00_B
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎÎ
ÎÎ
ÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎ
ÎÎ
• DALLAS, TEXAS 75265
ÎÎ
ÎÎ
ÎÎÎÎ
ÎÎ
ÎÎ
DIN0
twl (DCLK)
D70_A
D71_A
D7E_A
D7F_A
D70_B
DOUT7
Figure 6. Timing Diagram (Shift Register for Gray Scale Data)
PRINCIPLES OF OPERATION
POST OFFICE BOX 655303
tsu (DIN–DCLK)
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
18
RSEL
BC_ENA
RSEL
th (RSEL–LATCH )
ENABLE
th (RSEL–DCLK)
tsu (RSEL–DCLK)
DCLK
D00_A
D01_A
D02_A
D03_A
DIN7
D70_A
D71_A
D72_A
D73_A
D04_A
D74_A
D05_A
D06_A
D07_A
D08_A
D09_A
D0A_A
D00_B
D01_B
D75_A
D76_A
D77_A
D78_A
D79_A
D7A_A
D70_B
D71_B
LATCH
BCL_0 # Default Value ”1”
D02_A
D05_A
D06_A
BCL_7 # Default Value ”0”
D72_A
D75_A
D76_A
DOUT0
D7n–2_N
D02_A
D05_A
D06_A
D07_A
D0n–1_N
D0n_N
D00_A
D7n–1_N
D72_A
D75_A
D76_A
D77_A
D7n–1_N
D7n_N
D70_A
# Internal brightness control latch
19
Figure 7. Timing Diagram (Brightness Control Register)
TLC5903
LED DRIVER
DOUT7
D0n–1_N
SLLS383 – DECEMBER 1999
D0n–2_N
ÎÎ ÎÎ
ÎÎ ÎÎ
ÎÎ ÎÎ
• DALLAS, TEXAS 75265
t su (RSEL–LATCH )
PRINCIPLES OF OPERATION
POST OFFICE BOX 655303
DIN0
tsu (LATCH–GSCLK)
BLANK
tsu(BLANK–GSCLK)
t d (BLANK–BOUT)
1/f(GSCLK)
td (BLANK–OUT0)
GSCLK
t wl(GSCLK)
twh(GSCLK)
td (GSCLK–OUT0)
td (GSCLK–OUT0)
WDT
twl (WDT)
twh(WDT)
OUT0
OFF
ON(Note1)
OFF
(Note1)
OFF
(Note1)
td (OUTn+1–OUTn)
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
• DALLAS, TEXAS 75265
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
t wd
OUT15
OFF
DOWN
HI–z
ON(Note1)
OFF
BOUT
td (GSCLK–GSOUT)
GSOUT
NOTE 1: ON or OFF, or ON time is varied depending on the gray scale data and BLANK.
Figure 8. Timing Diagram (Constant Current Output)
(Note1)
OFF
(Note1)
PRINCIPLES OF OPERATION
POST OFFICE BOX 655303
1/f(WDT)
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
20
LATCH
TLC5903
LED DRIVER
SLLS383 – DECEMBER 1999
MECHANICAL DATA
PZP (S-PQFP-G100)
PowerPAD PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
50
76
Thermal Pad
(see Note D)
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
1,05
0,95
0,25
0,15
0,05
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4146929/A 04/99
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The dimensions of the thermal
pad are 2 mm × 2 mm (maximum). The pad is centered on the bottom of the package.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TLC5903PZP
OBSOLETE
HTQFP
PZP
Pins Package Eco Plan (2)
Qty
100
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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