TI OPA688M

SGLS144B − APRIL 2003 − DECEMBER 2006
features
D
D
D
D
D
D
D
High Linearity Near Limiting
Fast Recovery from Overdrive: 2.4 ns
IiMiting Voltage Accuracy: ±15 mV
−3dB Bandwidth (G = +1): 450 MHz
Slew Rate: 1000 V/µs
±5-V and 5-V Supply Operation
Unity Gain Version of the OPA689
applications
D
D
D
D
Fast Limiting ADC Input Buffers
CCD Pixel Clock Stripping
Video Sync Stripping
HF Mixers
D
D
D
D
IF Limiting Amplifiers
AM Signal Generation
Non−Linear Analog Signal Processing
High Speed Comparators
JD PACKAGE
(TOP VIEW)
NC
INVERTING INPUT
NON-INVERTING INPUT
−VCC
1
8
2
7
3
6
4
5
VH
+VCC
OUTPUT
VL
NC - No internal connection
description
The OPA688 is a wideband, unity gain stable voltage-feedback op amp that offers bipolar output voltage limiting.
Two buffered limiting voltages take control of the output when it attempts to drive beyond these limits. This new
output limiting architecture holds the limiter offset error to ±15 mV. The op amp operates linearly to within
30 mV of the output limit voltages.
The combination of narrow nonlinear range and low limiting offset allows the limiting voltages to be set within
100 mV of the desired linear output range. A fast 2.4-ns recovery from limiting ensures that overdrive signals
will be transparent to the signal channel. Implementing the limiting function at the output, as opposed to the
input, gives the specified limiting accuracy for any gain, and allows the OPA688 to be used in all standard op
amp applications.
Non-linear analog signal processing will benefit from the OPA688s sharp transition from linear operation to
output limiting. The quick recovery time supports high-speed applications.
The OPA688M is available in an industry standard pinout CDIP-8 package. For higher gain, or transimpedance
applications requiring output limiting with fast recovery, consider the OPA689M.
ORDERING INFORMATION†
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−55°C to 125°C
CDIP - JD
Tube
OPA688MJD
OPA688MJD
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2006, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SGLS144B − APRIL 2003 − DECEMBER 2006
D E T A IL O F L IM IT E D O U T P U T V O L T A G E
L IM IT E D O U T P U T R E S P O N S E
2 .1 0
V H = − V L = 2 .0 V
G = +2
2 .0
1 .5
VI N
1 .0
VO
0 .5
0
− 0 .5
− 1 .0
2 .0 5
O u t p u t V o lt a g e ( V )
In p u t a n d O u tp u t V o lta g e ( V )
2 .5
2 .0 0
1 .9 5
VO
1 .9 0
1 .8 5
1 .8 0
1 .7 5
− 1 .5
1 .7 0
− 2 .0
1 .6 5
1 .6 0
− 2 .5
T im e ( 5 0 n s / d iv )
T im e ( 2 0 0 n s /d iv )
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6.5 V
Common-mode input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC
Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC
Limiter voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±(VS − 0.7 V)
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
Split-Rail Operation
Operating voltage
Single-Supply Operation
Operating free-air temperature
2
−55
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
NOM
MAX
±5
±6
5
12
125
UNIT
V
°C
SGLS144B − APRIL 2003 − DECEMBER 2006
electrical characteristics, VCC = ±5 V, VICM = 0 V, RL = 500 Ω, limiter pins open (unless otherwise
noted) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC Performance (see Figure 1)
RF = 25 Ω
G = +1,
Small signal bandwidth
VO < 0.2 Vp-p,
VO < 0.2 Vp-p,
G = +2
215
G = −1
215
Gain-bandwidth product (G w 5)
VO < 0.2 Vp-p,
VO < 0.2 Vp-p
Bandwidth for 0.1 dB gain flatness
Gain peaking
Large signal bandwidth
VO = 0.2 V
G = +1, VO < 0.2 Vp-p,
Slew rate
VO = 4 Vp-p,
4 V step,
Rise and fall time
0.2 V step
Settling time to 0.05%
2 V step
Spurious free dynamic range
Differential gain
VO = 2 Vp-p,
RL = 500 Ω,
Differential phase
RL = 500 Ω,
Input noise, voltage noise density
f w 1 MHz
Input noise, current noise density
f w 1 MHz
450
RF = 25 Ω
MHz
250
MHz
30
MHz
11
VH = −VL = 2.5 V
VH = −VL = 2.5 V
dB
145
MHz
1000
V/µs
1.9
ns
8
ns
66
dB
NTSC, PAL
0.02
%
NTSC, PAL
0.01
°
6.3
nV/√Hz
2
pA/√Hz
f = 5 MHz
DC Performance
Open-loop voltage gain (AVOL)
TA = 25°C
TA = Full range
VO = ±0.5 V
46
52
dB
43
Input offset voltage (VIO)
TA = 25°C
TA = Full range
±2
Input bias current (IIB) (See Note 2)
TA = 25°C
TA = Full range
±6
Input offset current (IIO)
TA = 25°C
TA = Full range
±0.3
±8
±11
±12
±20
±2
±4
mV
µA
A
µA
A
Input
Common-mode rejection ratio
(CMRR)
VICM = ±0.5 V,
Input referred
Common-mode input voltage range
(VICR) (See Note 3)
TA = 25°C
TA = Full range
50
TA = 25°C
TA = Full range
±3.2
Input impedance, differential mode
Input impedance, common mode
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
57
dB
47
±3.3
±3.1
V
0.4
1
MΩ
pF
1
1
MΩ
pF
3
SGLS144B − APRIL 2003 − DECEMBER 2006
electrical characteristics, VCC = ±5 V, VICM = 0 V, RL = 500 Ω, limiter pins open (unless otherwise
noted) (see Note 1) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
±4.1
MAX
UNIT
Output
Output voltage range (VOH, VOL)
VH = 4.3 V, VL = −4.3 V,
RL w 500 Ω
TA = 25°C
TA = Full range
±3.9
VH = 4.3 V, VL = −4.3 V,
RL = 20 Ω
TA = 25°C
TA = Full range
90
Current output, sourcing (IOH)
VH = 4.3 V, VL = −4.3 V,
RL = 20 Ω
TA = 25°C
TA = Full range
−70
Current output, sinking (IOL)
Closed-loop output impedance
G = +1, RF = 25 Ω, f < 100 kHz
V
±3.7
105
mA
80
−85
mA
−60
Ω
0.2
Power Supply
Operating voltage (VCC)
Quiescent current (ICC)
Power supply rejection ratio (PSRR)
Input referred,
VS = ±4.5 V to ±5.5 V
TA = 25°C
TA = Full range
14
TA = 25°C
TA = Full range
58
±5
±6
15.8
17
11
20
70
V
mA
dB
55
dB
Output Voltage Limiters (pins 5 and 8)
TA = 25°C
TA = Full range
Default output limited voltage
Limiter pins open
Limiter output offset voltage
(VO − VH) or (VO − VL)
Limiter input bias current magnitude
(See Note 4)
VO = 0 V
±3
TA = Full range
TA = 25°C
35
TA = Full range
31
Limiter input impedance
Limiter feedthrough (See Note 5)
±3.3
f = 5 MHz
±15
±50
54
65
70
−60
dB
400
Op amp bias current shift
(See Note 2)
Limter slew rate (See Note 6)
Limiter step response, recovery time
VI = ±2 V
VI = ±2 V
Linearity guardband (See Note 7)
VO = 2 Vp-p,
Limiter step response, overshoot
NOTES: 1.
2.
3.
4.
5.
6.
7.
4
f = 5 MHz
V
mV
3
VI = ±2 V, VO < 0.02 Vp-p
µA
MΩ
pF
±4.3
Minimum limiter voltage separation
mV
2
1
Maximum limiter voltage
Limiter small signal bandwidth
V
±2.8
µA
450
MHz
100
V/µs
250
mV
2.4
ns
30
mV
All typical limits are at TA = 25°C unless otherwise specified.
Current is considered positive out of node.
CMIR tested as < 3dB degradation from minimum CMRR at specified limits.
IVH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3, Figure 30 and Figure 37.
Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0.
VH slew rate conditions are: VIN = +2 V, G = +2, VL = −2 V, VH = step between 2 V and 0 V. VL slew rate conditions are similar.
Linearity Guardband is defined for an output sinusoid (f = 5 MHz, VO = 0 VDC ±1 VP-P) centered between the limiter levels (VH and
VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 38).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS144B − APRIL 2003 − DECEMBER 2006
electrical characteristics, VCC = 5 V, VICM = 2.5 V, RL = 500 Ω, limiter pins open (unless otherwise
noted) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC Performance (see Figure 2)
RF = 25 Ω
G = +1,
Small signal bandwidth
VO < 0.2 Vp-p,
VO < 0.2 Vp-p,
G = +2
200
G = −1
190
Gain bandwidth product (G w +5)
VO < 0.2 Vp-p,
VO < 0.2 Vp-p
VO < 0.2 Vp-p,
VO < 0.2 Vp-p
G = +1,
Gain peaking
375
MHz
230
RF = 25 Ω
MHz
10
dB
30
MHz
200
MHz
Slew rate
VO < 2 Vp-p
2 V step
820
V/µs
Rise and fall time
0.2 V step
2.3
ns
Settling time to 0.05%
1 V step
Spurious free dynamic range
Input noise, voltage noise density
VO = 2 Vp-p,
f > 1 MHz
Input noise, current noise density
f > 1 MHz
Bandwidth for 0.1 dB gain flatness
Large signal bandwidth
f = 5 MHz
12
ns
64
dB
6.3
nV/√Hz
2
pA/√Hz
DC Performance
Open-loop voltage gain (AVOL)
TA = 25°C
TA = Full range
VO = ±0.4 V
46
52
dB
43
Input offset voltage (VIO)
TA = 25°C
TA = Full range
±2
Input bias current (IIB)
TA = 25°C
TA = Full range
±6
Input offset current (IIO)
TA = 25°C
TA = Full range
±0.3
±8
±11
±12
±20
±2
±4
mV
A
µA
µA
A
Input
Common-mode rejection ratio
(CMRR)
VICM = ±0.5 V,
Input referred
Common-mode input voltage range
(VICR) (See Note 3)
TA = 25°C
TA = Full range
48
55
dB
45
TA = 25°C
VICM
±0.7 V
TA = Full range
VICM
±0.6 V
Input impedance, differential mode
Input impedance, common mode
VICM
±0.8 V
V
0.4
1
MΩ
pF
1
1
MΩ
pF
Output
Output voltage range (VOH, VOL)
VH = VICM + 1.8 V, VL = VICM − 1.8 V,
RL w 500 Ω
TA = 25°C
VICM±
1.4 V
TA = Full range
VICM±
1.3 V
VCC = ±2.5 V,
RL = 20 Ω
TA = 25°C
TA = Full range
60
Current output, sourcing (IOH)
VCC = ±2.5 V,
RL = 20 Ω
TA = 25°C
TA = Full range
−50
Current output, sinking (IOL)
Closed-loop output impedance
G = +1,
RF = 25 Ω,
f < 100 kHz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VICM±
1.6 V
V
70
mA
50
−60
mA
−40
0.2
Ω
5
SGLS144B − APRIL 2003 − DECEMBER 2006
electrical characteristics, VCC = 5 V, VICM = 2.5 V, RL = 500 Ω, limiter pins open (unless otherwise
noted) (see Note 1) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5
12
UNIT
Power Supply
Operating voltage (VCC)
Quiescent current (ICC)
Power supply rejection ratio (PSRR)
Input referred,
VCC = ±2 V to ±3 V
13
V
TA = 25°C
TA = Full range
11
TA = Full range
55
70
dB
TA = 25°C
VICM
±0.6 V
VICM
±0.9 V
V
TA = Full range
VICM
±0.4 V
TA = Full range
TA = 25°C
0
TA = Full range
0
9
15
16.5
mA
Output Voltage Limiters (pins 5 and 8)
Default output limited voltage
Limiter output offset voltage
Limiter input bias current magnitude
(See Note 4)
Limiter pins open
(VO − VH) or (VO − VL)
VO = 2.5 V
Limiter input bias current drift
Limiter input impedance
Limiter feedthrough (See Note 5)
f = 5 MHz
V
±15
±50
35
65
85
nA/°C
2
1
MΩ
pF
Maximum limiter voltage
Limiter small signal bandwidth
400
VI = VICM ± 1.2 V, VO < 0.02 Vp-p
Limiter step response, recovery time
VI = VICM ± 1.2 V
VI = VICM ± 1.2 V
Linearity guardband (See Note 7)
VO = 2 Vp-p,
f = 5 MHz
NOTES: 1.
2.
3.
4.
5.
6.
30
V
mV
5
Limiter slew rate (See Note 6)
Limiter step response, overshoot
dB
VICM±
1.8
Output bias current shift
(See Note 2)
µA
A
30
−60
Minimum limiter voltage separation
mV
µA
300
MHz
20
V/µs
55
mV
15
ns
mV
All typical limits are at TA = 25°C unless otherwise specified.
Current is considered positive out of node.
CMIR tested as < 3dB degradation from minimum CMRR at specified limits.
IVH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3, Figure 31 and Figure 37.
Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0.
VH slew rate conditions are: VIN = VICM + 0.4 V, G = +2, VL = VICM − 1.2 V, VH = stepped between VICM + 1.2 V and VICM. VL slew
rate conditions are similar.
7. Linearity Guardband is defined for an output sinusoid (f = 5 MHz, VO = 0 VDC ±1 VP-P) centered between the limiter levels (VH and
VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 38).
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS144B − APRIL 2003 − DECEMBER 2006
TYPICAL CHARACTERISTICS
FREQUENCY RESPONSE
FREQUENCY RESPONSE
6
12
3
G = +2, R C = ∞
3
0
RS
150 Ω
− 3
− 6
V
IN
V
− 9
R
O
C
R
F
− 18
1M
R
− 3
− 6
− 9
G = −2
− 12
− 15
G= − 5
− 18
− 12
− 15
V O = 0.2Vp−p
0
Ω , R F = 25 Ω
G = +1, R C = 175
Normalized Gain (dB)
Normalized Gain (dB)
6
G= − 1
G = +1, R C = ∞ , R F = 25 Ω
V O = 0.2Vp−p
9
G = +5, R C = ∞
G
10M
100M
− 21
− 24
1M
1G
Figure 1
2.5
2.0
0.20
V O = 0.2Vp−p
0.15
1.5
0.10
1.0
Output Voltage (V)
Output Voltage (V)
1G
LARGE−SIGNAL PULSE RESPONSE
SMALL−SIGNAL PULSE RESPONSE
0.05
0
− 0.05
− 0.10
V O = 4Vp−p
V H = − V L = 2.5V
0.5
0
− 0.5
− 1.0
− 0.15
− 1.5
− 0.20
− 2.0
− 2.5
− 0.25
Time (5ns/div)
Time (5ns/div)
Figure 3
Figure 4
V L Ñ LIMITED PULSE RESPONSE
V H − LIMITED PULSE RESPONSE
2.5
2.5
2.0
2.0
1.5
1.5
1.0
VIN
0.5
VO
0
− 0.5
− 1.0
G = +2
V H = +2V
Input and Output Voltages (V)
Input and Output Voltages (V)
100M
Figure 2
0.25
− 1.5
10M
Frequency (Hz)
Frequency (Hz)
G = +2
V L = −2 V
1.0
0.5
0
− 0.5
− 1.0
V IN
− 1.5
V O
− 2.0
− 2.0
− 2.5
− 2.5
Time (20ns/div)
Time (20ns/div)
Figure 5
Figure 6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SGLS144B − APRIL 2003 − DECEMBER 2006
TYPICAL CHARACTERISTICS
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
HARMONIC DISTORTION vs FREQUENCY
− 40
− 40
V O = 2 Vp-p
R L = 500 Ω
V O = 0V DC ± 1 Vp
− 45
2nd and 3rd Harmonic Distortion (dBc)
2nd and 3rd Harmonic Distortion (dBc)
− 45
− 50
− 55
HD2
− 60
− 65
− 70
HD3
− 75
− 80
− 85
− 90
1M
10M
f 1 = 5 MHz
R L = 500 Ω
− 50
− 55
− 60
HD2
− 65
− 70
− 75
HD3
− 80
− 85
− 90
0.9
20M
1.0
1.1
1.2
1.3
R L = 500 Ω
− 55
− 60
− 65
− 70
f 1 = 5MHz
− 75
f 1 = 2MHz
− 80
f 1 = 1MHz
1.0
f 1 = 2MHz
f 1 = 5MHz
− 65
f 1 = 1MHz
f 1 = 10MHz
− 70
f 1 = 20MHz
− 75
− 80
− 90
0.1
5.0
1.0
5.0
Output Swing (Vp−p)
Figure 10
LARGE−SIGNAL FREQUENCY RESPONSE
HARMONIC DISTORTION vs LOAD RESISTANCE
− 40
12
− 50
≤ 0.2Vp−p
G = +2
V O = 2 Vp-p
f 1 = 5MHz
− 45
9
6
HD2
3
2Vp−p
− 60
Gain (dB)
2nd and 3rd Harmonic Distortion (dBc)
Ω
− 60
Figure 9
− 65
HD3
− 70
0
− 3
− 6
− 75
− 9
− 80
− 12
− 85
− 15
− 90
− 18
50
100
1000
1M
Load Resistance ( Ω )
10M
100M
Frequency (Hz)
Figure 11
8
2.0
− 55
Output Swing (Vp−p)
− 55
1.9
− 85
− 90
0.1
1.8
− 50
f 1 = 10MHz
3rd Harmonic Distortion (dBc)
2nd Harmonic Distortion (dBc)
R L = 500
− 45
f 1 = 20MHz
− 85
1.7
3RD HARMONIC DISTORTION vs OUTPUT SWING
− 40
− 50
1.6
Figure 8
2ND HARMONIC DISTORTION vs OUTPUT SWING
− 45
1.5
± Limit Voltage (V)
Frequency (Hz)
Figure 7
− 40
1.4
Figure 12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1G
SGLS144B − APRIL 2003 − DECEMBER 2006
TYPICAL CHARACTERISTICS
FREQUENCY RESPONSE vs CAPACITIVE LOAD
R S vs CAPACITIVE LOAD
12
80
C L =0
9
70
V O = 0.2Vp−p
6
Gain to Capacitive Load (dB)
R S (Ω )
60
50
40
30
20
C L = 10pF
3
C L = 100pF
0
− 3
− 6
402 Ω
− 18
1k Ω
C
O
L
1k Ω is optional
1M
300
10M
100M
1G
Frequency (Hz)
Capacitive Load (pF)
Figure 13
Figure 14
OPEN−LOOP FREQUENCY RESPONSE
100
50
−30
40
−60
30
−90
20
−120
V O = 0.2Vp−p
10
−150
0
−180
−10
−210
−20
Open−Loop Phase (deg)
Gain
Phase
Input Current Noise Density (pA/Hz)
0
Input Voltage Noise Density (nV/Hz)
60
100k
1M
10M
100M
Voltage Noise
10
√ Hz
6.3nV/
Current Noise
√ Hz
2.0pA/
1
−240
10k
100
1G
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 15
Figure 16
LIMITER FEEDTHROUGH
LIMITER SMALL−SIGNAL FREQUENCY RESPONSE
−30
6
−35
3
V O = 0.02Vp−p
0
−40
−45
− 6
− 9
V
H
= 0.02Vp−p + 2.0V
DC
200 Ω
2V
8
DC
V
− 12
− 15
Feedthrough (dB)
− 3
Limiter Gain (dB)
Open−Loop Gain (dB)
V
402 Ω
0
100
S
OPA688
− 12
− 15
10
R
IN
− 9
10
1
200 Ω
V
O
402 Ω
402 Ω
H
= 0.02Vp−p + 2V
DC
8
−60
V
−65
O
402 Ω
402 Ω
−75
−80
− 24
1M
V
200 Ω
−55
−70
− 18
− 21
−50
10M
100M
1G
1M
10M
50M
Frequency (Hz)
Frequency (Hz)
Figure 17
Figure 18
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9
SGLS144B − APRIL 2003 − DECEMBER 2006
TYPICAL CHARACTERISTICS
L IM IT E R IN P U T B IA S C U R R E N T v s B IA S V O L T A GE
CLOSED−LOOP OUTPUT IMPEDANCE
100
100
M a x im u m O v e r T e mp e ra tu re
G = +1
Ω )
Output Impedance (
75
R F = 25 Ω
V O = 0.2Vp−p
50
10
25
M in im u m O v e r T e m p e ra tu re
0
− 25
1
L im it er H e a d ro o m = + V S − V H
= V L − (− V S )
− 50
C u r re n t = I VH o r − I VL
− 75
0.1
1M
10M
100M
− 100
0 .0
1G
0 .5
1 .0
1 .5
2 .0
2 .5
3 .0
3 .5
4 .0
4 .5
5 .0
L im ite r H e a d r o o m (V )
Frequency (Hz)
Figure 19
Figure 20
PSR AND CMR vs TEMPERATURE
SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE
100
20
Output Current, Sourcing
Output Current (mA)
Supply Current (mA)
18
PSR and CMR, Input Referred (dB)
95
16
Supply Current
14
| Output Current, Sinking
|
12
10
− 25
0
25
50
Ambient Temperature (
Figure 21
75
85
80
PSRR
75
PSR+
70
65
CMRR
60
55
50
70
− 50
PSR−
90
− 50
100
− 25
° C)
0
Figure 22
VOLTAGE RANGES vs TEMPERATURE
5.0
V H = − V L = 4.3V
Voltage Range (V)
4.5
Output Voltage Range
4.0
3.5
Common−Mode Input Range
3.0
−50
−25
0
25
50
75
Ambient Temperature ( °C)
Figure 23
10
25
Ambient Temperature (
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100
50
°C)
75
100
SGLS144B − APRIL 2003 − DECEMBER 2006
TYPICAL CHARACTERISTICS
FREQUENCY RESPONSE
FREQUENCY RESPONSE
12
V O = 0.2Vp−p
G = +1, R
G = +1, R
= 175
G = +2, R
C
6
Normalized Gain (dB)
C
C
3
Ω ,R
F
F
6
Ω
= 25
0
= ∞
R
150 Ω
−6
V
IN
V
R
−9
O
C
R
F
−12
R
−15
G = +5, R
C
G
10M
G
G ==
G=
− 5
− 6
− 9
− 12
− 15
− 21
100M
− 24
1M
1G
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 25
LARGE−SIGNAL FREQUENCY RESPONSE
12
G = +2
9
6
≤ 0.2Vp−p
3
0
−3
2.0Vp−p
−6
−9
−12
−15
In p u t a n d O u tp u t V o lta g e s (V )
Figure 24
Gain (dB)
− 2
− 3
− 18
= ∞
−18
1M
− 1
V O = 0.2Vp−p
Ω
0
−3
G=
3
= 25
Normalized Gain (dB)
9
= ∞ ,R
V H A N D V L − L IM IT E D P U L S E R E S P O N S E
5 .0
V H = V CM + 1 .2 V
4 .5
V L = V CM − 1 .2 V
4 .0
3 .5
V IN
3 .0
V
2 .5
CM
V O
= 2 .5 V
2 .0
V IN
1 .5
VO
1 .0
0 .5
−18
1M
10M
100M
0
1G
T im e ( 2 0 n s /d iv )
Frequency (Hz)
Figure 26
Figure 27
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
HARMONIC DISTORTION vs FREQUENCY
−40
−40
V O = 2 Vp-p
R L = 500 Ω
V O = 2.5V ± 1Vp
f 1 = 5 MHz
R L = 500 Ω
−45
2nd and 3rd Harmonic Distortion (dBc)
2nd and 3rd Harmonic Distortion (dBc)
−45
−50
−55
HD2
−60
−65
HD3
−70
−75
−80
−85
−50
−55
−60
HD2
−65
−70
HD3
−75
−80
−85
−90
−90
1M
10M
20M
0.9
1.0
1.1
1.2
1.3
| Limit Voltages
Frequency (Hz)
Figure 28
1.4
1.5
1.6
1.7
1.8
− 2.5V DC |
Figure 29
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11
SGLS144B − APRIL 2003 − DECEMBER 2006
APPLICATION INFORMATION
dual-supply, non-inverting amplifier
Figure 30 shows a non-inverting gain amplifier for dual-supply operation. This circuit was used for AC
characterization of the OPA688, with a 50-Ω source, which it matches, and a 500-Ω load. The power-supply
bypass capacitors are shown explicitly in Figures 30 and 31, but will be assumed in the other figures. The limiter
voltages (VH and VL) and their bias currents (IVH and IVL) have the polarities shown.
single-supply, non-inverting amplifier
Figure 31 shows an AC-coupled, non-inverting gain amplifier for single +5V supply operation. This circuit was
used for AC characterization of the OPA688, with a 50W source, which it matches, and a 500-Ω load. The
power-supply bypass capacitors are shown explicitly in Figures 30 and 31, but will be assumed in the other
figures. The limiter voltages (VH and VL) and their bias currents (IVH and IVL) have the polarities shown. Notice
that the single-supply circuit can use three resistors to set VH and VL, where the dual-supply circuit usually uses
four to reference the limit voltages to ground.
limited output, ADC input driver
Figure 32 shows a simple ADC (Analog-to-Digital Converter) driver that operates on a single supply, and gives
excellent distortion performance. The limit voltages track the input range of the converter, completely protecting
against input overdrive.
3.01k Ω
1.91k Ω
+V S = +5V
∝F
2.2 ∝ F 0.1
0.1 ∝ F
+
V H = +2V
Ω
174
7
3
V IN
8
Ω
49.9
R G
402 Ω
6
OPA688
2
I VH
5
I VL
V O
500
Ω
4
R F
402 Ω
0.1 ∝ F
0.1 ∝ F
V L = − 2V
2.2 ∝ F
3.01k Ω
1.91k Ω
+
− V S = − 5V
Figure 30. DC-Coupled, Dual Supply Amplifier
12
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SGLS144B − APRIL 2003 − DECEMBER 2006
V S = +5V
0.1 ∝ F
+
2.2 ∝ F
523
Ω
0.1 ∝ F
V H = 3.7V
806 Ω
0.1 ∝ F
3
I VH
7
V IN
976
8
Ω
57.6
806 Ω
6
OPA688
2
5
R F
V O
500
I VL
4
402
Ω
0.1 ∝ F
Ω
Ω
0.1 ∝ F
V L = 1.3V
R G
402 Ω
523
0.1 ∝ F
Ω
Figure 31. AC-Coupled, Single Supply Amplifier
VS = +5V
562Ω
V H = + 3 .6 V
0 .1 ∝ F
715Ω
+ 3 .5 V
VS = +5V
R E FT
0 .1 ∝ F
3
V IN
V S = +5V
102Ω
R S EL
+V S
7
8
O P A 688
2 4 .9 Ω
5
2
A D S 822
6
1 0 −B i t
IN
40M S PS
100pF
1 0 −B i t
D a ta
4
715Ω
R E FB
402Ω
I N T / E X TG N D
+ 1 .5 V
102Ω
402Ω
0 .1 ∝ F
V L = + 1 .4 V
0 .1 ∝ F
562Ω
Figure 32. Single Supply, Limiting ADC Input Driver
precision half wave rectifier
Figure 33 shows a half wave rectifier with outstanding precision and speed. VH (pin 8) will default to a voltage
between 3.1 and 3.8 V if left open, while the negative limit is set to ground.
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13
SGLS144B − APRIL 2003 − DECEMBER 2006
+V S = +5V
200 Ω
7
2
NC
V IN
8
OPA688
6
V O
5
3
4
402
Ω
402
Ω
− V S = − 5V
Figure 33. Precision Half Wave Rectifier
very high speed Schmitt trigger
Figure 34 shows a very high-speed Schmitt trigger. The output levels are precisely defined, and the switching
time is exceptional. The output voltage swings between ±2V.
unity-gain buffer
Figure 35 shows a unity-gain voltage buffer using the OPA688. The feedback resistor (RF) isolates the output
from any board inductance between pins 2 and 6. We recommend that
RF × 24.9W for unity-gain buffer applications. RC is an optional compensation resistor that reduces the peaking
typically seen at G = +1. Choosing RC = RS + RF gives a unity gain buffer with approximately the G = +2
frequency response.
DC restorer
Figure 36 shows a DC restorer using the OPA688 and OPA660. The OPA660’s OTA amplifier is used as a
Current Conveyor (CCII) in this circuit, with a current gain of 1.0.
When VO tries to go below ground, CCII charges C1 through D1, which restores the output back to ground. D1
adds a propagation delay to the restoration process, which then has an exponential decay with time constant
R1C1/G (G = +2 = the OPA688 gain). When the signal is above ground, it decays to ground with a time constant
of R2C1. The OPA688 output recovers very quickly from overdrive.
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• DALLAS, TEXAS 75265
SGLS144B − APRIL 2003 − DECEMBER 2006
3.01k Ω
1.91k Ω
+V S = +5V
0.1 ∝ F
200 Ω
402
Ω
VO
V IN
3
7
8
6
OPA688
133 Ω
2
5
4
0.1 ∝ F
3.01k Ω
1.91k Ω
− V S = − 5V
Figure 34. Very High Speed Schmitt Trigger
R S
V O
OPA688
V S
R C
R F
24.9
Ω
Figure 35. Unity-Gain Buffer
C
100pF
U1
200
Ω
5
V IN
V H = +3V
20 Ω
6
+1
8
D 1
1
R Q
1k Ω
R
100k
OPA688
Ω
D 2
R Q = 1k Ω (sets U1 ’s I Q)
D 1 , D 2 = 1N4148
V O
5
V L = − 1V
402
Ω
U1
C
20 Ω
402 Ω
3
B
R
40.2
CCII
Ω
2
E
Figure 36. DC Restorer
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15
SGLS144B − APRIL 2003 − DECEMBER 2006
design-in tools
applications support
The Texas Instrments web site (http://www.ti.com) has the latest data sheets and other design aids.
theory of operation
The OPA688 is a voltage-feedback op amp that is unity-gain stable. The output voltage is limited to a range set
by the voltage on the limiter pins (5 and 8). When the input tries to overdrive the output, the limiters take control
of the output buffer. This avoids saturating any part of the signal path, giving quick overdrive recovery and
excellent limiter accuracy at any signal gain.
The limiters have a very sharp transition from the linear region of operation to output limiting. This allows the
limiter voltages to be set very near (< 100mV) the desired signal range. The distortion performance is also very
good near the limiter voltages.
circuit layout
Achieving optimum performance with the high-frequency OPA688 requires careful attention to layout design
and component selection. Recommended PCB layout techniques and component selection criteria are:
a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Open a window in the ground
and power planes around the signal I/O pins, and leave the ground and power planes unbroken elsewhere.
b) Provide a high quality power supply. Use linear regulators, ground plane and power planes to provide
power. Place high-frequency 0.1 µF decoupling capacitors < 0.2” away from each power-supply pin. Use wide,
short traces to connect to these capacitors to the ground and power planes. Also use larger (2.2 µF to 6.8 µF)
high-frequency decoupling capacitors to bypass lower frequencies. They may be somewhat further from the
device, and be shared among several adjacent devices.
c) Place external components close to the OPA688. This minimizes inductance, ground loops, transmission
line effects and propagation delay problems. Be extra careful with the feedback (RF), input and output resistors.
d) Use high-frequency components to minimize parasitic elements. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter layout. Metal film or carbon composition
axially-leaded resistors can also provide good performance when their leads are as short as possible. Never
use wirewound resistors for high-frequency applications. Remember that most potentiometers have large
parasitic capacitances and inductances.
Multilayer ceramic chip capacitors work best and take up little space. Monolithic ceramic capacitors also work
very well. Use RF type capacitors with low ESR and ESL. The large power pin bypass capacitors (2.2 µF to
6.8 µF) should be tantalum for better high-frequency and pulse performance.
e) Choose low resistor values to minimize the time constant set by the resistor and its parasitic parallel
capacitance. Good metal film or surface mount resistors have approximately 0.2 pF parasitic parallel
capacitance. For resistors > 1.5 kΩ, this adds a pole and/or zero below 500 MHz.
Make sure that the output loading is not too heavy. The recommended 402-Ω feedback resistor is a good starting
point in your design.
f) Use short direct traces to other wideband devices on the board. Short traces act as a lumped capacitive
load. Wide traces (50 to 100 mils) should be used. Estimate the total capacitive load at the output, and use the
series isolation resistor recommended in the typical performance curve ”RS vs Capacitive Load”. Parasitic loads
< 2 pF may not need the isolation resistor.
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SGLS144B − APRIL 2003 − DECEMBER 2006
g) When long traces are necessary, use transmission line design techniques (consult an ECL design
handbook for microstrip and stripline layout techniques). A 50-Ω transmission line is not required on board—a
higher characteristic impedance will help reduce output loading. Use a matching series resistor at the output
of the op amp to drive a transmission line, and a matched load resistor at the other end to make the line appear
as a resistor. If the 6 dB of attenuation that the matched load produces is not acceptable, and the line is not too
long, use the series resistor at the source only. This will isolate the source from the reactive load presented by
the line, but the frequency response will be degraded.
Multiple destination devices are best handled as separate transmission lines, each with its own series source
and shunt load terminations. Any parasitic impedances acting on the terminating resistors will alter the
transmission line match, and can cause unwanted signal reflections and reactive loading.
h) Do not use sockets for high-speed parts like the OPA688. The additional lead length and pin-to-pin
capacitance introduced by the socket creates an extremely troublesome parasitic network. Best results are
obtained by soldering the part onto the board.
power supplies
The OPA688 is nominally specified for operation using either ±5-V supplies or a single +5-V supply. The
maximum specified total supply voltage of 12 V allows reasonable tolerances on the supplies. Higher supply
voltages can break down internal junctions, possibly leading to catastrophic failure. Single-supply operation is
possible as long as common mode voltage constraints are observed. The common mode input and output
voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input
and output headroom requirement will allow design of non-standard or single-supply operation circuits.
Figure 31 shows one approach to single-supply operation.
ESD protection
ESD damage has been known to damage MOSFET devices, but any semiconductor device is vulnerable to
ESD damage. This is particularly true for very high-speed, fine geometry processes.
ESD damage can cause subtle changes in amplifier input characteristics without necessarily destroying the
device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift.
Therefore, ESD handling precautions are required when handling the OPA688.
output limiters
The output voltage is linearly dependent on the input(s) when it is between the limiter voltages VH (pin 8) and
VL (pin 5). When the output tries to exceed VH or VL, the corresponding limiter buffer takes control of the output
voltage and holds it at VH or VL.
Because the limiters act on the output, their accuracy does not change with gain. The transition from the linear
region of operation to output limiting is very sharp—the desired output signal can safely come to within 30 mV
of VH or VL with no onset of non-linearity.
The limiter voltages can be set to within 0.7 V of the supplies (VL ≥ −VS + 0.7 V, VH ≤ +VS − 0.7 V). They must
also be at least 400 mV apart (VH − VL ≥ 0.4V).
POST OFFICE BOX 655303
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17
L im te r In p u t B ia s C u r r e n t ( ∝ A
SGLS144B − APRIL 2003 − DECEMBER 2006
L IM IT E R IN P U T B IA S C U R R E N T vs B IA S V O L T A G E
100
M a x im u m O v e r T e m p e ra tu re
75
50
25
M in im u m O v e r T e m p e ra tu re
0
− 25
L im ite r H e a d r o o m = + V S − V H
= V L − ( − V S)
− 50
C u r re n t = I VH o r − I VL
− 75
− 100
0 .0
0 .5
1 .0
1 .5
2 .0
2 .5
3 .0
3 .5
4 .0
4 .5
5 .0
L im ite r H e a d r o o m (V )
Figure 37. Limiter Bias Current vs Bias Voltage
When pins 5 and 8 are left open, VH and VL go to the Default Voltage Limit; the minimum values are in the
Specifications. Looking at Figure 37 for the zero bias current case will show the expected range of (Vs _ default
limit voltages) = headroom.
When the limiter voltages are more than 2.1V from the supplies (VL > −VS + 2.1 V or VH < +VS − 2.1 V), you
can use simple resistor dividers to set VH and VL (see Figure 30). Make sure you include the Limiter Input Bias
Currents (Figure 37) in the calculations (i.e., IVL ≥ −50 µA out of pin 5, and IVH ≤ +50 µA out of pin 8). For good
limiter voltage accuracy, run at least 1-mA quiescent bias current through these resistors.
When the limiter voltages need to be within 2.1V of the supplies (VL ≤ −VS + 2.1 V or VH ≥ +VS − 2.1 V), consider
using low impedance buffers to set VH and VL to minimize errors due to bias current uncertainty. This will typically
be the case for single supply operation (VS = +5V). Figure 31 runs 2.5 mA through the resistive divider that sets
VH and VL. This keeps errors due to IVH and IVL < ±1% of the target limit voltages.
The limiters’ DC accuracy depends on attention to detail. The two dominant error sources can be improved as
follows:
• Power supplies, when used to drive resistive dividers that set VH and VL, can contribute large errors (e.g.,
"5%). Using a more accurate source, and bypassing pins 5 and 8 with good capacitors, will improve limiter
PSRR.
• The resistor tolerances in the resistive divider can also dominate. Use 1% resistors.
Other error sources also contribute, but should have little impact on the limiters’ DC accuracy:
• Reduce offsets caused by the Limiter Input Bias Currents. Select the resistors in the resistive divider(s) as
described above.
• Consider the signal path DC errors as contributing to uncertainty in the useable output swing.
• The Limiter Offset Voltage only slightly degrades limiter accuracy.
Figure 38 shows how the limiters affect distortion performance. Virtually no degradation in linearity is observed
for output voltage swinging right up to the limiter voltages.
18
POST OFFICE BOX 655303
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SGLS144B − APRIL 2003 − DECEMBER 2006
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
−40
V O = 0V DC " 1 Vp
f 1 = 5 MHz
R L = 500 Ω
2nd and 3rd Harmonic Distortion (dBc)
−45
−50
−55
−60
HD2
−65
−70
−75
HD3
−80
−85
−90
0.9
1.0
1.1
1.2
"
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
Limit Voltage (V)
Figure 38. Harmonic Distortion Near Limit Voltages
offset voltage adjustment
The circuit in Figure 39 allows offset adjustment without degrading offset drift with temperature. Use this circuit
with caution since power supply noise can inadvertently couple into the op amp.
+V
R 2
S
R
T R IM
47kΩ
V
O PA688
− V
S
0 .1 ∝ F
R 1
R 3 (2 ) = R
V
IN
O
(1 )
1
|| R
2
o r G ro u n d
N O T E S : (1 ) S e t R 1 < < R TRIM . (2 ) R 3 is o p tio n a l a n d
m in im ize s ou t u t p
offset d ue to in u t bia s cu
p rre nts.
Figure 39. Offset Voltage Trim
Remember that additional offset errors can be created by the amplifier’s input bias currents. Whenever possible,
match the impedance seen by both DC input bias currents using R3. This minimizes the output offset voltage
caused by the input bias currents.
output drive
The OPA688 has been optimized to drive 500-Ω loads, such as ADCs. It still performs very well driving 100-Ω
loads; the specifications are shown for the 500-Ω load. This makes the OPA688 an ideal choice for a wide range
of high-frequency applications.
Many high-speed applications, such as driving ADCs, require op amps with low output impedance. As shown
in the typical performance curve ”Output Impedance vs Frequency”, the OPA688 maintains very low closed-loop
output impedance over frequency. Closed-loop output impedance increases with frequency, since loop gain
decreases with frequency.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SGLS144B − APRIL 2003 − DECEMBER 2006
thermal considerations
The OPA688 will not require heat-sinking under most operating conditions. Maximum desired junction
temperature will set a maximum allowed internal power dissipation as described below. In no case should the
maximum junction temperature be allowed to exceed 150°C.
The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and the additional power
dissipated in the output stage (PDL) while delivering load power. PDQ is simply the specified no-load supply
current times the total supply voltage across the part. PDL depends on the required output signals and loads.
For a grounded resistive load, and equal bipolar supplies, it is at a maximum when the output is at 1/2 either
supply voltage. In this condition, PDL = VS2/(4RL) where RL includes the feedback network loading. Note that
it is the power in the output stage, and not in the load, that comprises PDL.
The operating junction temperature is: TJ = TA + PD ΘJA, where TA is the ambient temperature.
For example, the maximum TJ for a OPA688M with G = +2, RFB = 402 Ω, RL = 100 Ω, and ±VS = ±5 V at the
maximum TA = + 85°C is calculated as:
P DQ + (10 V
P DL +
20 mA) + 200 mW
(5 V)
4
2
ǒ100 W ø 804 WǓ
+ 70 mW
P D + 200 mW ) 70 mW + 270 mW
TJ = 85°C + 270 mW × (119°C/W) = 117°C
capacitive loads
Capacitive loads, such as the input to ADCs, will decrease the amplifier’s phase margin, which may cause
high-frequency peaking or oscillations. Capacitive loads × 2 pF should be isolated by connecting a small resistor
in series with the output as shown in Figure 40. Increasing the gain from +2 will improve the capacitive drive
capabilities due to increased phase margin.
R
S
V
OPA688
R
L
C
O
L
R L is optional
Figure 40. Driving Capacitive Loads
In general, capacitive loads should be minimized for optimum high-frequency performance. The capacitance
of coax cable (29 pF/foot for RG-58) will not load the amplifier when the coaxial cable, or transmission line, is
terminated in its characteristic impedance.
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SGLS144B − APRIL 2003 − DECEMBER 2006
frequency response compensation
The OPA688 is internally compensated to be unity-gain stable, and has a nominal phase margin of 60° at a gain
of +2. Phase margin and peaking improve at higher gains. Recall that an inverting gain of −1 is equivalent to
a gain of +2 for bandwidth purposes (i.e., noise gain = 2).
Standard external compensation techniques work with this device. For example, in the inverting configuration,
the bandwidth may be limited without modifying the inverting gain by placing a series RC network to ground on
the inverting node. This has the effect of increasing the noise gain at high frequencies, which limits the
bandwidth.
To maintain a wide bandwidth at high gains, cascade several op amps, or use the high gain optimized OPA689.
In applications where a large feedback resistor is required, such as photodiode transimpedance amplifier, the
parasitic capacitance from the inverting input to ground causes peaking or oscillations. To compensate for this
effect, connect a small capacitor in parallel with the feedback resistor. The bandwidth will be limited by the pole
that the feedback resistor and this capacitor create. In other high gain applications, use a three resistor ”Tee”
network to reduce the RC time constants set by the parasitic capacitances. Be careful to not increase the noise
generated by this feedback network too much.
pulse settling time
The OPA688 is capable of an extremely fast settling time in response to a pulse input. Frequency response
flatness and phase linearity are needed to obtain the best settling times. For capacitive loads, such as an ADC,
use the recommended RS in the typical performance curve ”RS vs Capacitive Load”. Extremely fine-scale
settling (0.01%) requires close attention to ground return current in the supply decoupling capacitors.
The pulse settling characteristics when recovering from overdrive are very good.
distortion
The OPA688’s distortion performance is specified for a 500-Ω load, such as an ADC. Driving loads with smaller
resistance will increase the distortion as illustrated in Figure 41. Remember to include the feedback network
in the load resistance calculations.
HARMONIC DISTORTION vs LOAD RESISTANCE
−40
V O = 2 Vp-p
f 1 = 5MHz
2nd and 3rd Harmonic Distortion (dBc)
−45
−50
HD2
−55
−60
−65
HD3
−70
−75
−80
−85
−90
50
100
1000
Load Resistance ( Ω )
Figure 41. 5 MHz Harmonic Distortion vs Load Resistance
POST OFFICE BOX 655303
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21
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
OPA688MJD
NRND
CDIP SB
JD
Pins Package Eco Plan (2)
Qty
8
1
TBD
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA688M :
• Catalog: OPA688
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
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