HOLTEK HT1620_09

HT1620
RAM Mapping 32´4 LCD Controller for I/O MCU
PATENTED
PAT No. : 099352
Technical Document
· FAQs
· Application Note
Features
· Logic operating voltage: 2.4V~3.3V
· 8 kinds of time base/WDT clock source
· LCD voltage: 3.6V~4.9V
· 32´4 LCD driver
· Low operating current <3mA at 3V
· Built-in 32´4-bit display RAM
· External 32.768kHz crystal oscillator
· 3-wire serial interface
· Selection of 1/2 or 1/3 bias, and selection of
· Internal LCD driving frequency source
1/2 or 1/3 or 1/4 duty LCD applications
· Software configuration feature
· Internal time base frequency sources
· R/Wy address auto increment
· Two selectable buzzer frequencies
· Data mode and command mode instructions
(2kHz/4kHz)
· Three data accessing modes
· Built-in capacitor type bias charge pump
· HT1620: 64pin LQFP package
· Time base or WDT overflow output
HT1620G: Gold bumped chip
General Description
terface between the host controller and the HT1620.
The HT1620 consumes low operating current owing to
adopting capacitor type bias charge pump. The HT162X
series have many kinds of products that match various
applications.
The HT1620 is a 128 pattern (32´4), memory mapping,
and multi-function LCD driver. The S/W configuration
feature of the HT1620 makes it suitable for multiple LCD
applications including LCD modules and display subsystems. Only three or four lines are required for the in-
Selection Table
HT162X
HT1620
HT1621
HT1622
HT16220
HT1623
HT1625
HT1626
COM
4
4
8
8
8
8
16
SEG
32
32
32
32
48
64
48
Built-in Osc.
¾
Ö
Ö
¾
Ö
Ö
Ö
Crystal Osc.
Ö
Ö
¾
Ö
Ö
Ö
Ö
Rev. 1.80
1
July 27, 2009
PATENTED
HT1620
Block Diagram
D is p la y R A M
O S C O
O S C I
C o n tro l
a n d
T im in g
C ir c u it
C S
R D
W R
C O M 0
C O M 3
L C D D r iv e r /
B ia s C ir c u it
S E G 0
D A T A
S E G 3 1
C C 1
V D D
C C 2
V S S
V O 1 5 N
V E E
B Z
T o n e F re q u e n c y
G e n e ra to r
B Z
Note:
W a tc h d o g T im e r &
T im e B a s e G e n e r a to r
IR Q
CS: Chip selection
BZ, BZ: Tone outputs
WR, RD, DATA: Serial interface
COM0~COM3, SEG0~SEG31: LCD outputs
IRQ: Time base or WDT overflow output
VO15N: Half voltage circuit output pin
VEE: Double voltage circuit output pin
CC1/CC2: External capacitor pin, for double voltage and half voltage circuit use
Pin Assignment
N C
N C
N C
C S
R D
W R
D A T A
V S S
O S C O
O S C I
V D D
IR Q
B Z
B Z
C C 1
N C
6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9
4 8
N C
3
4 6
5
4 4
N C
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
N C
C
V O 1
V
C O
C O
C O
C O
S E
S E
S E
S E
S E
S E
S E
N C
C 2
5 N
E E
M 0
M 1
M 2
M 3
G 0
G 1
G 2
G 3
G 4
G 5
G 6
1
4 7
2
4 5
4
6
7
8
H T 1 6 2 0
6 4 L Q F P -A
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
N C
N C
G 3 1
G 3 0
G 2 9
G 2 8
G 2 7
G 2 6
G 2 5
G 2 4
G 2 3
G 2 2
G 2 1
G 2 0
N C
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
N C
N C
S E G
S E G
1 9
1 8
1 7
1 6
2
1 5
1 4
1 3
1 2
1 1
1 0
9
8
7
Rev. 1.80
July 27, 2009
PATENTED
HT1620
Pad Assignment
4 5
4 4
4 3
4 2
C S
4 6
R D
4 7
W R
O S C I
4 8
D A T A
V D D
4 9
V S S
IR Q
5 0
O S C O
B Z
5 1
4 1 4 0
2
3
C O M 0
C O M 1
C O M 2
C O
S E
S E
S E
B Z
V O 1 5 N
V E E
1
C C 1
C C 2
4
5
6
M 3
G 0
G 1
G 2
1 0
S E G 3
S E G 4
S E G 5
1 1
1 2
1 3
7
8
(0 ,0 )
9
S E G 7
S E G 8
S E G 9
S E G 1 0
S E G 1 2
2 3 2 4
2 5 2 6
2 7
S E G 1 9
S E G 6
2 1 2 2
S E G 1 8
2 0
S E G 1 7
1 8 1 9
S E G 1 6
1 7
S E G 1 5
1 6
S E G 1 4
S E G 1 3
1 5
S E G 1 1
1 4
3 9
S E G 3 1
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
S E G 3 0
S E G 2 9
S E G 2 8
S E G 2 7
S E G
S E G
S E G
S E G
S E G
S E G
2 6
2 5
2 4
2 3
2 2
2 1
S E G 2 0
Chip size: 92 ´ 89 (mil)2
Bump height: 18mm ± 3mm
Min. Bump spacing: 23.102mm
Bump size: 76 ´ 76mm2
* The IC substrate should be connected to VDD in the PCB layout artwork.
Rev. 1.80
3
July 27, 2009
PATENTED
HT1620
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
1
-1047.550
1003.190
2
-1047.675
751.820
27
288.954
-1017.875
28
1066.345
3
-1047.589
-956.690
653.370
29
1066.345
4
-857.591
-1047.675
546.716
30
1066.345
-758.569
5
-1047.675
447.615
31
1066.345
-659.470
6
-1047.675
348.594
32
1066.345
-560.449
7
-1047.675
249.495
33
1066.345
-461.351
8
-1047.675
150.475
34
1066.345
-362.330
9
-1047.675
51.375
35
1066.345
-263.230
10
-1047.675
-47.646
36
1066.345
-164.210
11
-1047.675
-146.745
37
1066.345
12
-1047.675
-245.766
38
1066.345
-65.110
33.910
13
-1047.675
-344.865
39
1066.345
133.010
14
-998.865
-1017.875
40
1061.255
1003.190
15
-899.766
-1017.875
41
962.234
1003.190
16
-800.745
-1017.875
42
863.135
1003.190
17
-701.646
-1017.875
43
612.943
1003.190
18
-602.625
-1017.875
44
430.677
999.625
19
-503.526
-1017.875
45
267.974
1003.190
20
-404.505
-1017.875
46
168.952
1003.190
21
-305.406
-1017.875
47
59.692
1003.715
22
-206.385
-1017.875
48
-126.910
1003.190
23
-107.285
-1017.875
49
-445.130
999.100
24
-1017.875
50
-704.419
999.100
25
-8.264
90.835
-1017.875
51
-855.819
1003.190
26
189.855
-1017.875
Rev. 1.80
4
July 27, 2009
PATENTED
HT1620
Pad Description
Pad No.
Pad Name
I/O
Description
51, 1
CC1, CC2
I
External capacitor pin, for double voltage and half voltage circuit use
2
VO15N
O
Half voltage circuit output pin
3
VEE
¾
Double voltage circuit output pin
4~7
COM0~COM3
O
LCD common outputs
8~39
SEG0~SEG31
O
LCD segment outputs
40
CS
I
Chip selection input with pull-high resistor.
When the CS is logic high, the data and command, read from or written to the
HT1620 are disabled. The serial interface circuit is also reset. But if the CS is
at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1620 are all enabled.
41
RD
I
READ clock input with pull-high resistor.
Data in the RAM of the HT1620 are clocked out on the falling edge of the RD
signal. The clocked out data will appear on the DATA line. The host controller
can use the next raising edge to latch the clocked out data.
42
WR
I
WRITE clock input with pull-high resistor.
Data on the DATA line are latched into the HT1620 on the rising edge of the
WR signal.
43
DATA
I/O
Serial data input/output with pull-high resistor
44
VSS
¾
Negative power supply, Ground
45
OSCO
O
46
OSCI
I
The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock.
47
VDD
¾
Positive power supply
48
IRQ
O
Time base or WDT overflow flag, NMOS open drain output
49, 50
BZ, BZ
O
2kHz or 4kHz tone frequency output pair (tri-state output buffer)
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+3.6V
Storage Temperature ............................-50oC to 125oC
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-25oC to 75oC
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.80
5
July 27, 2009
PATENTED
HT1620
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
2.4
¾
3.3
V
VDD
Operating Voltage
¾
IDD
Operating Current
3V
See note 1
¾
2
3
mA
ISTB
Standby Current
3V
See note 2
¾
¾
1
mA
VIL
Input Low Voltage
3V
DATA, WR, CS, RD
¾
¾
0.6
V
VIH
Input High Voltage
3V
DATA, WR, CS, RD
2.4
¾
3.0
V
IOL1
DATA, BZ, BZ, IRQ
3V
VOL=0.3V
0.8
1.6
¾
mA
IOH1
DATA, BZ, BZ
3V
VOH=2.7V
-0.6
-1.2
¾
mA
IOL2
LCD Common Sink Current
3V
VOL=0.3V
80
150
¾
mA
IOH2
LCD Common Source Current
3V
VOH=2.7V
-70
-120
¾
mA
IOL3
LCD Segment Sink Current
3V
VOL=0.3V
70
140
¾
mA
IOH3
LCD Segment Source Current
3V
VOH=2.7V
-30
-60
¾
mA
RPH
Pull-high Resister
3V
DATA, WR, CS, RD
100
200
300
kW
Note:
1. No load, Buzzer Off, LCD On, system enable and CS=WR=RD=High
2. No load, Buzzer Off, LCD Off, system disable and CS=WR=RD=High
A.C. Characteristics
Symbol
fSYS
Parameter
Ta=25°C
Test Conditions
System Clock
3V
LCD Frame Frequency
¾
LCD Frame Frequency 1/2 Duty
¾
fLCD
Min.
Typ.
Max.
Unit
¾
32768
¾
Hz
¾
64
¾
Hz
¾
64
¾
Hz
¾
56
¾
Hz
¾
64
¾
Hz
n: Number of COM
¾
n/fLCD
¾
s
Write mode
4
¾
150
kHz
Read mode
¾
¾
75
kHz
¾
2.0
¾
kHz
¾
4.0
¾
kHz
CS
500
600
¾
ns
Write mode
3.34
¾
125
Read mode
6.67
¾
¾
VDD
LCD Frame Frequency 1/3 Duty
¾
LCD Frame Frequency 1/4 Duty
¾
tCOM
LCD Common Period
¾
fCLK
Serial Data Clock
3V
Conditions
Crystal 32kHz
Crystal 32kHz
Tone Frequency (2kHz)
fTONE
3V
Crystal 32kHz
Tone Frequency (4kHz)
tCS
Serial Interface Reset Pulse
Width
(Figure 3)
¾
tCLK
WR, RD Input Pulse Width
(Figure 1)
3V
t r, t f
Rise/Fall Time Serial Data Clock
Width
(Figure 1)
3V
¾
¾
120
160
ns
tSU
Setup Time for DATA to WR, RD
Clock Width
(Figure 2)
3V
¾
60
120
¾
ns
tH
Hold Time for DATA to WR, RD
Clock Width
(Figure 2)
3V
¾
500
600
¾
ns
Rev. 1.80
6
ms
July 27, 2009
PATENTED
Symbol
Test Conditions
Parameter
VDD
Conditions
HT1620
Min.
Typ.
Max.
Unit
tSU1
Setup Time for CS to WR,RD
Clock Width
(Figure 3)
3V
¾
500
600
¾
ns
tH1
Hold Time for CS to WR, RD
Clock Width
(Figure 3)
3V
¾
50
100
¾
ns
tOFF
VDD OFF Times (Figure 4)
¾
VDD drop down to 0V
20
¾
¾
ms
tSR
VDD Rising Slew Rate (Figure 4)
¾
¾
0.05
¾
¾
V/ms
Note:
1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal
Power-on Reset (POR) circuit will not operate normally.
2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions
of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for
20ms (min.) before rising to the normal operating voltage.
V A L ID D A T A
tf
W R , R D
C lo c k
tr
9 0 %
5 0 %
1 0 %
tC
V
D D
ts
L K
W R , R D
C lo c k
S
V
5 0 %
F IR S T
C lo c k
th
1
G N D
V
L A S T
C lo c k
V D D
D D
0 V
tS
tO
R
F F
G N D
Figure 4. Power-on Reset Timing
Figure 3
Rev. 1.80
D D
G N D
D D
5 0 %
u 1
V
5 0 %
Figure 2
tC
ts
D D
G N D
th
u
W R , R D
C lo c k
Figure 1
C S
V
5 0 %
G N D
tC
L K
D B
7
July 27, 2009
PATENTED
HT1620
Functional Description
Display Memory - RAM structure
Time Base and Watchdog Timer - WDT
The static display RAM is organized into 32´4 bits and
stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in
the RAM can be accessed by the READ, WRITE and
READ-MOD IFY-WRITE commands. The following is a
mapping from the RAM to the LCD patterns.
The time base generator and WDT share the same divided (¸256) counter. TIMER DIS/EN/CLR, WDT
DIS/EN/CLR and IRQ EN/DIS are independent from
each other. Once the WDT time-out occurs, the IRQ pin
will stay at a logic low level until the CLR WDT or the
IRQ DIS command is issued.
C O M 3
C O M 2
C O M 1
C O M 0
Buzzer Tone Output
S E G 0
0
S E G 1
1
S E G 2
2
S E G 3
3
A simple tone generator is implemented in the HT1620.
The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone.
A d d r e s s 6 b its
(A 5 , A 4 , ..., A 0 )
LCD Driver
The HT1620 is a 128 (32´4) pattern LCD driver. It can be
configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons of
LCD driver by the S/W configuration. This feature
makes the HT1620 suitable for multiple LCD applications. The LCD driving clock is derived from the system
clock. The value of the driving clock is always 256Hz even
when it is at a 32.768kHz crystal oscillator frequency. The
LCD corresponding commands are summarized in the table.
3 1
S E G 3 1
D
3
D
2
D
1
D
A d d r
D a ta
0
D a ta 4 b its
(D 3 , D 2 , D 1 , D 0 )
RAM Mapping
T im e B a s e
W D T E N /D IS
V D D
C L R
IR Q
T IM E R E N /D IS
/2 5 6
C lo c k S o u r c e
T im e r
W D T
/4
Q
D
IR Q
C K
E N /D IS
R
C L R W D T
Timer and WDT Configurations
Name
Command Code
Function
LCD OFF
10000000010X
Turn off LCD outputs
LCD ON
10000000011X
Turn on LCD outputs
1000010abXcX
c=0: 1/2 bias option
c=1: 1/3 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
BIAS and COM
Rev. 1.80
8
July 27, 2009
PATENTED
Interfacing
The bold form of 1 0 0, namely 1 0 0, indicates the command mode ID. If successive commands have been issued, the command mode ID will be omitted, except for
the first command. The LCD OFF command turns the
LCD display off by disabling the LCD bias generator.
The LCD ON command, on the other hand, turns the
LCD display on by enabling the LCD bias generator. The
BIAS and COM are the LCD panel related commands.
With the use of the LCD related commands, the HT1620
can be compatible with most types of LCD panels.
Only four lines are required to interface with the
HT1620. The CS line is used to initialize the serial interface circuit and to terminate the communication between
the host controller and the HT1620. If the CS pin is set to
1, the data and command issued between the host controller and the HT1620 are first disabled and then initialized. Before issuing a mode command or mode switching,
a high level pulse is required to initialize the serial interface
of the HT1620. The DATA line is the serial data input/output line. Data to be read or written or commands to be written have to be passed through the DATA line. The RD line
is the READ clock input. Data in the RAM are clocked out
on the falling edge of the RD signal, and the clocked out
data will then appear on the DATA line. It is recommended
that the host controller read in correct data during the interval between the rising edge and the next falling edge of
the RD signal. The WR line is the WRITE clock input. The
data, address, and command on the DATA line are all
clocked into the HT1620 on the rising edge of the WR signal. There is an optional IRQ line to be used as an interface between the host controller and the HT1620. The
IRQ pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host controller can
perform the time base or the WDT function by connecting
with the IRQ pin of the HT1620.
Command Format
The HT1620 can be configured by the S/W setting. There
are two mode commands to configure the HT1620 resources and to transfer the LCD display data. The configuration mode of the HT1620 is called command mode, and
its command mode ID is 1 0 0. The command mode consists of a system configuration command, a system frequency selection command, an LCD configuration
command, a tone frequency selection command, a
timer/WDT setting command, and an operating command.
The data mode, on the other hand, includes READ,
WRITE, and READ-MODIFY-WRITE operations. The following are the data mode IDs and the command mode ID:
Operation
Mode
ID
READ
Data
110
WRITE
Data
101
Data
101
Command
100
READ-MODIFY-WRITE
COMMAND
HT1620
The mode command should be issued before the data or
command is transferred. If successive commands have
been issued, the command mode ID, 1 0 0, can be omitted. While the system is operating in the non-successive
command or the non-successive address data mode,
the CS pin should be set to ²1² and the previous operation mode will be reset also. Once the CS pin returns to
²0², a new operation mode ID should be issued first.
Rev. 1.80
9
July 27, 2009
PATENTED
HT1620
Timing Diagrams
READ Mode (Command Code: 1 1 0)
C S
W R
R D
D A T A
1
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s 1 (M A 1 )
0
1
D 0 D 1 D 2 D 3
D a ta (M A 1 )
1
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s 2 (M A 2 )
0
1
D 0 D 1 D 2 D 3
D a ta (M A 2 )
READ Mode (Successive Address Reading)
C S
W R
R D
1
D A T A
1
0
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s (M A )
D 0 D 1 D 2 D 3
D a ta (M A )
D 0 D 1 D 2 D 3
D a ta (M A + 1 )
D 0 D 1 D 2 D 3
D a ta (M A + 2 )
D 0 D 1 D 2 D 3
D a ta (M A + 3 )
D 0
WRITE Mode (Command Code: 1 0 1)
C S
W R
D A T A
Rev. 1.80
1
0
1
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s 1 (M A 1 )
D 0 D 1 D 2 D 3
D a ta (M A 1 )
10
1
0
1
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s 2 (M A 2 )
D 0 D 1 D 2 D 3
D a ta (M A 2 )
July 27, 2009
PATENTED
HT1620
WRITE Mode (Successive Address Writing)
C S
W R
1
D A T A
1
0
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
M e m o ry A d d re s s (M A ) D a ta (M A )
D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 )
Note: It is recommended that the host controller should read with the data from the DATA line
between the raising edge of the RD line and the falling edge of the next RD line.
READ-MODIFY-WRITE Mode (Command Code: 1 0 1)
C S
W R
R D
D A T A
1
1
0
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s 1 (M A 1 )
D 0 D 1 D 2 D 3
D a ta (M A 1 )
D 0 D 1 D 2 D 3
D a ta (M A 1 )
1
0
1
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s 2 (M A 2 )
D 0 D 1 D 2 D 3
D a ta (M A 2 )
READ-MODIFY-WRITE Mode (Successive Address Accessing)
C S
W R
R D
D A T A
Rev. 1.80
1
0
1
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s (M A )
D 0 D 1 D 2 D 3
D a ta (M A )
D 0 D 1 D 2 D 3
D a ta (M A )
11
D 0 D 1 D 2 D 3
D a ta (M A + 1 )
D 0 D 1 D 2 D 3
D a ta (M A + 1 )
D 0 D 1 D 2 D 3
D a ta (M A + 2 )
D 0
July 27, 2009
PATENTED
HT1620
Command Mode (Command Code: 1 0 0)
C S
W R
D A T A
1
0
0
C 8
C 7
C 6
C 5 C 4 C 3 C 2 C 1
C o m m a n d 1
C 0
C 8
C o m m a n d ...
C 7
C 6
C 5 C 4 C 3 C 2 C 1
C o m m a n d i
C 0
C o m m a n d
o r
D a ta M o d e
Mode (Data And Command Mode)
C S
W R
D A T A
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
R D
Rev. 1.80
12
July 27, 2009
PATENTED
HT1620
Application Circuits
V
0 .1 m F
V
D D
D D
0 .1 m F
0 .1 m F
3 M W
C C 1
C C 2
V O 1 5 N
V E E
C S
O S C I
R D *
W R
D A T A
M C U
O S C O
H T 1 6 2 0
C ry s ta l
3 2 7 6 8 H z
O s c illa to r
B Z
R
P ie z o
IR Q *
C O M 0 ~ C O M 3
S E G 0 ~ S E G 3 1
B Z
1 /2 o r 1 /3 B ia s ; 1 /2 , 1 /3 o r 1 /4 D u ty
L C D
Note:
P a n e l
* The connection of the IRQ and RD pin is selectable depending on the requirement of the MCU.
VDD=2.4V~3.3V, VEE=-1/2 VDD, VLCD (LCD voltage)=VDD-VEE=3/2 VDD=3.6V~4.9V.
Adjust R (external pull-high resistance) to fit user¢s time base clock.
Command Summary
Name
ID
Command Code
D/C
Function
Def.
READ
110
A5A4A3A2A1A0D0D1D2D3
D
Read data from the RAM
WRITE
101
A5A4A3A2A1A0D0D1D2D3
D
Write data to the RAM
READ
MODIFY
WRITE
101
A5A4A3A2A1A0D0D D2D3
D
Read and write to the RAM
SYS DIS
100
0000-0000-X
C
Turn off both system oscillator and LCD
bias generator
SYS EN
100
0000-0001-X
C
Turn on system oscillator
LCD OFF
100
0000-0010-X
C
Turn off LCD bias generator
LCD ON
100
0000-0011-X
C
Turn on LCD bias generator
TIMER DIS
100
0000-0100-X
C
Disable time base output
Yes
WDT DIS
100
0000-0101-X
C
Disable WDT time-out flag output
Yes
TIMER EN
100
0000-0110-X
C
Enable time base output
WDT EN
100
0000-0111-X
C
Enable WDT time-out flag output
TONE OFF
100
0000-1000-X
C
Turn off tone outputs
CLR TIMER
100
0000-1101-X
C
Clear the contents of the time base
generator
CLR WDT
100
0000-111X-X
C
Clear the contents of the WDT stage
BIAS 1/2
100
0010-abX0-X
C
LCD 1/2 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
Rev. 1.80
13
Yes
Yes
Yes
July 27, 2009
PATENTED
Name
ID
Command Code
D/C
HT1620
Function
BIAS 1/3
100
0010-abX1-X
C
LCD 1/3 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
TONE 4K
100
010X-XXXX-X
C
Tone frequency, 4kHz
TONE 2K
100
0110-XXXX-X
C
Tone frequency, 2kHz
IRQ DIS
100
100X-0XXX-X
C
Disable IRQ output
IRQ EN
100
100X-1XXX-X
C
Enable IRQ output
F1
100
101X-0000-X
C
Time base clock output: 1Hz
The WDT time-out flag after: 4s
F2
100
101X-0001-X
C
Time base clock output: 2Hz
The WDT time-out flag after: 2s
F4
100
101X-0010-X
C
Time base clock output: 4Hz
The WDT time-out flag after: 1s
F8
100
101X-0011-X
C
Time base clock output: 8Hz
The WDT time-out flag after: 1/2s
F16
100
101X-0100-X
C
Time base clock output: 16Hz
The WDT time-out flag after: 1/4s
F32
100
101X-0101-X
C
Time base clock output: 32Hz
The WDT time-out flag after: 1/8s
F64
100
101X-0110-X
C
Time base clock output: 64Hz
The WDT time-out flag after: 1/16s
F128
100
101X-0111-X
C
Time base clock output: 128Hz
The WDT time-out flag after:1/32s
TEST
100
1110-0000-X
C
Test mode, user don¢t use.
100
1110-0011-X
C
Normal mode
NORMAL
Note:
Def.
Yes
Yes
Yes
,
X: Don t care
A5~A0: RAM addresses
D3~D0: RAM data
D/C: Data/command mode
Def.: Power on reset default
All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command
mode ID. If successive commands have been issued, the command mode ID except for the first command will
be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from a
32.768kHz crystal oscillator. Calculation of the frequency is based on the system frequency sources as stated
above. It is recommended that the host controller should initialize the HT1620 after power on reset, for power
on reset may fail, which in turn leads to malfunctioning of the HT1620.
Rev. 1.80
14
July 27, 2009
PATENTED
HT1620
Package Information
64-pin LQFP (7mm´7mm) Outline Dimensions
C
D
4 8
G
3 3
H
I
3 2
4 9
F
A
B
E
6 4
1 7
K
a
J
1 6
1
Symbol
A
Rev. 1.80
Dimensions in mm
Min.
Nom.
Max.
8.9
¾
9.1
B
6.9
¾
7.1
C
8.9
¾
9.1
D
6.9
¾
7.1
E
¾
0.4
F
0.13
G
1.35
¾
H
¾
¾
1.6
I
0.05
¾
0.15
¾
0.23
1.45
J
0.45
¾
0.75
K
0.09
¾
0.20
a
0°
¾
7°
15
July 27, 2009
PATENTED
HT1620
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103
Tel: 86-21-5422-4590
Fax: 86-21-5422-4705
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2009 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.80
16
July 27, 2009