RFM42/43 RF M 42/ 43 ISM T R A N SMI T T E R Mo d u l e V1. 1 Features Frequency Range = 240–930 MHz Output Power Range Integrated 32 kHz RC or 32 kHz XTAL ◆ +8 to +17 dBm (RFM42) Integrated voltage regulators ◆ –8 to +13 dBm (RFM43) Configurable packet structure TX 64 byte FIFO Low battery detector Temperature sensor and 8-bit ADC –40 to +85 °C temperature range Integrated voltage regulators Frequency hopping capability FSK, GFSK, and OOK modulation Power-on-reset (POR) Low Power Consumption ◆ (RFM42) 60 mA @ +17 dBm 27 mA @ +11 dBm ◆ (RFM43) 28 mA @ +13 dBm 16 mA @ +1 dBm Data Rate = 1 to 128 kbps Power Supply = 1.8 to 3.6 V Ultra low power shutdown mode Wake Up Timer RFM42/43 Applications ■ Remote control Remote keyless entry Remote meter reading ■Telemetry Home automation ■Personal Industrial control Sensor networks Health monitors ■Home ■Toy ■ security & alarm data logging control Wireless PC peripherals Description The RFM42/43 is low cost ISM transmitter module and offers advanced radio features including continuous frequency coverage from 240–930 MHz with adjustable power output levels of –8 to +13 dBm on the RFM43 and +8 to +17 dBm on the RFM42. Power adjustments are made in 3 dB steps. The RFM42‘s Industry leading +17 dBm output power ensures extended range and improved link performance. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX FIFO, and automatic packet handling reduce overall current consumption and allow the use of lower-cost system MCUs. An integrated temperature sensor, general purpose ADC, power-on-reset (POR), and GPIOs further reduce overall system cost and size. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and reduced spectral spreading ensuring compliance with FCC and ETSI regulations. 1 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 TABLE OF CONTENTS Section Page 1. Electrical Specifications . . .. . . ….. . … … . . . . . . …….. . . . . . . . . . . . . . . . ….. . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . ……. . . . . . . . . … . . . . . . . . . .10 2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . ……. . . . . . . . . .. . . . . . . . . . . .10 3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . ……. . . . . . . . . . … . . . . . . . . . . .11 3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . ……. . . . . . . . . . .. . . . . . . . . . . .11 3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . …… . . . . . . . . . ... . . . . . . . . . . .13 3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….... . . . . . . . . . . … . . . . . . . . . . . .16 3.4. Device Code . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . . . . .. . . . . . . . . . . . .16 3.5. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . . . … . . . . . . . . . . . . .17 3.6. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . .. . . . . . . . . . . . . . .18 4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …… . . .. . . . . . . . . . . . . . . .23 4.1. Modulation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …… . . ... . . . . .. . . . . . . . . . .23 4.2. Modulation Data Source . . . . . . . . . . . . . . . . . . . . . …... . . . .. . . . .. . . . . . . . . . . . .24 4.3. FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ….... . . . . .. . . . . . . . . . . . . . . . . .24 4.4. Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . …… . . . … . . . . . . . . . . . . . . . . . . . .24 4.5. PN9 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …….. . . . . . . . . . . . . . . . . . . .25 4.6. Synchronous vs. Asynchronous . . . . . . . . . . . . . . . . . ……... . . . . . . . . . . . . . . .. . . .25 5. Internal Functional Blocks . . . . . . . . . . . . . . .. . .. . .. .. . . .. … . . . .. . . . . .. . . . . . . . . . . .26 5.1. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . .. .. . . . . . . . . . . . . . . . . . . . . .26 5.2. Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . …... . . .. . . . . .. . . . . . . . . . . . . . . . . .27 5.3. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . …….. . . . . .. . . . . . . . . . . . . . . . . .28 5.4. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….... . . . . . . . . . . . . . . . . . . . . . . .28 6. Data Handling and Packet Handler . . . . . . . . . . . . . . …... . . . . . . . . . . . . . . . . . . . . . . ..29 6.1. TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . … . . . . . . . . . . . . . . . . . . . . . .29 6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . ….. . . . .. . . . . . . .. . . . . . . . . . . . . .30 6.3. Packet Handler TX Mode . . . . . . . . . . . . . . . . . . . . …... . . . . . . . … . . . . . . . . . . . . .30 6.4. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . … …... . . . . . . . . . . .32 6.5. TX Retransmission and Auto TX . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . . . . . .32 7. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …….. . . . . . . . . . . . . . .33 7.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . … . . ….. . . . . . . . . . . . .33 7.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ….. . . . . . . . . . . .34 7.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . ….... .. . . . . . . . . . . . . . . . .35 7.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . ….. ... . . . . . . . . . . . . . . . . . .38 7.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . ….. . . .. . . . . . . . . . . . . . . . . . .40 7.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. ... . . . . . . . . . . . . . . . . . . .41 7.7. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... …. . .. . . . . . . . . . . . . . .43 8. Reference Design..............................................................................................................44 9. Measurement Results . . . . . . . . . . . . . . . . . . . . .. . . . . . . . ... . . . . . . . . . . . …. . . . . . . . .45 2 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 10. Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .48 10.1. Complete Register Table and Descriptions . . . . . . . . . . .. . . . . . . . …. . . . . . . . . .48 11. Pin Descriptions: RFM42/43 . . . . . . .. . . . . . . . . . . . . . . . … . . . . . . . . . .... . . . . . . . . .103 12. Mechanical Dimension: RFM42/43. . . . . . . . . . . . . . … . . . . .. . . . . . … . . . . . . . . . . .105 13.Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . .. . . . . . . . . . . . . . 107 16. Errata Status Summary................................................................................................108 17. Errata Details.................................................................................................................109 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . … . . . . . . . . . . . .. . . . . . . . .110 3 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 1. Electrical Specifications Table 1. DC Characteristics Parameter Supply Symbol Voltage Range Power Saving Modes Conditions Vdd IShutdown RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF2 Min Typ Max Units 1.8 3.0 3.6 V 10 TBD nA — Low Power Digital Regulator ON (Register values IStandby retained) and Main Digital Regulator, and RC 400 — nA — Oscillator OFF1 RC Oscillator and Low Power Digital Regulator ON ISleep (Register values retained) and Main Digital Regulator 800 — nA — OFF1 ISensor-L BD ISensor-T S IReady ITune TX Mode Current for ITX_+17 RFM42 ITX_+11 TX Mode Current for ITX_+13 RFM43 ITX_+1 TUNE Mode Current Main Digital Regulator and Low Battery Detector ON, Crystal Oscillator and all other blocks OFF2 Main Digital Regulator and Temperature Sensor ON, Crystal Oscillator and all other blocks OFF2 Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled1 — — — 1 1 600 — — — μA μA μA Synthesizer and regulators enabled — 9.5 — mA txpow[2:0] = 011 (+17 dBm), VDD = 3.3 V — 60 — mA txpow[2:0] = 000 (+11 dBm), VDD = 3.3 V — 27 — mA txpow[2:0] = 111 (+13 dBm), VDD = 3.3 V — 28 — mA txpow[2:0] = 100 (+1 dBm), VDD = 3.3 V — 16 — mA Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. 4 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Table 2. Synthesizer AC Electrical Characteristics2 Parameter Symbol Conditions Min Typ Max Units Synthesizer FSYNTH-LB FSYNTH-HB FRES-LB Low Band 240 — 480 MHz High Band 480 — 930 MHz Low Band — 156.25 — Hz FRES-HB High Band — 312.5 — Hz fREF fcrystal /3 — 10 — MHz 0.7 — 1.6 V — 200 — μs — 2 4 kHzRMS △F = 10 kHz — –80 — dBc/Hz △F = 100 kHz — –90 — dBc/Hz △F = 1 MHz — –115 — dBc/Hz △F = 10 MHz — –130 — dBc/Hz Frequency Range Synthesizer Frequency Resolution2 Reference Frequency Reference Frequency Input When using reference frequency instead fREF_LV of crystal. Measured peak-to-peak (VPP) Level2 Synthesizer Settling Measured from leaving Ready mode with tLOCK Time2 XOSC running to any frequency includ-ing VCO Calibration Residual FM2 Phase Noise2 △FRMS Lφ (fM) Integrated over ± 250 kHz bandwidth (500 Hz lower bound of integration) Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. 5 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Table 3. Transmitter AC Electrical Characteristics Parameter TX Frequency Range1 FSK Modulation Data Rate2 OOK Modulation Data Rate2 Symbol Output Power Range1 (RFM43) Max Output Power(RFM43) Output Power Range1 (RFM42) Max Output Power(RFM42) TX RF Output Steps2 Min Typ Max Unit 240 — 480 480 — 930 DRFSK 1 — 128 kbps DROOK 1.2 — 40 kbps ±320 kHz FSYNTH-LB FSYNTH-HB Low Band High Band Production tests maximum limit of 320 Δf Deviation1 Deviation Resolution Conditions s Modulation Modulation 1 kHz ΔfRES ±0.625 MHz — 0.625 — kHz –8 — +13 dBm +11 +13 — dBm +8 — +17 dBm +15 +17 — dBm controlled by txpow[2:0] Register — 3 — dB PRF_V Measured from VDD=3.6 V to VDD=1.8 V — 2 — dB PRF_TEMP –40 to +85 ℃ — 2 — dB — 1 — dB — 0.5 — — — –54 dBm — — –54 dBm Power control by txpow[2:0] Register PTX Production test at txpow[2:0] = 11 Tested at 915 MHz PTX_max Tested at 315-915 MHz Power control by txpow[2:0] Register PTX Production test at txpow[2:0] = 11 Tested at 915 MHz PTX_max PRF_OUT Tested at 315-915 MHz TX RF Output Level Variation vs. Voltage2 TX RF Output Level2 Variation vs. Temperature TX RF Output Level Variation vs. PRF_FREQ Measured across any one frequency band Frequency2 Transmit Modulation Filtering2 Spurious Emissions2 Gaussian B*T Filtering Bandwith Time Product POB-TX1 POB-TX2 POUT =11dBm, Frequencies <1 GHz 1–12.75 GHz, excluding harmonics Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. 6 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 1 Table 4. Auxiliary Block Specifications Parameter Symbol Min Typ Max Units — 0.5 — °C TSS — 5 — mV/°C LBDRES — 50 — mV LBDCT — 250 — μs 32.768K — 30M Hz ADCENB — 8 — bit ADCRES — 4 — mV ADCCT — 305 — μsec t30M — 1 — ms 30MRES — 97 — fF — 6 — sec — 100 — ppm — 2500 — ppm — 16 — ms — 100 — μs Temperature Sensor TSA Accuracy2 Temperature Sensor Sensitivity2 Low Battery Detector Resolution2 Low Battery Detector Conversion Time2 Conditions When calibrated using temp sensor offset register Microcontroller Clock Configurable to 30 MHz, Output Frequency 15 MHz, 10 MHz, 4 MHz, MC 3 MHz, 2 MHz, 1 MHz, or 32.768 kHz General Purpose ADC Accuracy2 General Purpose ADC Resolution2 Temp Sensor & General Purpose ADC Conversion Time2 30 MHz XTAL Start-Up time 30 MHz XTAL Cap Resolution2 32 kHz XTAL Start-Up t32K XTAL 32KRES Time2 32 kHz Accuracy2 32 kHz RC OSC 32KRCRES Accuracy2 POR Reset Time Software Reset Time2 tPOR tsoft Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. 7 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) Parameter Symb Conditions Min Typ Max Units ol Rise Time TRISE 0.1 x VDD to 0.9 x VDD, CL= 5 pF — — 8 ns Fall Time TFALL 0.9 x VDD to 0.1 x VDD, CL= 5 pF — — 8 ns Input Capacitance CIN — — 1 pF Logic High Level Input Voltage VIH VDD – 0.6 — — V Logic Low Level Input Voltage VIL — 0.6 V Input Current Logic High Level Output Voltage IIN VOH 0<VIN< VDD IOH<1 mA source, VDD=1.8 V –100 VDD – 0.6 — — 100 — nA V Logic Low Level Output Voltage VOL IOL<1 mA sink, VDD=1.8 V — — 0.6 V Min Typ Max Units — — 8 ns — — 8 ns 1 pF Note: All specification guaranteed by production test unless otherwise noted. Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) Parameter Symbol Rise Time TRISE Fall Time TFALL Conditions 0.1 x VDD to 0.9 x VDD, CL= 10 pF, DRV<1:0>=HH 0.9 x VDD to 0.1 x VDD, CL= 10 pF, DRV<1:0>=HH Input Capacitance CIN — — Logic High Level Input Voltage VIH VDD – 0.6 — Logic Low Level Input Voltage VIL — — 0.6 V Input Current IIN –100 — 100 nA VIL=0 V 5 — 25 Input Current If Pullup is Activated Maximum Output Current 0<VIN< VDD IINP V IOmaxLL DRV<1:0>=LL 0.1 0.5 0.8 mA IOmaxLH DRV<1:0>=LH 0.9 2.3 3.5 mA IOmaxHL DRV<1:0>=HL 1.5 3.1 4.8 mA IOmaxHH DRV<1:0>=HH IOH< IOmax source, VDD=1.8 V IOL< IOmax sink, VDD=1.8 V 1.8 3.6 5.4 mA VDD – 0.6 — — V — — 0.6 V Logic High Level Output Voltage VOH Logic Low Level Output Voltage VOL Note: All specification guaranteed by production test unless otherwise noted. 8 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Table 7. Absolute Maximum Ratings Parameter Value Unit VDD to GND –0.3, +3.6 V VDD to GND on TX Output Pin –0.3, +8.0 V Voltage on Digital Control Inputs –0.3, VDD + 0.3 V Voltage on Analog Inputs –0.3, VDD + 0.3 V –40 to +85 ℃ Thermal Impedance θ JA 30 ℃/W Junction Temperature TJ +125 ℃ –55 to +125 ℃ Operating Ambient Temperature Range T A Storage Temperature Range TSTG Note: Stresses beyond those listed under ―Absolute Maximum Ratings‖ may cause permanent damage to the device. These are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Caution: ESD sensitive device. Power Amplifier may be damaged if switched on without proper load or termination connected. 9 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 2. Functional Description The RFM42/43 is low cost ISM wireless transmitter module with continuous frequency tuning over the complete 240–930 MHz band. The wide operating voltage range of 1.8–3.6 V and low current consumption makes the RFM42/43 and ideal solution for battery powered applications. A high precision local oscillator (LO) is used for transmit mode. The LO is generated by an integrated VCO and △∑Fractional-N PLL synthesizer. The synthesizer is designed to support configurable data rates, output frequency,frequency deviation, and Gaussian filtering at any frequency between 240–930 MHz. The transmit FSK data is modulated directly into the △∑data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted spectral content. The RFM42‘s PA output power can be configured between +8 and +17 dBm in 3 dB steps, while the RFM43's PA output power can be configured between –8 and +13 dBm in 3 dB steps. The PA incorporates automatic ramp-up and ramp-down control to reduce unwanted spectral spreading. The RFM42/43 is designed to work with a microcontroller to create a very low cost system. Voltage regulators are integrated on-chip which allow for a wide range of operating supply voltage conditions from +1.8 to +3.6 V. A standard 4-pin SPI bus is used to communicate with the microcontroller. Three configurable general purpose I/Os are available for use to tailor towards the needs of the system. A more omplete list of the available GPIO functions is shown in "7. Auxiliary Functions" but just to name a few, microcontroller clock output, POR, and specific interrupts. 2.1. Operating Modes The RFM42/43 provides several modes of operation which can be used to optimize the power consumption of the device application. Table 8 summarizes the modes of operation of the RFM42/43. In general, any given mode of operation may be classified as an Active mode or a Power Saving mode. The table indicates which block(s) are enabled (active) in each corresponding mode. With the exception the Shutdown mode, all can be dynamically selected by sending the appropriate commands over the SPI in order to optimize the average current consumption. An ―X‖ in any cell means that, in the given mode of operation, that block can be independently programmed to be either ON or OFF, without noticeably affecting the current consumption. The SPI circuit block includes the SPI interface and the register space. The 32 kHz OSC circuit block includes the 32.768 kHz RC oscillator or 32.768 kHz crystal oscillator, and wake-up timer. AUX (Auxiliary Blocks) includes the temperature sensor, general purpose ADC, and low-battery detector. Table 8. Operating Modes RFM43 10 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 3. Controller Interface 3.1. Serial Peripheral Interface (SPI) The RFM42/43 communicates with the host MCU over a 3 wire SPI interface: SCLK, SDI, and nSEL. The host MCU can also read data from internal registers on the SDO output pin. A SPI transaction is a 16-bit sequence which consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA), as demonstrated in Figure 1. The 7-bit address field supports reading from or writing to one of the 128, 8-bit control registers. The R/W select bit determines whether the SPI transaction is a write or read transaction. If R/W = 1, it signifies a WRITE transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are latched into the RFM42/43 every eight clock cycles. The timing parameters for the SPI interface are shown in Table 9. The SCLK rate is flexible with a maximum rate of 10 MHz. To read back data from the RFM42/43, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored when R/W = 0. The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the selected register will be available on the SDO output pin. The READ function is shown in Figure 2. After the READ function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the last data bit clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup. 11 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Figure 2. SPI Timing—READ Mode The SPI interface contains a burst read/write mode which will allows for reading/writing sequential registers without having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI interface will automatically increment the ADDR and read from/write to the next address. An SPI burst write transaction is demonstrated in Figure 3 and burst read in Figure 2. As long as nSEL is held low, input data will be latched into the RFM42/43 every eight SCLK cycles. A burst read transaction is also demonstrated in Figure 4. Figure 4. SPI Timing—Burst Read Mode 12 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 3.2. Operating Mode Control There are three primary states in the RFM42/43 radio state machine: SHUTDOWN, IDLE, and TX (see Figure 5). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different configurations/options for the IDLE state which can be selected to optimize the module to the applications needs. "Register 07h. Operating Mode and Function Control 1" controls which operating mode/state is selected. The TX state may be reached automatically from any of the IDLE states by setting the txon bit in "Register 07h. Operating Mode and Function Control 1". Table 10 shows each of the operating modes with the time required to reach TX mode as well as the current consumption of each mode. The output of the LPLDO is internally connected in parallel to the output of the main digital regulator (and is available externally at the VR_DIG pin); this common digital supply voltage is connected to all digital circuit blocks,including the digital modem, crystal oscillator, and SPI and register space. The LPLDO has extremely low quiescent current consumption but limited current supply capability; it is used only in the IDLE-STANDBY and IDLE-SLEEP modes. RFM42: Parameter VDD to GND RFM43: VDD to GND on TX Output Pin Voltage on Digital Control Inputs Voltage on Analog Inputs Operating Ambient Temperature R Thermal Impedance θ JA Junction Temperature TJ Storage Temperature Range TSTG Note: Stresses beyond those listed un stress ratings only and functional 13not implied. Expo specifications is Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] reliability. Caution: ESD sensitive http://www.hoperf.com Power Amplifier may be damage RFM42/43 3.2.1. Shutdown State The shutdown state is the lowest current consumption state of the device with nominally less than 10 nA of current consumption. The shutdown state may be entered by driving the SDN pin high. The SDN pin should be held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the contents of the registers are lost and there is no SPI access. When the module is connected to the power supply, a POR will be initiated after the falling edge of SDN. 3.2.2. Idle State There are four different modes in the IDLE state which may be selected by "Register 07h. Operating Mode and Function Control 1". All modes have a tradeoff between current consumption and response time to TX mode. This tradeoff is shown in Table 10. After the POR event, SWRESET, or exiting from the SHUTDOWN state the module will default to the IDLE-READY mode. After a POR event the interrupt registers must be read to properly enter the SLEEP, SENSOR, or STANDBY mode and to control the 32 kHz clock correctly. 3.2.2.1. STANDBY Mode STANDBY mode has the lowest current consumption possible with only the LPLDO enabled to maintain the register values. In this mode the registers can be accessed in both read and write mode. The standby mode can be entered by writing 0h to "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Additionally, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 3.2.2.2. SLEEP Mode In SLEEP mode the LPLDO is enabled along with the Wake-Up-Timer, which can be used to accurately wake-up the radio at specified intervals. See "7.6. Wake-Up Timer" for more information on the Wake-Up-Timer. Sleep mode is entered by setting enwt = 1 (40h) in "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Also, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 3.2.2.3. SENSOR Mode In SENSOR Mode either the Low Battery Detector, Temperature Sensor, or both may be enabled in addition to the LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 and the temperature sensor can be enabled by setting ents = 1 in "Register 07h. Operating Mode and Function Control 1". See "7.4. Temperature Sensor" and "7.5. Low Battery Detector" for more information on these features. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve theminimum current consumption. 3.2.2.4. READY Mode READY Mode is designed to give a fast transition time to TX mode with reasonable current consumption. In this mode the Crystal oscillator remains enabled reducing the time required to switch to the TX mode by eliminating the crystal start-up time. Ready mode is entered by setting xton = 1 in "Register 07h. Operating Mode and Function Control 1". To achieve the lowest current consumption state the crystal oscillator buffer should be disabled. This is done by setting "Register 62h. Crystal Oscillator/Power-on-Reset Control" to a value of 02h. To exit ready mode, bufovr (bit 1) of this register must be set back to 0. 3.2.2.5. TUNE Mode In TUNE Mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This will give the fastest response to TX mode as the PLL will remain locked but it results in the highest current consumption. This mode of operation is designed for Frequency Hopping Systems (FHS). Tune mode is entered by setting pllon= 1 in "Register 07h. Operating Mode and Function Control 1". It is not necessary to set xton to 1 for this mode, the internal state machine automatically enables the crystal oscillator. 14 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 3.2.3. TX State The TX state may be entered from any of the IDLE modes when the txon bit is set to 1 in "Register 07h. Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to ramping up the PA to prevent unwanted spectral splatter. The following sequence of events will occur automatically when going from STANDBY mode to TX mode by setting the txon bit. 1. Enable the Main Digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is ―0‖, default value is ―1‖). 5. Wait until PLL settles to required transmit frequency (controlled by timer). 6. Activate Power Amplifier and wait until power ramping is completed (controlled by timer). 7. Transmit Packet. The first few steps may be eliminated depending on which IDLE mode the module is configured to prior to setting the txon bit. By default, the VCO and PLL are calibrated every time the PLL is enabled. If the ambient temperature is constant and the same frequency band is being used these functions may be skipped by setting the appropriate bits in "Register 55h. Calibration Control". 3.2.4. Device Status Add R/W Function/Description 02 R Device Status D7 D6 D5 D4 ffovfl ffunfl Reserved Reserved D3 D2 D1 D0 cps[1] cps[0] POR Def. —— The operational status of the module can be read from "Register 02h. Device Status". 15 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 3.3. Interrupts The RFM42/43 is capable of generating an interrupt signal when certain events occur. The module notifies the microcontroller that an interrupt event has been detected by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h–04h) containing the active Interrupt Status bit; the nIRQ output signal will then be reset until the next change in status is detected. All of the interrupts must be enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h–06h). All enabled interrupt bits will be cleared when the microcontroller reads the interrupt status register. If the interrupt is not enabled when the event occurs inside of the module it will nottrigger the nIRQ pin, but the status may still be read correctly at anytime in the Interrupt Status registers. Add R/W 03 R 04 Function/De POR D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Status 1 ifferr itxffafull itxffaem Reserved iext ipksent Reserved Reserved — R Interrupt Status 2 Reserved Reserved Reserved Reserved iwut ilbd ichiprdy ipor — 05 R/W Interrupt Enable1 enfferr entxffafull entxffaem Reserved enext Reserved Reserved 00h 06 R/W enchiprdy enpor 01h scription Def. enpks ent Interrupt Enable 2 Reserved Reserved Reserved Reserved enwut enlbd See ―Register 03h. Interrupt/Status 1,‖ and ―Register 04h. Interrupt/Status 2,‖ for a complete list of interrupts. 3.4. Device Code The device version code is readable from "Register 01h. Version Code (VC)". This is a read only register. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. Notes 01 R Device Version 0 0 0 vc[4] vc[3] vc[2] vc[1] vc[0] 00h DV 16 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 3.5. System Timing The system timing for TX mode is shown in Figure 6. The timing is shown transitioning from STANDBY mode to TX mode and going automatically through the built-in sequencer of required steps. If a small range of frequencies is being used and the temperature range is fairly constant a calibration may only be needed at the initial power up of the device. The relevant system timing registers are shown below. Function/De Add R/W 53 R/W PLL Tune Time 54 R/W Reserved 1 55 R/W scription D7 D6 D5 D4 D3 D2 pllts[4:0] X X X Calibration xtalstart adccaldo Control half ne D1 D0 pllt0[2:0] X X enrcfcal rccal X Vcoca ldp POR Def. 45h X X 00h vcocal skipvco 04h The VCO will automatically calibrate at every frequency change or power up. The VCO CAL may also be forced by setting the vcocal bit. The 32.768 kHz RC oscillator is also automatically calibrated but the calibration may also be forced. The enrcfcal will enable the RC Fine Calibration which will occur every 30 seconds. The rccal bit will force a complete calibration of the RC oscillator which will take approximately 2 ms. The PLL T0 time is to allow for bias settling of the VCO, the default for this should be adequate. The PLL TS time is for the settling time of the PLL, which has a default setting of 200 μs. This setting should be adequate for most applications but may be reduced if small frequency jumps are used. For more information on the PLL register configuration options, see ―Register 53h. PLL Tune Time,‖ and ―Register 55h. Calibration Control,‖. Figure 6. TX Timing 17 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 3.6. Frequency Control 3.6.1. Frequency Programming In order to transmit an RF signal, the desired channel frequency, fcarrier, must be programmed into the RFM42/43.Note that this frequency is the center frequency of the desired channel and not an LO frequency. The carrier frequency is generated by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and the rd clock of the (3 order) ΔΣ modulator. This modulator uses modulo 64000 accumulators. This design was made to obtain the desired frequency resolution of the synthesizer. The overall division ratio of the feedback loop consist of an integer part (N) and a fractional part (F).In a generic sense, the output frequency of the synthesizer is: fout = 10MHz x (N + F) The fractional part (F) is determined by three different values, Carrier Frequency (fc[15:0]), Frequency Offset (fo[8:0]), and Frequency Modulation (fd[7:0]). Due to the fine resolution and high loop bandwidth of the synthesizer, FSK modulation is applied inside the loop and is done by varying F according to the incoming data; this is discussed further in "3.6.4. Frequency Deviation". Also, a fixed offset can be added to fine-tune the carrier frequency and counteract crystal tolerance errors. For simplicity assume that only the fc[15:0] register will determine the fractional component. The equation for selection of the carrier frequency is shown below: f carrier = 10MHz x (hbsel + 1) x (N + F) fc[15: 0] fTX =10MHz *(hbsel+ 1)*( fb[4 : 0] +24+ 64000 ) POR Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 73 R/W Frequency Offset 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h 74 R/W Frequency Offset2 fo[9] fo[8] 00h 75 R/W Frequency Band Select fb[1] fb[0] 35h 76 R/W fc[9] fc[8] BBh 77 R/W fc[1] fc[0] 80h Nominal Carrier Frequency 1 Nominal Carrier Frequency 0 sbsel hbsel fb[4] fc[15] fc[14] fc[13] fc[12] fc[7] fc[6] fc[5] fc[4] fb[3] fb[2] fc[11 fc[1 ] 0] fc[3] fc[2] Def. The integer part (N) is determined by fb[4:0]. Additionally, the output frequency can be halved by connecting a ÷2 divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in "Register 75h. Frequency Band Select". This effectively partitions the entire 240–930 MHz frequency range into two separate bands: High Band (HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of fb[4:0] is from 0 to 23. If a higher value is written into the register, it will default to a value of 23. The integer part has a fixed offset of 24 added to it as shown in the formula above. Table 11 demonstrates the selection of fb[4:0] for the corresponding frequency band. After selection of the fb (N) the fractional component may be solved with the following equation: ( 10MHz *f(hbsel + 1) fc[15:0]= TX - fb[4:0]-24) * 64000 fb and fc are the actual numbers stored in the corresponding registers. 18 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Table 11. Frequency Band Selection fb[4:0] Value N 0 Frequency Band hbsel=0 hbsel=1 24 240–249.9 MHz 480–499.9 MHz 1 25 250–259.9 MHz 500–519.9 MHz 2 26 260–269.9 MHz 520–539.9 MHz 3 27 270–279.9 MHz 540–559.9 MHz 4 28 280–289.9 MHz 560–579.9 MHz 5 29 290–299.9 MHz 580–599.9 MHz 6 30 300–309.9 MHz 600–619.9 MHz 7 31 310–319.9 MHz 620–639.9 MHz 8 32 320–329.9 MHz 640–659.9 MHz 9 33 330–339.9 MHz 660–679.9 MHz 10 34 340–349.9 MHz 680–699.9 MHz 11 35 350–359.9 MHz 700–719.9 MHz 12 36 360–369.9 MHz 720–739.9 MHz 13 37 370–379.9 MHz 740–759.9 MHz 14 38 380–389.9 MHz 760–779.9 MHz 15 39 390–399.9 MHz 780–799.9 MHz 16 40 400–409.9 MHz 800–819.9 MHz 17 41 410–419.9 MHz 820–839.9 MHz 18 42 420–429.9 MHz 840–859.9 MHz 19 43 430–439.9 MHz 860–879.9 MHz 20 44 440–449.9 MHz 880–899.9 MHz 21 45 450–459.9 MHz 900–919.9 MHz 22 46 460–469.9 MHz 920–930.0 MHz 23 47 470–479.9 MHz — The module will automatically shift the frequency of the Synthesizer down by 937.5 kHz (30 MHz ÷ 32) to achieve the correct Intermediate Frequency (IF). 19 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 3.6.2. Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrier frequency of the RFM42/43, it is often easier to think in terms of ―channels‖ or ―channel numbers‖ rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h–77h, as described above. Registers 79h and 7Ah are then used to set a channel step size and channel number, relative to the nominal setting. The Frequency Hopping Step Size (fhs[7:0]) is set in increments of 10 kHz with a maximum channel step size of 2.56 MHz. The Frequency Hopping Channel Select Register then selects channels based on multiples of the step size. Fcarrier= Fnom + fhs[7 : 0] X ( fhch[7 : 0] X 10kHz) For example: if the nominal frequency is set to 900 MHz using Registers 73h–77h and the channel step size is set to 1 MHz using "Register 7Ah. Frequency Hopping Step Size". For example, if the "Register 79h. Frequency Hopping Channel Select" is set to 5d, the resulting carrier frequency would be 905 MHz. Once the nominal frequency and channel step size are programmed in the registers, it is only necessary to program the fhch[7:0] register in order to change the frequency. Add R/W 79 R/W 7A R/W Function/Descript ion Frequency Hopping Channel Select Frequency Hopping Step Size POR D7 D6 D5 D4 D3 D2 D1 D0 fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch [2] fhch [1] fhch [0] 00h fhs[7] fhs[6] fhs[5] fhs[4] fhs[3] fhs[2] fhs[1] fhs[0] 00h Def. 3.6.3. Automatic Frequency Change If registers 79h or 7Ah are changed in TX mode, the state machine will automatically transition the module back to tune and change the frequency. This feature is useful to reduce the number of SPI commands required in a Frequency Hopping System. This in turn reduces microcontroller activity, reducing current consumption. 3.6.4. Frequency Deviation The peak frequency deviation is configurable from ±1 to ±320 kHz. The Frequency Deviation (Δf) is controlled by the Frequency Deviation Register (fd), address 71 and 72h, and is independent of the carrier frequency setting. When enabled, regardless of the setting of the hbsel bit (high band or low band), the resolution of the frequency deviation will remain in increments of 625 Hz. When using frequency modulation the carrier frequency will deviatefrom the nominal center channel carrier frequency by ±Δf: △ f = fd [8: 0] X 625Hz △f fd [8: 0] = 625Hz △f = peak deviation 20 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Figure 7. Frequency Deviation The previous equation should be used to calculate the desired frequency deviation. If desired, frequency modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center frequency; see "4.1. Modulation Type" for further details. Add R/W 71 R/W 72 R/W Function/Des cription Modulation Mode Control 2 Frequency Deviation POR D7 D6 D5 D4 D3 D2 D1 D0 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h fd [7] fd [6] fd [5] fd [4] fd [3] fd [1] fd [0] 43h fd [2] Def. 21 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 3.6.5. Frequency Offset Adjustment A frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The frequency offset adjustment is implemented by shifting the Synthesizer Local Oscillator frequency. This register is a signed register so in order to get a negative offset you will need to take the twos complement of the positive offset number. The offset can be calculated by the following: DesiredOffset = 156.25Hz x (hbsel + 1) x fo[9 : 0] DesiredOffset fo[9 : 0] = 156.25Hz x (hbsel + 1) The adjustment range in high band is: ±160 kHz, and adjustment range in low band is: ±80 kHz. For example to compute an offset of +50 kHz in high band mode fo[9:0] should be set to 0A0h. For an offset of –50 kHz in high band mode the fo[9:0] register should be set to 360h. Function/Descri Add R/W 73 R/W Frequency Offset 74 R/W Frequency Offset ption D7 D6 D5 D4 D3 D2 D1 D0 POR Def. fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[1] 00h fo[9] fo[8] 43h Notes 73 3.6.6. TX Data Rate Generator The data rate is configurable between 1–128 kbps. For data rates below 30 kbps the‖txdtrtscale‖ bit in register 70hshould be set to 1. When higher data rates are used this bit should be set to 0. The TX date rate is determined by the following formula: DR_ TX = txdr[15:0] x1MHz 216+5*xdtrtscale txdr[15:0] = DR_ TX X 2 16+5*xdtrtscale 1MHz The txdr register may be found in the following registers. Add R/W 6E R/W 6F R/W Function/Des D7 D6 D5 D4 D3 D2 D1 D0 POR Def. TX Data Rate 1 txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[10] txdr[9] txdr[8] 0Ah TX Data Rate 0 txdr[7] txdr[6] txdr[5] txdr[4] txdr[3] txdr[2] txdr[1] txdr[0] AAh cription 22 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 4. Modulation Options 4.1. Modulation Type The RFM42/43 supports three different modulation options: Gaussian Frequency Shift Keying (GFSK), Frequency Shift Keying (FSK), and On-Off Keying (OOK). GFSK is the recommended modulation type as it provides the best performance and cleanest modulation spectrum. Figure 8 demonstrates the difference between FSK and GFSK for a Data Rate of 64 kbps. The time domain plots demonstrate the effects of the Gaussian filtering. The frequency omain plots demonstrate the spectral benefit of GFSK over FSK. The type of modulation is selected with the modtyp[1:0] bits in "Register 71h. Modulation Mode Control 2". Note that it is also possible to obtain an unmodulated carrier signal by setting modtyp[1:0] = 00. modtyp[1:0] Modulation Source 00 Unmodulated Carrier 01 OOK 10 FSK 11 GFSK (enable TX Data CLK when direct mode is used) Figure 8. FSK vs GFSK Spectrums 23 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 4.2. Modulation Data Source The RFM42/43 may be configured to obtain its modulation data from one of three different sources: FIFO mode, Direct Mode, and from a PN9 mode. Furthermore, in Direct Mode, the TX modulation data may be obtained from several different input pins. These options are set through the dtmod[1:0] field in "Register 71h. Modulation Mode Control 2". Add R/W 71 R/W Function/Descr iption Modulation Mode Control 2 D7 D6 trclk[1] trclk[0] D5 D4 dtmod dtmod [1] [0] D3 D2 D1 D0 eninv fd[8] modtyp[1] modtyp[0] POR Def. 23h modtyp[1:0] Modulation Source 00 Direct Mode using TX_Data via GPIO pin (GPIO needs programming accordingly also) 01 Direct Mode using TX_Data via SDI pin (only when nSEL is high) 10 FIFO Mode 11 PN9 (internally generated) 4.3. FIFO Mode In FIFO mode, the integrated FIFO is used to transmit the data. The FIFO is accessed via "Register 7Fh. FIFO Access" with burst write capability. The FIFO may be configured specific to the application packet size, etc. (see "6. Data Handling and Packet Handler" for further information). When in FIFO mode the module will automatically exit the TX State when the ipksent interrupt occurs. The module will return to any of the other states based on the settings in "Register 07h. Operating Mode and Function Control 1". For instance, if both the txon and pllon bits are set, the module will transmit all of the contents of the FIFO and the ipksent interrupt will occur. When this event occurs the module will clear the txon bit and return to pllon or Tune Mode. If no other bits are set in register 07h besides txon initially then the module will return to the Idle state. 4.4. Direct Mode For legacy systems that have packet handling within an MCU or other baseband module, it may not be desirable to use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely. In Direct Mode, the TX modulation data is applied to an input pin of the module and processed in ―real time‖ (i.e., not stored in a register for transmission at a later time). There are various configurations for choosing which pin is used for the TX Data. Furthermore, an additional input pin is required for the TX Data Clock if GFSK modulation is desired (only the TX Data input pin is required for FSK). Two options for the source of the TX Data are available in the dtmod[1:0] field, and various configurations for the source of the TX Data Clock may be selected through the trclk[1:0] field. trclk[1:0] TX Data Clock Configuration 00 No TX Clock (only for FSK) 01 TX Data Clock is available via GPIO (GPIO needs programming accordingly as well) 10 TX Data Clock is available via SDO pin (only when nSEL is high) 11 TX Data Clock is available via the nIRQ pin The eninv bit in Address 71h will invert the TX Data for testing purposes. 24 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 4.5. PN9 Mode In this mode the TX Data is generated internally using a pseudorandom (PN9 sequence) bit generator. The primary purpose of this mode is for use as a test mode to observe the modulated spectrum without having to load/provide data. 4.6. Synchronous vs. Asynchronous In Asynchronous mode no clock is used to synchronize the data to the internal modulator. This mode can only be used with FSK. The advantage of this mode that it saves a microcontroller pin because no data clock is required. The disadvantage is that you don‘t get the clean spectrum and limited BW of GFSK. If Asynchronous FSK is used the TX_DR register should be set to its maximum value. 25 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 5. Internal Functional Blocks This section provides an overview some of the key blocks of the internal radio architecture. 5.1. Synthesizer An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–930 MHz is rovided on-chip. Using a ΣΔ synthesizer has many advantages; it provides large amounts of flexibility in choosing data rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the loop in the digital domain through the fractional divider which results in very precise accuracy and control over the transmit deviation. The PLL and Δ-Σ modulator scheme is designed to support any desired frequency and channel spacing in the range from 240–930 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz (High band). The transmit data rate can be programmed between 1–128 kbps, and the frequency deviation can be programmed between ±1–160 kHz. These parameters may be adjusted via registers as shown in "3.6. Frequency Control". Figure 9. PLL Synthesizer Block Diagram The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-chip spiral inductors. The output of the VCO is followed by a configurable divider which will divide down the signal to the desired output frequency band. The modulus of this divider stage is controlled dynamically by the output from the Δ-Σ modulator. The tuning resolution of the Δ-Σ modulator is determined largely by the over-sampling rate and the number of bits carried internally. The tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of 312.5 Hz anywhere in the range between 240–930 MHz. 5.1.1. VCO The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and fb[4:0] fields in "Register 75h. Frequency Band Select". A 2X VCO is utilized to help avoid problems due to frequency pulling, especially when turning on the integrated Power Amplifier. In receive mode, the LO frequency is automatically shifted downwards (without reprogramming) by the IF frequency of 937.5 kHz, allowing transmit operation on the same frequency. The VCO integrates the resonator inductor, tuning varactor, so no external VCO components are required. The VCO uses capacitance bank to cover the wide frequency range specified. The capacitance bank will automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this might not be desirable so the VCO calibration may be skipped by setting the appropriate register. 26 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 5.2. Power Amplifier The RFM42 contains an internal integrated power amplifier (PA) capable of transmitting at output levels between +8 to +17 dBm. The output power is programmable in 3 dB steps through the txpow[2:0] field in "Register 6Dh. TX Power". The RFM43 contains a PA which is capable of transmitting output levels between –8 to +13 dBm. 5.2.1. Output Power Selection With the RFM42, the output power is configurable in 3 dB steps from +8 to +17 dBm with the txpow[2:0] field in "Register 6Dh. TX Power". The PA output is ramped up and down to prevent unwanted spectral splatter.The higher power setting of the module achieves maximum possible range, but of course comes at the cost of higher TX current consumption. However, depending on the duty cycle of the system, the effect on battery life may be insignificant. Contact HopeRF Support for help in evaluating this tradeoff. The +13 dBm output power of the RFM43 is targeted at systems that require lower output power. The PA still offers high efficency and a range of output power from –8 to +13 dBm. Add R/W Function/Description 6D R/W TX Power D7 D6 D5 D4 D3 D2 D1 D0 POR Def. txpow[2] txpow[1] txpow[0] 07h txpow[1:0] RFM42 Output Power 00 +8 dBm 01 +11 dBm 10 +14 dBm 11 +17 dBm txpow[2:0] RFM43 Output Power 000 –8 dBm 001 –5 dBm 010 –2 dBm 011 +1 dBm 100 +4 dBm 101 +7 dBm 110 +10 dBm 111 +13 dBm 27 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 5.3. Crystal Oscillator For RF42/RF43 IC The RF42/43 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 μs when a suitable parallel resonant crystal is used. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. By default, all that is required off-chip is the 30 MHz crystal blank. The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance requirements and to slightly adjust the frequency of the crystal oscillator. The tuning of the crystal load capacitance is programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Oscillator Load Capacitance". The total internal capacitance is 12.5 pF and is adjustable in approximately 127 steps (97fF/step). The xtalshift bit is a course shift in frequency but is not binary with xlc[6:0]. The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance requirements and to slightly adjust the frequency of the crystal oscillator. This latter function can be used to compensate for crystal production tolerances. Utilizing the on-chip temperature sensor and suitable control software even the temperature dependency of the crystal can be canceled. The crystal load capacitance is programmed using register 09h. The typical value of the total on-chip (internal) capacitance Cint can be calculated as follows: Cint = 1.8 pF + 0.085 pF x xlc[6:0] + 3.7 pF x xtalshift Note that the course shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by the crystal can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If the maximum value of Cint (16.3 pF) is not sufficient, an external capacitor can be added for exact tuning. See more on this, calculating Cext and crystal selection guidelines in "10. Application Notes" . If AFC is disabled then the synthesizer frequency may be further adjusted by programming the Frequency Offset field fo[9:0]in "Register 73h. Frequency Offset 1" and "Register 74h. Frequency Offset 2", as discussed in "3.6. Frequency Control". The crystal oscillator frequency is divided down internally and may be output to the microcontroller through one of the GPIO pins for use as the System Clock. In this fashion, only one crystal oscillator is required for the entire system and the BOM cost is reduced. The available clock frequencies (i.e., internal division ratios) and the GPIO configuration are discussed further in "7.2. Microcontroller Clock". Add R/W 09 R/W Function/Descripti on Crystal Oscillator Load Capacitance D7 D6 D5 D4 D3 D2 D1 D0 xtalshift xlc[6] xlc[5] xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] POR Def. 40h 5.4. Regulators There are a total of six regulators integrated onto the RFM42/43. With the exception of the IF and Digital all regulators are designed to operate with only internal decoupling. The IF and Digital regulators both require an external 1 μF decoupling capacitor. All of the regulators are designed to operate with an input supply voltage from +1.8 to +3.6 V, and produce a nominal regulated output voltage of +1.7 V ±5%. The internal circuitry nominally operates from this regulated +1.7 V supply. The output stage of the of PA is not connected internally to a regulator and is connected directly to the battery voltage. A supply voltage should only be connected to the VDD pins. No voltage should be forced on the IF or DIG regulator outputs. 28 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 6. Data Handling and Packet Handler 6.1. TX FIFO A 64 byte FIFO is integrated into the module for TX, as shown in Figure 10. "Register 7Fh. FIFO Access" is used to access the FIFO. A burst write, as described in "3.1. Serial Peripheral Interface (SPI)", to address 7Fh will write data to the TX FIFO. Figure 10. FIFO Threshold The TX FIFO has two programmable thresholds. An interrupt event occurs when the data in the TX FIFO reaches these thresholds. The first threshold is the FIFO Almost Full threshold, txafthr[5:0]. The value in this register corresponds to the desired threshold value in number of bytes. When the data being filled into the TX FIFO reaches this threshold limit, an interrupt to the microcontroller is generated so the module can enter TX mode to transmit the contents of the TX FIFO. The second threshold for TX is the FIFO Almost Empty Threshold, txaethr[5:0]. When the data being shifted out of the TX FIFO reaches the Almost Empty threshold an interrupt will be generated. The microcontroller will need to switch out of TX mode or fill more data into the TX FIFO. The Transmitter may be configured so that when the TX FIFO is empty the chip will automatically move to the Ready state. In this mode the TX FIFO Almost Empty Threshold may not be useful. This functionality is set by the ffidle bit in ―Register 08h. Operating Mode and Function Control 2,‖. 29 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Add R/W 08 R/W 7C R/W 7D R/W Function/Descri D7 D6 D5 D4 Reser Reser Reserve Reserve ved ved d d TX FIFO Control 1 txafthr[5] txafthr[4] txafthr[3] txafthr[2] TX FIFO Control 2 txafthr[5] txafthr[4] txafthr[3] txafthr[2] ption Operating &Function Control 2 D3 autotx D2 D1 Reserve Reserved D0 POR Def. ffclrtx 00h txafthr[1] txafthr[0] 37h txafthr[1] txafthr[0] 04h d The TX FIFO may be cleared or reset with the ffclrtx bit in ―Register 08h. Operating Mode and Function Control 2,‖. All interrupts may be enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and ―Register 06h. Interrupt Enable 2,‖. If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin but the bits will still be read correctly in the Interrupt Status registers. 6.2. Packet Configuration When using the FIFO, automatic packet handling may be enabled for the TX mode. "Register 30h. Data Access Control" through ―Register 3Eh. Packet Length,‖ control the configuration for Packet Handling. The usual fields for network communication (such as preamble, synchronization word, headers, packet length, and CRC) can be configured to be automatically added to the data payload. The fields needed for packet generation normally change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload greatly reduces the amount of communication between the microcontroller and the RFM42/43 and therefore also reduces the required computational power of the microcontroller. The general packet structure is shown in Figure 11. The length of each field is shown below the field. The preamble pattern is always a series of alternating ones and zeroes, starting with a one. All the fields have programmable lengths to accommodate different applications. The most common CRC polynominals are available for selection. Figure 11. Packet Structure An overview of the packet handler configuration registers is shown in Table 12. A complete register description can be found in ―11.1. Complete Register Table and Descriptions‖. 6.3. Packet Handler TX Mode If the TX packet length is set the packet handler will send the number of bytes in the packet length field before returning to ready mode and asserting the packet sent interrupt. To resume sending data from the FIFO the microcontroller needs to command the module to re-enter TX mode Figure 12 provides an example transaction where the packet length is set to three bytes. 30 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 31 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 6.4. Data Whitening, Manchester Encoding, and CRC Data whitening can be used to avoid extended sequences of 0s or 1s in the transmitted data stream to achieve a more uniform spectrum. When enabled, the payload data bits are XORed with a pseudorandom sequence output from the built-in PN9 generator. The generator is initialized at the beginning of the payload. The receiver recovers the original data by repeating this operation. Manchester encoding can be used to ensure a dc-free transmission and good synchronization properties. When Manchester encoding is used, the effective datarate is unchanged but the actual datarate (preamble length, etc.) is doubled due to the nature of the encoding. The effective datarate when using Manchester encoding is limited to 64 kbps. Data Whitening and Manchester encoding can be selected with "Register 70h. Modulation Mode Control 1". The CRC is configured via "Register 30h. Data Access Control". 6.5. TX Retransmission and Auto TX The RFM42/43 is capable of automatically retransmitting the last packet in the FIFO if no additional packets were loaded into the TX FIFO. Automatic Retransmission is achieved by entering the TX state with the txon bit set. This feature is useful for Beacon transmission or when retransmission is required due to the absence of a valid acknowledgement. Only packets that fit completely in the TX FIFO are valid for retransmit. When it is necessary to transmit longer packets, the TX FIFO uses the circular read/write capability. An Automatic Transmission is also available. When autotx = 1 the transceiver will enter automatically TX State when the TX FIFO is almost full. When the TX FIFO is empty the transceiver will automatically return to the IDLE State. Add R/W 08 R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 autotx Reserved Reserved ffclrtx POR Def. Operating &Function Reserved 00h Control 2 32 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 7. Auxiliary Functions 7.1. Smart Reset The RFM42/43 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce reliable reset signal in any circumstances. Reset will be initiated if any of the following conditions occur: ■ Initial power on, when VDD starts from 0V: reset is active till VDD reaches VRR (see table); ■ When VDD decreases below VLD for any reason: reset is active till VDD reaches VRR again; ■ A software reset via ―Register 08h. Operating Mode and Function Control 2,‖: reset is active for time TSWRST ■ On the rising edge of a VDD glitch when the supply voltage exceeds the following time functioned limit: The reset will initialize all registers to their default values. The reset signal is also available for output and use by the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by default on GPIO_1. 33 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 7.2. Microcontroller Clock The crystal oscillator frequency is divided down internally and may be output to the microcontroller through GPIO2. This feature is useful to lower BOM cost by using only one crystal in the system. The system clock frequency is selectable from one of 8 options, as shown below. Except for the 32.768 kHz option, all other frequencies are derived by dividing the Crystal Oscillator frequency. The 32.768 kHz clock signal is derived from an internal RC Oscillator or an external 32 kHz Crystal, depending on which is selected. The GPIO2 default is the microcontroller clock with a 1 MHz microcontroller clock output. Add R/W A0 R/W Function/Descript D7 ion D6 Microcontroller D5 clkt[1] Output Clock D4 D3 D2 D1 D0 clkt[0] enlfc mclk[2] mclk[1] mclk[0] mclk[2:0] Modulation Source 000 30 MHz 001 15 MHz 010 10 MHz 011 4 MHz 100 3 MHz 101 2 MHz 110 1 MHz 111 32.768 KHz POR Def. 00h If the microcontroller clock option is being used there may be the need of a System Clock for the microcontroller while the RFM42/43 is in SLEEP mode. Since the Crystal Oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called Enable Low Frequency Clock and is enabled by the enlfc bit. When enlfc = 1 and the module is in SLEEP mode then the 32.768 kHz clock will be provided to the microcontroller as the System Clock, regardless of the setting of mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin to the microcontroller as the System Clock in all IDLE or TX states. When the module is commanded to SLEEP mode, the System Clock will become 32.768 kHz. Another available feature for the microcontroller clock is the Clock Tail, clkt[1:0]. If the Enable Low Frequency Clock feature is not enabled (enlfc = 0), then the System Clock to the microcontroller is disabled in SLEEP mode. However, it may be useful to provide a few extra cycles for the microcontroller to complete its operation prior to the shutdown of the System Clock signal. Setting the clkt[1:0] field will provide additional cycles of the System Clock before it shuts off. clkt[1:0] Modulation Source 00 0 cycles 01 128 cycles 10 256 cycles 11 512 cycles If an interrupt is triggered, the microcontroller clock will remain enabled regardless of the selected mode. As soon as the interrupt is read the state machine will then move to the selected mode. For instance, if the module is commanded to Sleep mode but an interrupt has occurred the 30 MHz XTAL will not disable until the interrupt has been cleared. 34 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 7.3. General Purpose ADC An 8-bit SAR ADC is integrated onto the module for general purpose use, as well as for digitizing the temperature sensor reading. ―Register 0Fh. ADC Configuration,‖ must be configured depending on the use of the GP ADC before use. The architecture of the ADC is demonstrated in Figure 15. First the input of the ADC must be selected by setting the ADCSEL[2:0] depending on the use of the ADC. For instance, if the ADC is going to be used to read out the internal temperature sensor, then ADCSEL[2:0] should be set to 000. Next, the input reference voltage to the ADC must be chosen. By default, the ADC uses the bandgap voltage as a reference so the input range of the ADC is from 0–1.02 V with an LSB resolution of 4 mV (1.02/255). Changing the ADC reference will change the LSB resolution accordingly. Every time the ADC conversion is desired, the ADCStart bit in ―Register 0Fh. ADC Configuration,‖ must be set to 1. This is a self clearing bit that will be cleared at the end of the conversion cycle of the ADC. The conversion time for the ADC is 350 us. After the 350 us or when the ADCstart/busy bit is cleared, then the ADC value may be read out of "Register 11h. ADC Value". Setting the "Register 10h. ADC Sensor Amplifier Offset", ADC Sensor Amplifier Offset is only necessary when the ADC is configured to used as a Bridge Sensor as described in the following section. 35 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 7.3.1. ADC Differential Input Mode—Bridge Sensor Example The differential input mode of ADC8 is designed to directly interface any bridge-type sensor, which is demonstrated in the figure below. As seen in the figure the use of the ADC in this configuration will utilize two GPIO pins. The supply source of the bridge and module should be the same to eliminate the measuring error caused by battery discharging. For proper operation one of the VDD dependent references (VDD/2 or VDD/3) should be selected for the reference voltage of ADC8. VDD/2 reference should be selected for VDD lower than 2.7 V, VDD/3 reference should be selected for VDD higher than 2.7 V. The differential input mode supports programmable gain to match the input range of ADC8 to the characteristic of the sensor and VDD proportional programmable offset adjustment to compensate the offset of the sensor. Figure 16. ADC Differential Input Example—Bridge Sensor The adcgain[1:0] bits in "Register 0Eh. I/O Port Configuration" determine the gain of the differential/single ended amplifier. This is used to fit the input range of the ADC8 to bridge sensors having different sensitivity: adcgain[1] adcgain[0] Differential Gain Input Range (% of VDD) adcref[0] = 0 adcref[0] = 1 0 0 22/13 33/13 16.7 0 1 44/13 66/13 8.4 1 0 66/13 99/13 5.6 1 1 88/13 132/13 4.2 Note: The input range is the differential voltage measured between the selected GPIO pins corresponding to the full ADC range (255). The gain is different for different VDD dependent references so the reference change has no influence on input range and digital measured values. 36 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 The differential offset can be coarse compensated by the adcoffs[3:0] bits found in "Register 11h. ADC Value". Fine compensation should be done by the microcontroller software. The main reason for the offset compensation is to shift the negative offset voltage of the bridge sensor to the positive differential voltage range. This is essential as the differential input mode is unipolar. The offset compensation is VDD proportional, so the VDD change has no influence on the measured value. 37 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 7.4. Temperature Sensor An analog temperature sensor is integrated into the module. The temperature sensor will be automatically enabled when the temperature sensor is selected as the input of the ADC or when the analog temp voltage is selected on the analog test bus. The temperature sensor value may be digitized using the general-purpose ADC and read out over the SPI through "Register 10h. ADC Sensor Amplifier Offset". The range of the temperature sensor is selectable to configure to the desired application and performance. The table below demonstrates the settings for the different temperature ranges and performance. To use the Temp Sensor: 1. Set input for ADC to be Temperature Sensor, "Register 0Fh. ADC Configuration"—adcsel[2:0] = 000 2. Set Reference for ADC, "Register 0Fh. ADC Configuration"—adcref[1:0] = 00 3. Set Temperature Range for ADC, "Register 12h. Temperature Sensor Calibration"—tsrange[1:0] 4. Set entsoffs = 1, "Register 12h. Temperature Sensor Calibration" 5. Trigger ADC Reading, "Register 0Fh. ADC Configuration"—adcstart = 1 6. Read-out Value—Read Address in "Register 11h. ADC Value" Add R/W 12 R/W 13 R/W Function/Descr iption POR D7 D6 D5 D4 D3 D2 D1 D0 tsrange[1] tsrange[0] entsoffs entstrim vbgtrim[3] vbgtrim[2] vbgtrim[2] vbgtrim[2] 20h tvoffs[7] tvoffs[7] tvoffs[7] tvoffs[7] tvoffs[7] tvoffs[7] tvoffs[7] tvoffs[7] 00h Temperature Def. Sensor Control Temperature Value Offset Table 14. Temperature Sensor Range entoff tsrange[1] tsrange[0] Temp. range Unit Slope ADC8 LSB 1 0 0 –64 … 64 °C °C 8 mV/°C 0.5 °C 1 0 1 –64 … 192 °C 4 mV/°C 1 °C 1 1 0 0 … 128 °C 8 mV/°C 0.5 °C 1 1 1 –40 … 216 °F 4 mV/°F 1 °F 0* 1 0 0 … 341 °K 3 mV/°K 1.333 °K *Note: Absolute temperature mode, no temperature shift. This mode is only for test purposes. POR value of EN_TOFF is 1. Control to adjust the temperature sensor accuracy is available by adjusting the bandgap voltage. By enabling the envbgcal and using the vbgcal[3:0] bits to trim the bandgap the temperature sensor accuracy may be fine tuned in the final application. The slope of the temperature sensor is very linear and monotonic but the exact accuracy or offset in temperature is difficult to control better than ±10 °C. With the vbgtrim or bandgap trim though the initial temperature offset can be easily adjusted and be better than ±3 °C. The different ranges for the temperature sensor and ADC8 are demonstrated in Figure 18. The value of the ADC8 may be translated to a temperature reading by ADC8Value x ADC8 LSB + Lowest Temperature in Temp Range. For instance for a tsrange = 00, Temp = ADC8Value x 0.5 – 64. 38 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Figure 18. Temperature Ranges using ADC8 39 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 7.5. Low Battery Detector A low battery detector (LBD) with digital read-out is integrated into the function is enabled by setting. A digital threshold may be programmed into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold". When the digitized battery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller. The microcontroller will then need to verify the interrupt by reading "Register 03h. Interrupt/Status 1" and ―Register 04h. Interrupt/Status 2,‖. If the LBD is enabled while the module is in SLEEP mode, it will automatically enable the RC oscillator which will periodically turn on the LBD circuit to measure the battery voltage. The battery voltage may also be read out through "Register 1Bh. Battery Voltage Level" at any time when the LBD is enabled. The Low Battery Detect function is enabled by setting enlbd=1 in "Register 07h. Operating Mode and Function Control 1". Ad R/W 1A R/W 1B R Function/Descri ption D7 D6 D5 Low Battery Detector Threshold Battery Voltage Level 0 0 0 POR D4 D3 D2 D1 D0 lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] — Def. The LBD output is digitized by a 5-bit ADC. When the LBD function is enabled, enlbd = 1 in "Register 07h. Operating Mode and Function Control 1", the battery voltage may be read at anytime by reading "Register 1Bh. Battery Voltage Level". A Battery Voltage Threshold may be programmed to register 1Ah. When the battery voltage level drops below the battery voltage threshold an interrupt will be generated on nIRQ pin to the microcontroller if the LBD interrupt is enabled in ―Register 06h. Interrupt Enable 2,‖. The microcontroller will then need to verify the interrupt by reading the interrupt status register, Addresses 03 and 04H. The LSB step size for the LBD ADC is 50 mV, with the ADC range demonstrated in the table below. If the LBD is enabled the LBD and ADC will automatically be enabled every 1 s for approximately 250 μs to measure the voltage which minimizes the current consumption in Sensor mode. Before an interrupt is activated four consecutive readings are required. BatteryVoltageV =1.7+50mV X ADCValue ADC Value VDD Voltage [V] 0 < 1.7 1 1.7–1.75 2 1.75–1.8 …… …… 29 3.1–3.15 30 3.15–3.2 31 >3.2 40 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 7.6. Wake-Up Timer The module contains an integrated wake-up timer which periodically wakes the module from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP mode, the wake-up timer will count for a time specified by the Wake-Up Timer Period in Registers 10h–12h. At the expiration of this period an interrupt will be generated on the nIRQ pin if this interrupt is enabled. The microcontroller will then need to verify the interrupt by reading the Interrupt Status Registers 03h–04h. The wake-up timer value may be read at any time by the wtv[15:0] read only registers 13h–14h. The formula for calculating the Wake-Up Period is the following: WUT = 32 X M X 2 32.768 R -D ms WUT Register Description wtr[3:0] R Value in Formula wtd[1:0] D Value in Formula wtm[15:0] M Value in Formula Use of the D variable in the formula is only necessary if finer resolution is required than the R value gives. Ad 14 15 16 R/W R/W Function/Descri ption D7 D6 D4 D3 D2 D1 D0 wtr[3] wtr[2] wtr[1] wtr[0] wtd[1] wtd[0] 00h wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 00h wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9] wtv[8] — wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] — Wake-Up Timer Period 1 R/W R/W 17 R 18 R Wake-Up Timer wtm Period 2 [15] Wake-Up Timer wtm Period 3 [7] Low Battery wtv[ Detector Threshold 15] Battery Voltage wtv[ Level 7] POR D5 Def. There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is enabled in ―Register 06h. Interrupt Enable 2,‖. If the WUT interrupt is enabled then nIRQ pin will go low when the timer expires. The module will also change state so that the 30 M XTAL is enabled so that the microcontroller clock output is available for the microcontroller to use process the interrupt. The other method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation the module will not change state until commanded by the microcontroller. The two different modes of operation of the WUT are demonstrated in Figure 19. A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in 07h, GPIO0 is automatically reconfigured so that an external 32 kHz XTAL may be connected to this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so only the XTAL should be connected to this pin and the XTAL should be physically located as close to the pin as possible. Once the x32 ksel bit is set, all internal functions such as WUT, micro-controller clock, and LDC mode will use the 32 K XTAL and not the 32 kHz RC oscillator. 41 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Interrupt Enable enwut=1 (Reg 06h) Figure 19. WUT Interrupt and WUT Operation 42 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 7.7. GPIO Configuration Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW control, Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low. Note: The ADC should not be selected as an input to the GPIO in Standby or Sleep Modes and will cause excess current consumption. Add 0B R/W R/W Function/D D7 D6 GPIO0 gpio0 gpio0dr Configuration drv[1] v[1] GPIO1 Gpio1 Configuration drv[1] GPIO2 Gpio2 Configuration drv[1] escription R/W 0C R/W 0D 0E R/W I/O Port D5 wt gpio1dr D3 D2 D1 D0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] Pup1 POR Def. 00h 00h v[1] w gpio2[4] gpio2dr gpio2[3] gpio2[2] gpio2[1] gpio2[0] Pup2 00h v[1] extitst[2] Configuration pup0 D4 extitst[ extitst[0] itsdo dio2 dio1 dio0 1] 00h The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000 default setting. The default settings for each GPIO are listed below: GPIO 00000—Default Setting GPIO0 POR GPIO1 POR Inverted GPIO2 Microcontroller Clock The module is configured to provide the System Clock output to the microcontroller so that only one crystal is needed in the system, therefore reducing the BOM cost. For the TX Data Source, Direct Mode is used because long packets are desired with a unique packet handling format already implemented in the microcontroller. In this configuration the TX Data Clock is configured onto GPIO0, the TX Data is configured onto GPIO1, and the Microcontroller System Clock output is configured onto GPIO2. For a complete list of the available GPIO's see ―Register 0Ch. GPIO Configuration 1,‖, ―Register 0Dh. GPIO Configuration 2,‖, and ―Register 0Eh. I/O Port Configuration,‖. 43 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 8. Reference Design RFM42 Reference Design Schematic RFM43 Reference Design Schematic 44 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 9. Measurement Results RF42 Figure 24. TX Modulation (40 kbps, 20 kHz Deviation) Figure 25. RFM43 TX Unmodulated Spectrum (917 MHz) 45 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Figure 26. RFM43 TX Modulated Spectrum (917 MHz, 40 kbps, 20 kHz Deviation, GFSK) RF42 Figure 27. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz 46 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Figure 28. Synthesizer Phase Noise (VCOCURR = 11) 47 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 10. Reference Material 10.1. Complete Register Table and Descriptions Table 17. Register Descriptions 48 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Table 17. Register Descriptions (Continued) 49 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 00h. Device Type Code (DT) Bit D7 D6 Name D5 D4 D3 Reserved Type D2 D1 D0 D1 D0 dt[4:0] R R Reset value = 00000111 Bit Name Function 7:5 Reserved 4:0 dt[4:0] Reserved. Device Type Code. Register 01h. Version Code (VC) Bit D7 D6 Name D5 D4 D3 vc[4:0] Reserved Type D2 R R Reset value = xxxxxxxx Bit Name Function 7:5 Reserved Reserved. Version Code. 4:0 vc[4:0] Code indicating the version of the module. Rev A0: 00100 Rev V2: 00011 50 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 02h. Device Status Bit D7 Name Type ffovfl D6 ffunfl R D5 Reserved R D4 D3 Reserved R Reserved R D2 D1 Reserved R R cps[1:0] D0 ffovfl R R Reset value = xxxxxxxx Bit Name Function 7 ffovfl TX 6 ffunfl TX 5:4 Reserved Reserved. 3:2 Reserved Reserved. 1:0 cps[1:0] Module Power State. 00: Idle State 10: TX State 51 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 03h. Interrupt/Status 1 Bit D7 Name Type D6 ifferr itxffafull R D5 ixtffaem R D4 D3 Reserved R iext R D2 D1 ipksent R Reserved R D0 Reserved R R Reset value = xxxxxxxx Bit Name 7 ifferr Function FIFO Underflow/Overflow Error. When set to 1 the TX FIFO has overflowed or underflowed. TX FIFO Almost Full. 6 itxffafull When set to 1 the TX FIFO has met its almost full threshold and needs to be transmitted. 5 itxffaem 4 Reserved TX FIFO Almost Empty. When set to 1 the TX FIFO is almost empty and needs to be filled. Reserved. External Interrupt. 3 iext When set to 1 an interrupt occurred on one of the GPIO‘s if it is programmed so. The status can be checked in register 0Eh. See GPIOx Configuration section for the details. 2 ipksent 1:0 Reserved Packet Sent Interrupt. When set to1 a valid packet has been transmitted. Reserved. When any of the Interrupt/Status 1 bits change state from 0 to 1 the device will notify the microcontroller by setting the nIRQ pin LOW if it is enabled in the Interrupt Enable 1 register. The nIRQ pin will go to HIGH and all the enabled interrupt bits will be cleared when the microcontroller reads this address. If any of these bits is not enabled in the Interrupt Enable 1 register then it becomes a status signal that can be read anytime in the same location and will not be cleared by reading the register. 52 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Table 18. Interrupt or Status 1 Bit Set/Clear Description Bit 7 Status Set/Clear Conditions Name ifferr Set if there is a FIFO overflow or underflow. Cleared by applying FIFO reset. Set when the number of bytes written to TX FIFO is greater than the Almost Full 6 itxffafull threshold. Automatically cleared at the start of transmission when the number of bytes in the FIFO is less than or equal to the threshold. Set when the number of bytes in the TX FIFO is less than or equal to the Almost 5 itxffaem Empty threshold. Automatically cleared when the number of data bytes in the TX FIFO is above the Almost Empty threshold. 4 Reserved 3 iext 2 ipksent 1:0 Reserved Reserved. External interrupt source. Set once a packet is successfully sent (no TX abort). Cleared upon leaving FIFO mode or at the start of a new transmission. Reserved. Table 19. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts? Bit 7 Status Set/Clear Conditions Name ifferr Set if there is a FIFO Overflow or Underflow. It is cleared only by applying FIFO reset to the specific FIFO that caused the condition. Will be set when the number of bytes written to TX FIFO is greater than the 6 itxffafull Almost Full threshold set by SPI. It is automatically cleared when we start transmitting and the FIFO data is read out and the number of bytes left in the FIFO is smaller or equal to the threshold). Will be set when the number of bytes (not yet transmitted) in TX FIFO is smaller 5 itxffaem or equal than the Almost Empty threshold set by SPI. It is automatically cleared when we write enough data to TX FIFO so that the number of data bytes not yet transmitted is above the Almost Empty threshold. 4 Reserved 3 iext Reserved. External interrupt source. Will go high once a packet is sent all the way through (no TX abort). This status 2 ipksent will be cleaned if 1) We leave FIFO mode or 2) In FIFO mode we start a new transmission. 1:0 Reserved Reserved. 53 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 04h. Interrupt/Status 2 Bit D7 D6 Name D5 D4 Reserved Type R D3 D2 D1 D0 iwut ilbd ichiprdy ipor R R R R Reset value = xxxxxxxx Bit Name 7：4 Reserved 3 iwut Function Reserved. Wake-Up-Timer. On the expiration of programmed wake-up timer this bit will be set to 1. Low Battery Detect. 2 ilbd When a low battery event is been detected this bit will be set to 1. This interrupt event is saved even if it is not enabled by the mask register bit and causes an interrupt after it is enabled. 1 ichiprdy Module Ready (XTAL). When a module ready event has been detected this bit will be set to 1. Power-on-Reset (POR). 0 ipor When the module detects a Power on Reset above the desired setting this bit will be set to 1. When any of the Interrupt/Status Register 2 bits change state from 0 to 1 the control block will notify the microcontroller by setting the nIRQ pin LOW if it is enabled in the Interrupt Enable 2 register. The nIRQ pin will go to HIGH and all the enabled interrupt bits will be cleared when the microcontroller reads this address. If any of these bits is not enabled in the Interrupt Enable 2 register then it becomes a status signal that can be read anytime in the same location and will not be cleared by reading the register. 54 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Table 20. Interrupt or Status 2 Bit Set/Clear Description Bit Name 7：4 Reserved 3 iwut Set/Clear Conditions Reserved. Wake time timer interrupt. Use as an interrupt, not as a status. Low Battery Detect. When a low battery event is been detected this bit will be 2 ilbd set to 1. This interrupt event is saved even if it is not enabled by the mask register bit and causes an interrupt after it is enabled. Probably the status is cleared once the battery is replaced. 1 ichiprdy 0 ipor Module ready goes high once we enable the xtal, TX and a settling time for the Xtal clock elapses. The status stay high unless we go back to Idle mode. Power on status. Table 21. Detailed Description of Status Registers when not Enabled as Interrupts Bit Name 7：4 Reserved 3 iwut Set/Clear Conditions Reserved. Wake time timer interrupt. Use as an interrupt, not as a status. Low Battery Detect. When a low battery event is been detected this bit will be 2 ilbd set to 1. This interrupt event is saved even if it is not enabled by the mask register bit and causes an interrupt after it is enabled. Probably the status is cleared once the battery is replaced. 1 ichiprdy 0 ipor Module ready goes high once we enable the xtal, TX and a settling time for the Xtal clock elapses. The status stay high unless we go back to Idle mode. Power on status. 55 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 05h. Interrupt Enable 1 Bit D7 Name enfferr Type R/w D6 D5 entxffafull entxffaem R/w R/w D4 D3 Reserved enext R/w D2 D1 enpksent R/w R/w Reserved D0 Reserved R/w R/w Reset value = 00000000 Bit Name 7 enfferr 6 entxffafull 5 entxffaem 4 Reserved 3 enext 2 enpksent 1:0 Reserved Function Enable FIFO Underflow/Overflow. When set to 1 the FIFO Underflow/Overflow interrupt will be enabled. Enable TX FIFO Almost Full. When set to 1 the TX FIFO Almost Full interrupt will be enabled. Enable TX FIFO Almost Empty. When set to 1 the TX FIFO Almost Empty interrupt will be enabled. Reserved. Enable External Interrupt. When set to 1 the External Interrupt will be enabled. Enable Packet Sent. When ipksent =1 the Packet Sense Interrupt will be enabled. Reserved. 56 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 06h. Interrupt Enable 2 Bit D7 D6 D5 Name Reserved Type R D4 D3 enwut D2 enlbd R/ w R/w D1 enchiprdy R/w D0 enpor R/w Reset value = 00000011 Bit Name 7:4 Reserved 3 enwut 2 enlbd 1 enchiprdy 0 enpor Function Reserved. Enable Wake-Up Timer. When set to 1 the Wake-Up Timer interrupt will be enabled. Enable Low Battery Detect. When set to 1 the Low Battery Detect interrupt will be enabled. Enable Module Ready (XTAL). When set to 1 the Module Ready interrupt will be enabled. Enable POR. When set to 1 the POR interrupt will be enabled. 57 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 07h. Operating Mode and Function Control 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name swres enlbd enwt x32ksel txon Reserved pllon xton Type R/w R/w R/w R/w R/w R/w R/w R/w Reset value = 00000001 Bit Name Function Software Register Reset Bit. 7 swres This bit may be used to reset all registers simultaneously to a DEFAULT state, without the need for sequentially writing to each individual register. The RESET is accomplished by setting swres = 1. This bit will be automatically cleared. Enable Low Battery Detect. 6 enlbd When this bit is set to 1 the Low Battery Detector circuit and threshold comparison will be enabled. Enable Wake-Up-Timer. 5 enwt Enabled when enwt = 1. If the Wake-up-Timer function is enabled it will operate in any mode and notify the microcontroller through the GPIO interrupt when the timer expires. 32,768 kHz Crystal Oscillator Select. 4 x32ksel 0: RC oscillator 1: 32 kHz crystal TX on in Manual Transmit Mode. Automatically cleared in FIFO mode once the packet is sent. Transmission can be 3 txon aborted during packet transmission, however, when no data has been sent yet, transmission can only be aborted after the device is programmed to ―unmodulated carrier‖ ("Register 71h. Modulation Mode Control 2"). 2 Reserved Reserved. TUNE Mode (PLL is ON). 1 pllon When pllon = 1 the PLL will remain enabled in Idle State. This will for faster turn-around time at the cost of increased current consumption in Idle State. 0 xton READY Mode (Xtal is ON). 58 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 08h. Operating Mode and Function Control 2 Bit D7 D6 Name D5 D4 D3 Reserved autotx R/w Type D2 D1 Reserved R/w R/w D0 ffclrtx R/w R/w Reset value = 00000000 Bit Name 7：4 Reserved Function Reserved. Automatic Transmission. 3 autotx When autotx = 1 the transceiver will enter automatically TX State when the FIFO is almost full. When the FIFO is empty it will automatically return to the Idle State. 2：1 Reserved Reserved. TX FIFO Reset/Clear. 0 ffclrtx This has to be a two writes operation: Setting ffclrtx =1 followed by ffclrtx = 0 will clear the contents of the TX FIFO. Register 09h. 30 MHz Crystal Oscillator Load Capacitance Bit D7 Name xtalshft Type R/w D6 D5 D4 D3 D2 D1 D0 xlc[6:0] R/w Reset value = 01111111 Bit Name Function Additional capacitance to course shift the frequency if xlc[6:0] is not sufficient. 7 xtalshft Not binary with xlc[6:0]. 6:0 xlc[6:0] Tuning Capacitance for the 30 MHz XTAL. 59 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 0Ah. Microcontroller Output Clock Bit D7 Name Type D6 D5 Reserved D4 D3 clkt[1:0] R/w R D2 D1 enlfc mclk[2:0] R/w R/w D0 Reset value = xx000110 Bit Name 7:6 Reserved Function Reserved. Clock Tail. If enlfc = 0 then it can be useful to provide a few extra cycles for the microcontroller to complete its operation. Setting the clkt[1:0] register will 5:4 clkt[1:0] provide the addition cycles of the clock before it shuts off. 00: 0 cycle 01: 128 cycles 10: 256 cycles 11: 512 cycles Enable Low Frequency Clock. When enlfc = 1 and the module is in Sleep mode then the 32.768 kHz clock will 3 enlfc be provided to the microcontroller no matter what the selection of mclk[2:0] is. For example if mclk[2:0] = ‗000‘, 30 MHz will be available through the GPIO to output to the microcontroller in all Idle or TX states. When the module is commanded to Sleep mode the 30 MHz clock will become 32.768 kHz. Microcontroller Clock. Different clock frequencies may be selected for configurable GPIO clock output. All clock frequencies are created by dividing the XTAL except for the 32 kHz clock which comes directly from the 32 kHz RC Oscillator. The mclk[2:0] setting is only valid when xton = 1 except the 111. 2:0 mclk[2:0] 000: 30 MHz 001: 15 MHz 010: 10 MHz 011: 4 MHz 100: 3 MHz 101: 2 MHz 110: 1 MHz 111: 32.768 kHz 60 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 0Bh. GPIO Configuration 0 Bit D7 Name Type D6 D5 gpiodrv0[1:0] R/w D4 D3 D2 D1 pup0 gpio0[4:0] R/w R/w D0 Reset value = 00000000 Bit Name 7:6 gpiodrv0[1:0] 5 pup0 Function GPIO Driving Capability Setting. Pullup Resistor Enable on GPIO0. When set to 1 the a 200 kresistor is connected internally between VDD and the pin if the GPIO is configured as a digital input. GPIO0 pin Function Select. 00000: Power-On-Reset (output) 00001: Wake-Up Timer: 1 when WUT has expired (output) 4:0 gpio0[4:0] 00010: Low Battery Detect: 1 when battery is below threshold setting (output) 00011: Direct Digital Input 00100: External Interrupt, falling edge (input) 00101: External Interrupt, rising edge (input) 00110: External Interrupt, state change (input) 00111: ADC Analog Input 01000: Reserved (Analog Test N Input) 01001: Reserved (Analog Test P Input) 01010: Direct Digital Output 01011: Reserved (Digital Test Output) 01100: Reserved (Analog Test N Output) 01101: Reserved (Analog Test P Output) 01110: Reference Voltage (output) 01111: TX Data CLK output to be used in conjunction with TX Data pin (output) 10000: TX Data input for direct modulation (input) 10001: External Retransmission Request (input) 10010: TX State (output) 10011: TX FIFO Almost Full (output) 10100: Reserved 10101: Reserved 10110: Reserved 10111: Reserved 11000: Reserved 11001: Reserved 11010: Reserved 11011: Reserved 11100: Reserved 11101: VDD else : GND 61 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 0Ch. GPIO Configuration 1 Bit D7 Name Type D6 D5 gpiodrv1[1:0] R/w D4 D3 D2 D1 pup1 Gpio1[4:0] R/w R/w D0 Reset value = 00000000 Bit Name 7:6 gpiodrv1[1:0] 5 Pup1 Function GPIO Driving Capability Setting. Pullup Resistor Enable on GPIO1. When set to 1 the a 200 kresistor is connected internally between VDD and the pin if the GPIO is configured as a digital input. GPIO1 pin Function Select. 00000: Inverted Power-On-Reset (output) 00001: Wake-Up Timer: 1 when WUT has expired (output) 4:0 gpio1[4:0] 00010: Low Battery Detect: 1 when battery is below threshold setting (output) 00011: Direct Digital Input 00100: External Interrupt, falling edge (input) 00101: External Interrupt, rising edge (input) 00110: External Interrupt, state change (input) 00111: ADC Analog Input 01000: Reserved (Analog Test N Input) 01001: Reserved (Analog Test P Input) 01010: Direct Digital Output 01011: Reserved (Digital Test Output) 01100: Reserved (Analog Test N Output) 01101: Reserved (Analog Test P Output) 01110: Reference Voltage (output) 01111: TX Data CLK output to be used in conjunction with TX Data pin (output) 10000: TX Data input for direct modulation (input) 10001: External Retransmission Request (input) 10010: TX State (output) 10011: TX FIFO Almost Full (output) 10100: Reserved 10101: Reserved 10110: Reserved 10111: Reserved 11000: Reserved 11001: Reserved 11010: Reserved 11011: Reserved 11100: Reserved 11101: VDD else : GND 62 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 0Ch. GPIO Configuration 2 Bit D7 Name Type D6 D5 gpiodrv2[1:0] R/w D4 D3 D2 D1 pup2 Gpio2[4:0] R/w R/w D0 Reset value = 00000000 Bit Name 7:6 gpiodrv2[1:0] 5 Pup2 Function GPIO Driving Capability Setting. Pullup Resistor Enable on GPIO2. When set to 1 the a 200 kresistor is connected internally between VDD and the pin if the GPIO is configured as a digital input. GPIO1 pin Function Select. 00000: Inverted Power-On-Reset (output) 00001: Wake-Up Timer: 1 when WUT has expired (output) 4:0 gpio2[4:0] 00010: Low Battery Detect: 1 when battery is below threshold setting (output) 00011: Direct Digital Input 00100: External Interrupt, falling edge (input) 00101: External Interrupt, rising edge (input) 00110: External Interrupt, state change (input) 00111: ADC Analog Input 01000: Reserved (Analog Test N Input) 01001: Reserved (Analog Test P Input) 01010: Direct Digital Output 01011: Reserved (Digital Test Output) 01100: Reserved (Analog Test N Output) 01101: Reserved (Analog Test P Output) 01110: Reference Voltage (output) 01111: TX Data CLK output to be used in conjunction with TX Data pin (output) 10000: TX Data input for direct modulation (input) 10001: External Retransmission Request (input) 10010: TX State (output) 10011: TX FIFO Almost Full (output) 10100: Reserved 10101: Reserved 10110: Reserved 10111: Reserved 11000: Reserved 11001: Reserved 11010: Reserved 11011: Reserved 11100: Reserved 11101: VDD else : GND 63 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 0Eh. I/O Port Configuration Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Reserved extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 Type R R R R/w R R/w R/w R/w Reset value = 00000000 Bit 7 Name Reserved Function Reserved External Interrupt Status. 6 extitst[2] If the GPIO2 is programmed to be external interrupt sources then the status can be read here. External Interrupt Status. 5 extitst[1] If the GPIO1 is programmed to be external interrupt sources then the status can be read here. External Interrupt Status. 4 extitst[0] If the GPIO0 is programmed to be external interrupt sources then the status can be read here. Interrupt Request Output on the SDO Pin. 3 itsdo nIRQ output is present on the SDO pin if this bit is set and the nSEL input is inactive (high). Direct I/O for GPIO2. 2 dio2 If the GPIO2 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO2 is configured to be a direct input then the value of the pin can be read here. Direct I/O for GPIO1. 1 dio1 If the GPIO1 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO1 is configured to be a direct input then the value of the pin can be read here. Direct I/O for GPIO0. 0 dio0 If the GPIO0 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO0 is configured to be a direct input then the value of the pin can be read here. 64 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 0Fh. ADC Configuration Bit D7 Name Type D6 D5 adcstart/ D3 adcsel[2:0] adcdone R D4 R D2 D1 adcref[1:0] R R/ w R D0 adcgain[1:0] R/w R/w R/w Reset value = 00000000 Bit 7 Name adcstart/adcdone Function ADC Measurement Start Bit. Reading this bit gives 1 if the ADC measurement cycle has been finished. ADC Input Source Selection. The internal 8-bit ADC input source can be selected as follows: 6:4 adcsel[2:0] 000: Internal Temperature Sensor 001: GPIO0, single-ended 010: GPIO1, single-ended 011: GPIO2, single-ended 100: GPIO0(+) – GPIO1(–), differential 101: GPIO1(+) – GPIO2(–), differential 110: GPIO0(+) – GPIO2(–), differential 111: GND ADC Reference Voltage Selection. The reference voltage of the internal 8-bit ADC can be selected as follows: 3:2 adcref[1:0] 0X: bandgap voltage (1.2 V) 10: VDD / 3 11: VDD / 2 ADC Sensor Amplifier Gain Selection. The full scale range of the internal 8-bit ADC in differential mode (see adcsel) 1:0 adcgain[1:0] can be set as follows: adcref[0] = 0: adcref[0] = 1: FS = 0.014 x (adcgain[1:0] + 1) x VDD FS = 0.021 x (adcgain[1:0] + 1) x VDD 65 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 10h. ADC Sensor Amplifier Offset Bit D7 D6 D5 Name Reserved Type R D4 D3 D2 D1 D0 adcoffs[3:0] R/w Reset value = xxxx0000 Bit Name 7：4 3：0 Reserved adcoffs[3:0] Function Reserved. ADC Sensor Amplifier Offset*. *Note: The offset can be calculated as Offset = adcoffs[2:0] x VDD / 1000; MSB = adcoffs[3] = Sign bit. Register 11h. ADC Value Bit D7 D6 D5 D4 D3 Name adc[7:0] Type R D2 D1 D0 Reset value = xxxxxxxx Bit Name 7：0 adc[7:0] Function Internal 8 bit ADC Output Value. 66 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 12h. Temperature Sensor Calibration Bit D7 D6 D5 D4 D3 Name tsrange[1:0] entsoffs entstrim Type R/w R/w R/w D2 D1 D0 tstrim[3:0] R/w Reset value = 00100000 Bit Name tsrange[1:0] Function Temperature Sensor Range Selection. (FS range is 0..1024 mV) 00: 7：6 –40℃ .. 64℃ (full operating range), with 0.5℃ resolution (1 LSB in the 8-bit ADC) 01: –40℃… 85℃, with 1℃ 11: 0 ℃ …85℃, with 0.5℃ 10: –40 F … 216 F, with 1 o o resolution (1 LSB in the 8-bit ADC) resolution (1 LSB in the 8-bit ADC) o F resolution (1 LSB in the 8-bit ADC) 5 entsoffs Temperature Sensor Offset to Convert from K to ºC. 4 entstrim Temperature Sensor Trim Enable. 3：0 tstrim[3:0] Temperature Sensor Trim Value. Register 13h. Temperature Value Offset Bit D7 D6 D5 D4 D3 Name tvoffs[7:0] Type R/W D2 D1 D0 Reset value = 00000000 Bit Name 7：0 tvoffs[7:0] Function Temperature Value Offset. This value is added to the measured temperature value. (MSB, tvoffs[8]: sign bit) Note: If a new configuration is needed (e.g., for the WUT or the LDC), proper functionality is required. The function must first be disabled, then the settings changed, then enabled back on. 67 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 14h. Wake-Up Timer Period 1 Bit D7 Name D6 D5 D4 D3 Reserved D1 D0 wtr[4:0] R/w Type D2 R/w Reset value = xxx00011 Bit Name 7：5 Reserved Function Reserved. Wake Up Timer Exponent (R) Value*. 4：0 wtr[4:0] Maximum value for R is decimal 20. A value greater than 20 will yield a result as if 20 were written. R Value = 0 can be written here. *Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R ) / 32.768 ms. R = 0 is allowed, and the maximum value for R is decimal 20. A value greater than 20 will result in the same as if 20 was written. Register 15h. Wake-Up Timer Period 2 Bit D7 D6 D5 D4 D3 Name wtm[15:8] Type R/W D2 D1 D0 D1 D0 Reset value = 00000000 Bit Name 7：0 wtm[15:8] Function Wake Up Timer Mantissa (M) Value*. *Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R ) / 32.768 ms. Register 16h. Wake-Up Timer Period 3 Bit D7 D6 D5 D4 D3 Name wtm[7:0] Type R/W D2 Reset value = 00000001 Bit Name 7：0 wtm[7:0] Function Wake Up Timer Mantissa (M) Value*. M[7:0] = 0 is not valid here. Write at least decimal 1. *Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R ) / 32.768 ms. 68 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 17h. Wake-Up Timer Value 1 Bit D7 D6 D5 D4 D3 Name wtm[15:8] Type R/W D2 D1 D0 D1 D0 Reset value = xxxxxxxx Bit Name 7：0 wtm[15:8] Function Wake Up Timer Mantissa (M) Value*. *Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R ) / 32.768 ms. Register 18h. Wake-Up Timer Value 2 Bit D7 D6 D5 D4 D3 Name wtm[7:0] Type R/W D2 Reset value = xxxxxxxx Bit Name 7：0 wtm[7:0] Function Wake Up Timer Mantissa (M) Value*. *Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R ) / 32.768 ms. 69 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 1Ah. Low Battery Detector Threshold Bit D7 Name D6 D5 D4 D3 Reserved Type D2 D1 D0 lbdt[4:0] R/w R Reset value = xxx10100 Bit Name Function 7：5 Reserved Reserved. Low Battery Detector Threshold. 4：0 lbdt[4:0] This threshold is compared to Battery Voltage Level. If the Battery Voltage is less than the threshold the Low Battery Interrupt is set. Default = 2.7 V.* *Note: The threshold can be calculated as Vthreshold = 1.7 + lbdt x 50 mV. Register 1Bh. Battery Voltage Level Bit D7 Name D6 D5 D4 D3 Reserved Type D2 D1 D0 vbat[4:0] R R Reset value = xxxxxxxx Bit Name 7：5 Reserved Function Reserved. Battery Voltage Level. 4：0 vbat[4:0] The battery voltage is converted by a 5 bit ADC. In Sleep Mode the register is updated in every 1 s. In other states it measures continuously. 70 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 30h. Data Access Control Bit D7 D6 D5 D4 D3 D2 Name Reserved lsbfrst crcdonly Reserved enpactx encrc R/w R/w R/w R/w Type R/w D1 R/w D0 crc[1:0] R/w Reset value = 10001101 Bit Name 7 Reserved 6 lsbfrst 5 crcdonly 4 Reserved Function Reserved. LSB First Enable. The LSB of the data will be transmitted first if this bit is set. CRC Data Only Enable. When this bit is set to 1 the CRC is calculated on the packet data fields only. Reserved. Enable Packet TX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be 3 enpactx enabled. Setting enpactx = 1 will enable automatic packet handling in the TX path. Register 30–4D allow for various configurations of the packet structure. Setting enpactx = 0 will not do any packet handling in the TX path. It will only transmit what is loaded to the FIFO. 2 encrc CRC Enable. Cyclic Redundancy Check generation is enabled if this bit is set. CRC Polynomial Selection. 1:0 crc[1:0] 00: CCITT 01: CRC-16 (IBM) 10: IEC-16 11: Biacheva 71 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 31h. EZMAC® Status Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Reserved pktx pksent Type R R R Reset value = 00000000 Bit Name 7:2 Reserved 1 pktx 0 pksent Function Reserved. Packet Transmitting. When pktx = 1 the radio is currently transmitting a packet. Packet Sent. A pksent = 1 a packet has been sent by the radio. (Same bit as in register 03, but reading it does not reset the IRQ) 72 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 33h. Header Control 2 Bit D7 Name Reserved Type D6 D5 D4 D3 hdlen[2:0] fixpklen R/w R D2 R/w D1 synclen[1:0] D0 prealen[8] R/w R/w Reset value = 00100010 Bit Name 7 Reserved Function Reserved. Header Length. Length of header used if packet handler is enabled for TX (enpactx). Headers are transmitted in descending order. 6:4 hdlen[2:0] 000: No TX header 001: Header 3 010: Header 3 and 2 011: Header 3 and 2 and 1 100: Header 3 and 2 and 1 and 0 Fix Packet Length. 3 fixpklen When fixpklen = 1 the packet length (pklen[7:0]) is not included in the header. When fixpklen = 0 the packet length is included in the header. Synchronization Word Length. The value in this register corresponds to the number of bytes used in the Synchronization Word. The synchronization word bytes are transmitted in 2:1 0 synclen[1:0] prealen[8] descending order. 00: Synchronization Word 3 01: Synchronization Word 3 and 2 10: Synchronization Word 3 and 2 and 1 11: Synchronization Word 3 and 2 and 1 and 0 MSB of Preamble Length. See register Preamble Length. 73 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 34h. Preamble Length Bit D7 D6 D5 Name D4 D3 D2 D1 D0 prealen[7:0] R/w Type Reset value = 00001000 Bit Name prealen[7:0] Function Preamble Length. The value in the prealen[8:0] register corresponds to the number of nibbles (4 bits) in the packet. For example prealen[8:0] = ‗000001000‘ corresponds to a 7：0 preamble length of 32 bits (8 x 4bits) or 4 bytes. The maximum preamble length is prealen[8:0] = 111111111 which corresponds to a 255 bytes Preamble. Writing 0 will have the same result as if writing 1, which corresponds to one single nibble of preamble. Register 36h. Synchronization Word 3 Bit D7 D6 D5 D4 D3 Name sync[31:24] Type R/W D2 D1 D0 D2 D1 D0 Reset value = 00101101 Bit Name 7：0 sync[31:24] Function Synchronization Word 3. 4th byte of the synchronization word. Register 37h. Synchronization Word 2 Bit D7 D6 D5 D4 D3 Name sync[23:16] Type R/W Reset value = 11010100 Bit Name 7：0 sync[23:16] Function Synchronization Word 2. 3rd byte of the synchronization word. 74 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 38h. Synchronization Word 1 Bit D7 D6 D5 D4 Name D3 D2 D1 D0 D2 D1 D0 D2 D1 D0 sync[15:8] R/w Type Reset value = 00000000 Bit Name 7：0 sync[15:8] Function Synchronization Word 1. 2nd byte of the synchronization word. Register 39h. Synchronization Word 0 Bit D7 D6 D5 D4 D3 Name sync[7:0] Type R/W Reset value = 00000000 Bit Name 7：0 sync[7:0] Function Synchronization Word 0. 1st byte of the synchronization word. Register 3Ah. Transmit Header 3 Bit D7 D6 D5 D4 D3 Name txhd[31:24] Type R/W Reset value = 00000000 Bit Name 7：0 txhd[31:24] Function Transmit Header 3. 4th byte of the header to be transmitted. 75 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 3Bh. Transmit Header 2 Bit D7 D6 D5 D4 Name D3 D2 D1 D0 D2 D1 D0 D2 D1 D0 txhd[23:16] R/w Type Reset value = 00000000 Bit Name 7：0 txhd[23:16] Function Transmit Header 2. 3rd byte of the header to be transmitted. Register 3Ch. Transmit Header 1 Bit D7 D6 D5 D4 D3 Name txhd[15:8] Type R/W Reset value = 00000000 Bit Name 7：0 txhd[15:8] Function Transmit Header 1. 2nd byte of the header to be transmitted. Register 3Ah. Transmit Header 3 Bit D7 D6 D5 D4 D3 Name txhd[7:0] Type R/W Reset value = 00000000 Bit Name 7：0 txhd[7:0] Function Transmit Header 0. 1st byte of the header to be transmitted. 76 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 3Eh. Packet Length Bit D7 D6 D5 D4 D3 Name pklen[7:0] Type R/W D2 D1 D0 Reset value = 00000000 Bit Name Function Packet Length. The value in the pklen[7:0] register corresponds directly to the number of bytes 7：0 in the Packet. For example pklen[7:0] = ‗00001000‘ corresponds to a packet pklen[7:0] length of 8 bytes. The maximum packet length is pklen[7:0] = ‗11111111‘, a 255 byte packet. Writing 0 is possible, in this case we do not send any data in the packet. Table 22. Internal Analog Signals Available on the Analog Test Bus atb[3:0] TESTp TESTn 0 NC NC 1 PLL_Icp_Test PLL_IBG_5u 2 PLL_VBG_Bias VSS_VCO 3 PLL_Vctrl PLL_Iptat_5u 4 VCO_LDO_VBG VCO_LDO_VOUT 5 RF_LDO_VBG RF_LDO_VOUT 6 PLL_LDO_VBG PLL_LDO_VOUT 7 RCOSC_65kout RCOSC_VSS 8 NC NC 9 LBD_Comp LBD_VBG(TS) 10 TS_VBG TS_VTemp 11 DIG_LDO_VBG DIG_LDO_VFB 12 PA_Ramp NC 13 ADC_VIN ADC_VDAC 14 NC NC 15 NC NC 77 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 51h. Digital Test Bus Select Bit D7 D6 D5 D4 D3 D2 Name Reserved ensctest dtb[5:0] Type R/W R/W R/W D1 D0 Reset value = 00000000 Bit Name 7 Reserved 6 ensctest 5:0 dtb[5:0] Function Reserved. Scan Test Enable. When set to 1 then GPIO0 will be the ScanEn input. Digital Test Bus. GPIO must be configured to Digital Test Mux output. Table 23. Internal Digital Signals Available on the Digital Test Bus 78 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Table 23. Internal Digital Signals Available on the Digital Test Bus (Continued) 79 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 52h. TX Ramp Control Bit D7 Name Reserved Type D6 D5 D4 D3 txmod[2:0] R/w D2 ldoramp[1:0] R/w R/w D1 D0 txramp[1:0] R/w Reset value = 00101111 Bit Name 7 Reserved Function Reserved. TX Modulation Delay. 6:4 txmod[2:0] The time delay between PA enable and the beginning of the TX modulation to allow for PA ramp-up. It can be set from 0 μs to 28 μs in 4 μs steps. This also works during PA ramp down. TX LDO Ramp Time. The RF LDO is used to help ramp the PA to prevent VCO pulling and spectral splatter. 3:2 ldoramp[1:0] 00: 5 μs 01: 10 μs 10: 15 μs 11: 20 μs TX Ramp Time. The PA is ramped up slowly to prevent VCO pulling and spectral splatter. This register sets the time the PA is ramped up. 1:0 txramp[1:0] 00: 5 μs 01: 10 μs 10: 15 μs 11: 20 μs 80 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 The total settling time (cold start) of the PLL after the calibration can be calculated as T CS = TS + TO. Register 53h. PLL Tune Time Bit D7 D6 D5 D4 D3 D2 D1 Name pllts[4:0] pllts0 Type R/w R/w D0 Reset value = 01010010 Bit Name Function PLL Soft Settling Time (TS). This register will set the settling time for the PLL from a previous locked 7:3 frequency in Tune mode. The value is configurable between 0 μs and 310 μs, pllts[4:0] in 10 μs intervals. The default plltime corresponds to 100 μs. See formula above. PLL Settling Time (TO). 2:0 This register will set the time allowed for PLL settling after the calibrations are pllts0t completed. The value is configurable between 0 μs and 70 μs, in 10 μs steps. The default pllt0 corresponds to 20 μs. See formula above. Register 54h. PA Boost Bit D7 Name Type D6 D5 D4 Reserved[7:6] D3 D2 inv_pre_th R/w R/w D1 D0 ldo_pa_boost pa_vbias_boost R/w R/w Reset value = 01010100 Bit Name Function 7:6 Reserved[7:6] Reserved. 5:2 inv_pre_th[5:2] Invalid Preamble Threshold. 1 ldo_pa_boost 0 pa_vbias_boost LDO PA Boost. PA VBIAS Boost. Invalid preamble will be evaluated during this period: (invalid_preamble_Threshold x 4) x Bit Rate period. 81 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 55h. Calibration Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Reserved xtalstarthalf Reserved enrcfcal rccal vcocaldp vcocal skipvco Type R R/w R/w R/w R R/w R/w R/w Reset value = x1x00100 Bit Name 7 Reserved 6 xtalstarthalf 5 Reserved 4 enrcfcal Function Reserved. If Set, the Xtal Wake Time Period is Halved. Reserved. RC Oscillator Fine Calibration Enable. If this bit is set to 1 then the RC oscillator performs fine calibration in every app. 30 s. RC Calibration Force. If setting rccal = 1 will automatically perform a forced calibration of the 32 kHz RC 3 rccal Oscillator. The RC OSC will automatically be calibrated if the Wake-Up-Timer is enabled. The calibration takes 2 ms. The 32 kHz RC oscillator must be enabled to perform a calibration. Setting this signal from a 0 to 1 will initiate the calibration. This bit is cleared automatically. VCO Calibration Double Precision Enable. 2 vcocaldp When this bit is set to 1 then the VCO calibration measures longer thus calibrates more precisely. VCO Calibration Force. 1 vcocal If in Idle Mode and pllon = 1, setting vcocal = 1 will force a one time calibration of the synthesizer VCO. This bit is cleared automatically. Skip VCO Calibration. 0 skipvco Setting skipvco = 1 will skip the VCO calibration when going from the Idle state to the TX state. 82 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 56h. Modem Test Bit D7 D6 D5 D4 D3 D2 D1 D0 Name bcrfbyp slicfbyp dttype oscdeten ookth refclksel refclkinv distogg Type R/w R/w R/w R/w R/w R/w R/w R/w Reset value = 00000000 Bit Name Function 7 bcrfbyp If set, BCR phase compensation will be bypassed. 6 slicfbyp If set, slicer phase compensation will be bypassed. Dithering Type. 5 If low and dither enabled, we add +1/0, otherwise if high and dithering enabled, dttype we add ±1. 4 oscdeten 3 ookth 2 refclksel If low, the ADC Oscillation Detection mechanism is allowed to work. If set, we disable the function. If set, in OOK mode, the slicer threshold will be estimated by 8 bits of preamble. By default, this bit is low and the demod estimate the threshold after 4 bits. Delta-Sigma Reference Clock Source Selection 1: 0: 10 MHz PLL 1 refclkinv Delta-Sigma Reference Clock Inversion Enable. 0 distogg If reset, the discriminator toggling is disabled. Register 57h. Charge Pump Test Bit D7 D6 D5 D4 D3 Name pfdrst fbdiv_rst cpforceup cpforcedn cdonly Type R/w R/w R/w R/w D2 R/w D1 D0 cdcurr[2:0] R/w Reset value = 00000000 Bit Name Function 7 pfdrst Direct Control to Analog. 6 fbdiv_rst Direct Control to Analog. 5 cpforceup Charge Pump Force Up. 4 cpforcedn Charge Pump Force Down. 3 cdonly 2:0 cdcurr[2:0] Charge Pump DC Offset Only. Charge Pump DC Current Selection. 83 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 58h. Charge Pump Current Trimming/Override Bit D7 D6 Name cpcurr[1:0] Type R/w D5 D4 D3 D2 cpcorrov D1 D0 cporr[4:0] R/w R/w Reset value = 100xxxxx Bit Name 7:6 cpcurr[1:0] Function Charge Pump Current (Gain Setting). Changing these bits will change the BW of the PLL. The default setting is adequate for all data rates. 5 cpcorrov Charge Pump Correction Override Enable. Charge Pump Correction Value. 4:0 cporr[4:0] During read, you read what the Charge Pump sees. If cpcorrov = 1, then the value you write will go to the Charge Pump, and will also be the value you read. By default, cpcorr[4:0] wakes up as all Zeros. Register 59h. Divider Current Trimming/Delta-Sigma Test Bit D7 D6 Name txcorboosten fbdivhc Type R/w R/w D5 D4 D3 d3trim[1:0] D2 d2trim[1:0] R/w D1 D0 d1p5trim[1:0] R/w R/w Reset value = 10000000 Bit Name Function 7 txcorboosten 6 fbdivhc 5:4 d3trim[1:0] Divider 3 Current Trim Value. 3:2 d2trim[1:0] Divider 2 Current Trim Value. 1:0 d1p5trim[1:0] If this is Set, then vcocorr (reg 5A[5:2]) = 1111 during TX Mode and VCO CAL followed by TX. Feedback (fractional) Divider High Current Enable (+5 μA). Divider 1.5 (div-by-1.5) Current Trim Value. 84 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 5Ah. VCO Current Trimming Bit D7 D6 D5 D4 D3 D2 D1 D0 Name txcurboosten vcocorrov vcocorr[3:0] vcocur[1:0] Type R/w R/w R/w R/w Reset value = 00000011 Bit Name Function 7. txcurboosten 6 vcocorrov 5:2 vcocorr[3:0] VCO Current Correction Value. 1:0 vcocur[1:0] VCO Current Trim Value. If this is Set, then vcocur = 11 during TX Mode and VCO CAL followed by TX. VCO Current Correction Override. Register 5Bh. VCO Calibration/Override Bit D7 Name vcocalov/vcdone Type D6 D5 D4 D3 D2 D1 D0 vcocal[6:0] R/w R/w Reset value = 00000000 Bit Name Function VCO Calibration Override/Done. When vcocalov = 0 the internal VCO calibration results may be viewed by 7. vcocalov/vcdone reading the vcocal register. When vcocalov = 1 the VCO results may be overridden externally through the SPI by writing to the vcocal register. Reading this bit gives 1 if the calibration process has been finished. 6:0 vcocal[6:0] VCO Calibration Results. 85 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 5Ch. Synthesizer Test Bit D7 D6 D5 D4 Name dsmdt vcotype enoloop dsmod dsorder[1:0] Type R/w R R/w R/w R/w D3 D2 D1 D0 dsrstmode dsrst R/w R/w Reset value = 0x001110 Bit Name 7 dsmdt 6 vcotype Function Enable DSM Dithering. If low, dithering is disabled. VCO Type. 0: basic, constant K 1: single varactor, changing K 5 enoloop Open Loop Mode Enable. Delta-Sigma Modulus. 4 dsmod 0: 64 000 1: 65 536 Delta-Sigma Order. 00: 0 order 3:2 dsorder[1:0] 01: 1st order 10: 2nd order 11: Mash 111 1 dsrstmode 0 dsrst Delta-Sigma Reset Mode. Delta-Sigma Reset. 86 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 5Dh. Block Enable Override 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name enmix enina enpga enpa enbf5 endv32 enbf12 enmx2 R/W R/W R/W R/W R/W R/W Type R/W R/W Reset value = 00000000 Bit Name Function 7 enmix Mixer Enable Override. 6 enina LNA Enable Override. 5 enpga PGA Enable Override. 4 enpa Power Amplifier Enable Override. 3 enbf5 Buffer 5 Enable Override. 2 endv32 Divider 3_2 Enable Override. 1 enbf12 Buffer 1_2 Enable Override. 0 enmx2 Multiplexer 2 Enable Override. Register 5Eh. Block Enable Override 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ends enldet enmx3 enbf4 enbf3 enbf11 enbf2 pllreset R/W R/W R/W R/W R/W R/W R/W Type R/W Reset value = 01000000 Bit Name 7 ends Function 6 enldet 5 enmx3 Multiplexer 3 Enable Override. 4 enbf4 Buffer 4 Enable Override. 3 enbf3 Buffer 3 Enable Override. 2 enbf11 Buffer 1_1 Enable Override. 1 enbf2 Buffer 2 Enable Override. 0 pllreset Delta-Sigma Enable Override. Lock Detect Enable. (direct control, does not need override!) PLL Reset Enable Override. 87 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 5Fh. Block Enable Override 3 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name enfrdv endv31 endv2 endv1p5 dvbshunt envco encp enbg Type R/W R/W R/W R/W R/W R/W R/W R/W Reset value = 00000000 Bit Name Function 7 enfrdv Fractional Divider Enable Override. 6 endv31 Divider 3_1 Enable Override. 5 endv2 Divider 2 Enable Override. 4 endv1p5 Divider 1.5 (div-by-1.5) Enable Override. 3 dvbshunt VCO Bias Shunt Enable Override Mode. 2 envco VCO Enable Override. 1 encp Charge Pump Enable Override. 0 enbg Bandgap Enable Override. 88 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 62h. Crystal Oscillator/Power-on-Reset Control Bit D7 D6 D5 D4 D3 D2 D1 D0 bufovr enbuf R/W R/W Name pwst[2:0] clkhyst enbias2x enamp2x Type R R/W R/W R/W Reset value = xxx00100 Bit Name Function Internal Power States of the Module. 7:5 pwst[2:0] LP: 000 RDY: 001 Tune: 011 TX: 010 4 clkhyst 3 enbias2x 2 Times Higher Bias Current Enable. 2 enamp2x 2 Times Higher Amplification Enable. Clock Hysteresis Setting. Output Buffer Enable Override. 1 bufovr If set to 1 then the enbuf bit controls the output buffer. 0: output buffer is controlled by the state machine. 1: output buffer is controlled by the enbuf bit. 0 enbuf Output Buffer Enable. This bit is active only if the bufovr bit is set to 1. 89 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 63h. RC Oscillator Coarse Calibration/Override Bit D7 Name rccov Type R/W D6 D5 D4 D3 D2 D1 D0 rcc[6:0] R/W Reset value = 00000000 Bit Name Function RC Oscillator Coarse Calibration Override. 7 rccov When rccov = 0 the internal Coarse Calibration results may be viewed by reading the rcccal register. When rccov = 1 the Coarse results may be overridden externally through the SPI by writing to the rcccal register. 6:0 rcc[6:0] RC Oscillator Coarse Calibration Override Value/Results. Register 64h. RC Oscillator Fine Calibration/Override Bit D7 D6 D5 D4 D3 Name rcfov rcf[6:0] Type R/W R/W D2 D1 D0 Reset value = 00000000 Bit Name Function RC Oscillator Fine Calibration Override. 7 rcfov When rcfov = 0 the internal Fine Calibration results may be viewed by reading the rcfcal register. When rcfov = 1 the Fine results may be overridden externally through the SPI by writing to the rcfcal register. 6:0 rcf[6:0] RC Oscillator Fine Calibration Override Value/Results. 90 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 65h. LDO Control Override Bit D7 D6 D5 D4 D3 D2 D1 D0 Name enspor enbias envcoldo enifldo enrfldo enpllldo endigldo endigpwdn Type R/W R/W R/W R/W R/W R/W R/W R/W Reset value = 10000001 Bit Name Function 7 enspor Smart POR Enable. 6 enbias Bias Enable. 5 envcoldo 4 enifldo IF LDO Enable. 3 enrfldo RF LDO Enable. 2 enpllldo PLL LDO Enable. 1 endigldo Digital LDO Enable. 0 endigpwdn VCO LDO Enable. Digital Power Domain Powerdown Enable in Idle Mode. Register 66h. LDO Level Settings Bit D7 D6 D5 D4 D3 D2 D1 Name enovr enxtal ents enrc32 Reserved diglvl Type R/W R/W R/W R/W R R/W D0 Reset value = 00000011 Bit Name Function Enable Overrides. 7 enovr If high, ovr values are output to the blocks and can enable or disable them, if low, some ovr value can only enable the blocks. 6 enxtal 5 ents 4 enrc32 3 Reserved 2:0 diglvl Xtal Override Enable Value. Temperature Sensor Enable. 32K Oscillator Enable. Reserved. Digital LDO Level Setting. 91 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 6Bh. GFSK FIR Filter Coefficient Address Bit D7 D6 D5 D4 D3 D2 D1 Name Reserved firadd[2:0] Type R R/W D0 Reset value = xxxxx000 Bit Name 7:3 Reserved Function Reserved. GFSK FIR Filter Coefficient Look-up Table Address. The address for Gaussian filter coefficients used in the TX path. The default GFSK setting is for BT = 0.5. It is not needed to change or load the GFSK Coefficients if BT = 0.5 is satisfactory for the system. 2:0 firadd[2:0] 000: i_coe0 (Default = d1) 001: i_coe1 (Default = d3) 010: i_coe2 (Default = d6) 011: i_coe3 (Default = d10) 100: i_coe4 (Default = d15) 101: i_coe5 (Default = d19) 110: i_coe6 (Default = d20) Register 6Ch. GFSK FIR Filter Coefficient Value Bit D7 Name Type D6 D5 Reserved D4 D3 D2 D1 D0 firval[5:0] R/W R/W Reset value = xxxxx000 Bit Name 7:6 Reserved 5:0 firval[5:0] Function Reserved. FIR Coefficient Value in the lOok-up Table Addressed by the firadd[2:0]. The default coefficient can be read or modified. 92 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 6Dh. TX Power Bit D7 Name D6 D5 D4 Reserved Type R D3 D2 lna_sw R/W D1 D0 txpow[2:0] R/W Reset value = xxxx1000 Bit Name 7:4 Reserved Function Reserved. LNA Switch Controller. 3 lna_sw If set, lna_sw control from the digital will go high during TX modes, and low during other times. If reset, the digital control signal is low at all times. 2:0 txpow[2:0] TX Output Power. The output power is configurable in ~3 dBm steps. 93 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 6Eh. TX Data Rate 1 Bit D7 D6 D5 D4 D3 Name txdr[15:8] Type R/W D2 D1 D0 Reset value = 00001010 Bit Name 7:0 txdr[15:8] Function Data Rate Upper Byte. See formula above. The data rate can be calculated as: TX_DR = 10 3 x txdr[15:0] / 216 [kbps] (if address 70[5] = 0) or The data rate can be calculated as: TX_DR = 103 x txdr[15:0] / 221 [kbps] (if address 70[5] = 1) Register 6Fh. TX Data Rate 0 Bit D7 D6 D5 D4 D3 Name txdr[7:0] Type R/W D2 D1 D0 Reset value = 00111101 Bit Name 7:0 txdr[7:0] Function Data Rate Lower Byte. See formula above. Defaults = 40 kbps. 94 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 70h. Modulation Mode Control 1 Bit D7 Name Type D6 Reserved D5 D4 D3 D2 D1 D0 txdtrtscale enphpwdn manppol enmaninv enmanch enwhite R/W R/W R/W R/W R R/W R/W Reset value = 00001100 Bit Name Function 7:6 Reserved Reserved. 5 txdtrtscale This bit should be set for Data Rates below 30 kbps. 4 enphpwdn If set, the Packet Handler will be powered down when module is in low power mode. Manchester Preamble Polarity (will transmit a series of 1 if set, or series of 0 if 3 manppol reset). This bit affects ONLY the transmitter side, not the receiver. This is valid ONLY if Manchester Mode is enabled. 2 enmaninv Manchester Data Inversion is Enabled if this bit is set. 1 enmanch Manchester Coding is Enabled if this bit is set. 0 enwhite Data Whitening is Enabled if this bit is set. 95 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 71h. Modulation Mode Control 2 Bit D7 Name D6 D5 trclk[1:0] Type D4 dtmod[1:0] R/W R/W D3 D2 eninv fd[8] R/W D1 D0 modtyp[1:0] R/W R/W Reset value = 00000000 Bit Name Function TX Data Clock Configuration. 00: No TX Data CLK is available (asynchronous mode – Can only work with modulations FSK or OOK). 7:6 trclk[1:0] 01: TX Data CLK is available via the GPIO (one of the GPIO‘s should be programmed as well). 10: TX Data CLK is available via the SDO pin. 11: TX Data CLK is available via the nIRQ pin. Modulation Source. 00: 5:4 dtmod[1:0] 3 eninv 2 fd[8] Direct Mode using TX_Data function via the GPIO pin (one of the GPIO‘s should be programmed accordingly as well) 01: Direct Mode using TX_Data function via the SDI pin (only when nSEL is high) 10: FIFO Mode 11: PN9 (internally generated) TX Data. MSB of Frequency Deviation Setting, see "Register 72h. Frequency Deviation". Modulation Type. 1：0 modtyp[1:0] 00: Unmodulated carrier 01: OOK 10: FSK 11: GFSK (enable TX Data CLK (trclk[1:0]) when direct mode is used) The frequency deviation can be calculated: Fd = 625 Hz x fd[8:0]. 96 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 72h. Frequency Deviation Bit D7 D6 D5 D4 D3 Name fd[7:0] Type R/W D2 D1 D0 Reset value = 00100000 Bit Name 7:0 fd[7:0] Function Frequency Deviation Setting. See formula above. Note: It's recommended to use modulation index of 1 or higher (maximum allowable modulation index is 32). The modulation index is defined by 2FN/FR were FD is the deviation and RB is the data rate. When Manchester coding is enabled the modulation index is defined by FD/RB. Register 73h. Frequency Offset 1 Bit D7 D6 D5 D4 D3 Name fo[7:0] Type R/W D2 D1 D0 Reset value = 00000000 Bit Name Function Frequency Offset Setting. 7:0 fo[7:0] The frequency offset can be calculated as Offset = 156.25 Hz x (hbsel + 1) x fo[7:0]. fo[9:0] is a twos complement value. 97 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 74h. Frequency Offset 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Reserved fo[9:8] Type R R/W Reset value = 00000000 Bit Name 7:2 Reserved Function Reserved. Upper Bits of the Frequency Offset Setting. 1:0 fo[9:8] fo[9] is the sign bit. The frequency offset can be calculated as Offset = 156.25 Hz x (hbsel + 1) x fo[7:0]. fo[9:0] is a twos complement value. Register 75h. Frequency Band Select Bit D7 D6 D5 Name Reserved sbsel hbsel fb[4:0] R/W R/W R/W Type R D4 D3 D2 D1 D0 Reset value = 01110101 Bit Name 7 Reserved 6 sbse Function Reserved. Side Band Select. High Band Select. 5 hbsel Setting hbsel = 1 will choose the frequency range from 480–930 MHz (high bands). Setting hbsel = 0 will choose the frequency range from 240–479.9 MHz (low bands). Frequency Band Select. Every increment corresponds to a 10 MHz Band for the Low Bands and a 20 MHz Band 4:0 fb[4:0] for the High Bands. Setting fb[4:0] = 00000 corresponds to the 240–250 MHz Band for hbsel = 0 and the 480–500 MHz Band for hbsel = 1. Setting fb[4:0] = 00001 corresponds to the 250–260 MHz Band for hbsel = 0 and the 500–520 MHz Band for hbsel = 1. The RF carrier frequency can be calculated as follows: fcarrier = (fb+24+(fc+fo) / 64000) x 10000 x (hbsel+1) + (fhch x fhs x 10) [kHz], where parameters fc, fo, fb and hb_sel come from registers 73h–77h. Parameters fhch and fhs come from register 79h and 7Ah. 98 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 76h. Nominal Carrier Frequency Bit D7 D6 D5 D4 D3 Name fc[15:8] Type R/W D2 D1 D0 D2 D1 D0 D2 D1 D0 Reset value = 10111011 Bit Name 7:0 fc[15:8] Function Nominal Carrier Frequency Setting. See formula above. Register 77h. Nominal Carrier Frequency Bit D7 D6 D5 D4 D3 Name fc[7:0] Type R/W Reset value = 10000000 Bit Name 7:0 fc[7:0] Function Nominal Carrier Frequency Setting. See formula above. Register 78h. Miscellaneous Settings Bit D7 D6 Name D5 D4 D3 Reserved[7:4] Type R/W Alt_PA_Seq rcosc_cal[2:0] R/W R/W Reset value = 01111000 Bit Name 7:0 Reserved[7:4] 3 Alt_PA_Seq Function Reserved. Alternative PA sequencing. If set, we will enable the alternative PA sequence. By default, this is not enabled. rcosc_cal[2:0]. 2:0 rcosc_cal[2:0] Fine changes on the RC OSC Calibration target frequency, to help compensate for ―calibration biases.‖ This register should not be changed by costumers. 99 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 79h. Frequency Hopping Channel Select Bit D7 D6 D5 D4 D3 Name fhch[7:0] Type R/W D2 D1 D0 D2 D1 D0 Reset value = 00000000 Bit Name 7:0 fhch[7:0] Function Frequency Hopping Channel Number. Register 7Ah. Frequency Hopping Step Size Bit D7 D6 D5 D4 D3 Name fhs[7:0] Type R/W Reset value = 00000000 Bit Name Function Frequency Hopping Step Size in 10 kHz Increments. 7:0 fhs[7:0] See formula for the nominal carrier frequency at "Register 76h. Nominal Carrier Frequency". 100 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 7Bh. Turn Around and 15.4 Length Compliance Bit D7 D6 D5 D4 Name 15.4 Length Reserved[6:3] Type R/W R/W D3 D2 D1 turn_around_en D0 phase[1:0] R/W R/W Reset value = 01111011 Bit Name Function 15.4 Packet Length Compliance. 7 If set, then PK Length definition for both TX and RX will also include the CRC bytes, 15.4 Length If reset, then the Length refers ONLY to the DATA payload. For example, writing ―9‖ to this register when it is set, means we are sending/expecting ―7‖ bytes of DATA, and the other ―2‖ should be the CRC (CRC should be enabled separately). 6:3 Reserved[6:3] 2 turn_around_en Reserved. Turn Around Enable. Enabling for the turn around functionality. Turn Around Phase. The RX to TX and vice-versa change in frequency will happen (if bit [2] is set) at the 1:0 phase[1:0] last byte, and these two registers set the bit position in which the frequency shifts should occur. Make sure it does not happen to early otherwise the last bits will be missed. Register 7Ch. TX FIFO Control 1 Bit Name Type D7 D6 D5 D4 Reserved D3 D2 D1 D0 txafthr[5:0] R/W R/W Reset value = 00110111 Bit Name Function 7：6 Reserved Reserved. 5：0 txafthr[5:0] TX FIFO Almost Full Threshold. 101 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 Register 7Dh. TX FIFO Control 2 Bit D7 Name D6 D5 D4 D3 Reserved Type D2 D1 D0 D1 D0 txfaethr[5:0] R/W R/W Reset value = 00000100 Bit Name 7：6 Reserved 5：0 txfaethr[5:0] Function Reserved. TX FIFO Almost Empty Threshold. Register 7Fh. FIFO Access Bit D7 D6 D5 Name D4 D3 D2 fifod[7:0] Type R/W Reset value = NA Bit Name Function FIFO Data. A Write (R/W = 1) to this Address will begin a Burst Write to the TX FIFO. The 7：0 fifod[7:0] FIFO will be loaded in the same manner as a Burst SPI Write but the SPI address will not be incremented. To conclude the TX FIFO Write the SEL pin should be brought HIGH, in the same manner. 102 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 11. Pin Descriptions: RFM42/43 RFM42/43-S1 RFM42/43-S2 RFM42/43-D 103 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 VCC S +1.8 to +3.6 V supply voltage. The recommended VCC supply voltage is +3.3 V. GND S Ground reference. GPIO_0 I/O GPIO_1 I/O GPIO_2 I/O SDO O General Purpose Digital I/O that may be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. See the SPI GPIO Configuration Registers, Address 0Bh, 0Ch, and 0Dh for more information. 0–VCC V digital output that provides a serial readback function of the internal control registers. Serial Data input. 0–VCC V digital input. This pin provides the serial data stream for the 4-line SDI I serial data bus. Serial Clock input. 0–VDD V digital input. This pin provides the serial data clock function for SCLK I the 4-line serial data bus. Data is clocked into the RFM42/43 on positive edge transitions. Serial Interface Select input. 0– VCC V digital input. This pin provides the Select/Enable nSEL I function for the 4-line serial data bus. The signal is also used to signify burst read/write mode. General Microcontroller Interrupt Status output. When the RFM42/43 exhibits anyone of the Interrupt Events the nIRQ pin will be set low=0. Please see the Control Logic registers nIRQ O section for more information on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a corresponding SPI Interrupt Status Registers, Address 03h and 04h. I SDN Shutdown input pin. 0–VCC V digital input. SDN should be = 0 in all modes except Shutdown mode. When SDN =1 the chip will be completely shutdown and the contents of the registers will be lost. ANT NC I/O RF signal output/input.(50 OHM output /input Impedance) No Connection 104 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 12. Mechanical Dimension:RFM42/43 SMD PACKAGE（S1） SMD PACKAGE（S2） 105 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 DIP PACKAGE（D） 106 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 13. Ordering Information Part Number=module type—operation band—package type RFM42/43—433—D module type operation band Package example：1，RFM43 module at 433MHz band, DIP : RFM43-433-D。 2，RFM42 module at 868MHZ band, SMD, thickness at 4.9mm: RFM42-868-S1。 107 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 14. Errata Status Summary Errat a# 1 2 3 4 5 Title Impact TX Current Consumption. Major Some non-standard frequencies are Status Increased current consumption at +13 dBm, other power levels unaffected. Major Will be fixed in the next revision. Minor Will be fixed in the next revision. Minor Will be fixed in the next revision. Minor Will be fixed in the next revision. Informational Will update data sheet to reflect operation. not supported. Radio does not return to the low power state when in Auto TX mode. Potential modem failure with default settings. Default register settings for optimal current consumption. Register modification required for TX 6 data-rates greater than 100 kbps. 7 Wake Up Timer and Low Duty Cycle mode not functional. Minor Use the micro or 32 kHz option for these functions. Will be fixed in the next revision. Impact Definition: Each erratum is marked with an impact, as defined below: Minor: Major: Information: Workaround exists. Errata that do not conform to the data sheet or standard. The device behavior is acceptable the data sheet will be changed to match the device behavior. 108 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42/43 15. Errata Details 1. Description: The TX current consumption at +13 dBm does not meet specification; lower power settings are within specification. Impact: May impact battery life. The +13 dBm current consumption is at 34 mA versus the data sheet specification of 28 mA. Workaround: No workaround exists in the current silicon for +13 dBm; lower power levels are unaffected. Resolution: Will be fixed in the next revision. 2. Description: Some non-standard frequencies are not supported. Impacts: Operation in frequencies between 240-280 MHz and 480-560 MHz should be avoided. Workaround: These are non-standard bands and should result in no customer impact; no workaround at this time. Resolution: Will be fixed in the next revision. 3. Description: Radio does not return to the low power state when in Auto TX mode. Impacts: When using Auto TX mode, the radio will not return to the low power state when the TX FIFO reaches the empty state. Workaround: The FIFO underflow interrupt can be enabled allowing the external MCU to wake up when the TX FIFO is empty and put the radio into the low power state: Program register 05h bit 7(enfferr = 1). Resolution: Will be fixed in the next revision. 4. Description: Potential modem failure in receive mode with default settings. Impacts: Under strong blocker conditions, the modem can fail unless the listed workaround is followed. Workaround: Operate the radio with AFC enabled: Program register 56h to C1h. Resolution: Will be fixed in the next revision. 5.Description: Default register settings for optimal current consumption. Impacts: Current consumption. Workaround: Program register 57h bits 2:0 (cdcurr[2:0] = 001), register 59 bit 6 (fbdivhc = 0), register 5Ah bits 1:0 (vcocur[1:0] = 01). Resolution: Will be fixed in the next revision. 6. Description: Register modification required for TX data-rates greater than 100 kbps. Impacts: Eye closure and phase noise. Workaround: Program register 58h bits 7:6 (cpcurr[1:0] = 11). Resolution: Will update data sheet to reflect operation. 109 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM42: Value Unit –0.3, +3.6 V Voltage on Digital Control Inputs –0.3, VDD + 0.3 V Voltage on Analog Inputs 7. Description: Wake-up Timer Operating Ambient Temperature Rangeand TA Low Duty Cycle Modes not functional. –0.3, VDD + 0.3 V –40 to +85 ℃ 30 ℃/W Parameter VDD to GND R–0.3, F +8.0 M 4 2 / 4V 3 VDD to GND on TX Output Pin Thermal Impacts: Impedance θ JAfeatures are not supported. These Junction Temperature TJ +125 ℃ Workaround:Range Use the external microcontroller or the 32 kHz XTAL option on the to implement Storage Temperature TSTG –55RF22 to +125 ℃ these functions. Note: Stresses beyond those listed under ―Absolute Maximum Ratings‖ may cause permanent damage to the device. These are stress ratings only Will and be functional the device at or beyond these ratings in the operational sections of the Resolution: fixed inoperation the nextofrevision. specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Caution: ESD sensitive device. Power Amplifier may be damaged if switched on without proper load or termination connected. HOPE MICROELECTRONICS CO.,LTD Add:4/F, Block B3, East Industrial Area, Huaqiaocheng, Shenzhen, Guangdong, China Tel: 86-755-82973805 Fax: 86-755-82973550 Email: [email protected] [email protected] Website: http://www.hoperf.com http://hoperf.en.alibaba.com This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Hope Microelectronics or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. ©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved. 110 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com