TI MSP430G2231QPW1EP

MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
MIXED SIGNAL MICROCONTROLLER
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
(1)
Low Supply-Voltage Range: 1.8 V to 3.6 V
Ultra-Low Power Consumption
– Active Mode: 220 µA at 1 MHz, 2.2 V
– Standby Mode: 0.5 µA
– Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With
One Calibrated Frequency
– Internal Very Low Power Low-Frequency
(LF) Oscillator
– 32-kHz Crystal (1)
– External Digital Clock Source
16-Bit Timer_A With Two Capture/Compare
Registers
Universal Serial Interface (USI) Supporting SPI
and I2C (See Table 1)
Brownout Detector
10-Bit 200-ksps A/D Converter With Internal
Reference, Sample-and-Hold, and Autoscan
(See Table 1)
Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security
Fuse
Crystal oscillator cannot be operated beyond 105°C
•
•
•
•
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
For Family Members Details, See Table 1 and
Available in a 14-Pin Plastic Small-Outline Thin
Package (TSSOP) (PW)
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide (SLAU144)
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
(2)
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Extended (–40°C/125°C)
Temperature Range (2)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Custom temperature ranges available
DESCRIPTION
The MSP430G2231 is an ultra-low-power microcontroller consisting of several devices featuring different sets of
peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized
to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit
RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally
controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430G2231 has a 10-bit A/D converter and built-in communication capability using synchronous
protocols (SPI or I2C). For configuration details, see Table 1.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Table 1. Available Options
Device
MSP430G2231
BSL
EEM
Flash
(KB)
RAM
(B)
Timer_A
USI
ADC10
Channel
Clock
I/O
Package
Type
-
1
2
128
1x TA2
1
8
LF, DCO, VLO
10
14-TSSOP
Table 2. ORDERING INFORMATION (1)
TA
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
VID NUMBER
–40°C to 125°C
TSSOP - PW
MSP430G2231QPW1EP
G2231EP
V62/12621-01XE
(1)
2
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Device Pinout
PW PACKAGE
(TOP VIEW)
DVCC
P1.0/TA0CLK/ACLK/A0
1
14
2
13
P1.1/TA0.0/A1
P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREFP1.4/SMCLK/A4/VREF+/VEREF+/TCK
3
12
4
11
5
10
6
9
P1.5/TA0.0/A5/SCLK/TMS
7
8
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/A7/SDI/SDA/TDO/TDI
P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK
NOTE: See port schematics in Application Information for detailed I/O information.
Functional Block Diagram
XIN XOUT
DVCC
DVSS
P2.x
P1.x
8
2
Port P1
Port P2
8 I/O
Interrupt
capability
pull-up/down
resistors
2 I/O
Interrupt
capability
pull-up/down
resistors
ACLK
Clock
System
ADC
SMCLK
Flash
2kB
1kB
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
Emulation
2BP
JTAG
Interface
RAM
128B
10-Bit
8 Ch.
Autoscan
1 ch DMA
USI
Brownout
Protection
Watchdog
WDT+
15-Bit
Spy-Bi
Wire
Timer0_A2
2 CC
Registers
Universal
Serial
Interface
SPI, I2C
RST/NMI
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
3
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Table 3. Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
P1.0/
TA0CLK/
ACLK/
A0
2
I/O
General-purpose digital I/O pin
Timer0_A, clock signal TACLK input
ACLK signal output
ADC10 analog input A0 (1)
P1.1/
TA0.0/
A1
3
I/O
General-purpose digital I/O pin
Timer0_A, capture: CCI0A input, compare: Out0 output
ADC10 analog input A1 (1)
P1.2/
TA0.1/
A2
4
I/O
General-purpose digital I/O pin
Timer0_A, capture: CCI1A input, compare: Out1 output
ADC10 analog input A2 (1)
I/O
General-purpose digital I/O pin
ADC10, conversion clock output (1)
ADC10 analog input A3 (1)
ADC10 negative reference voltage (1)
I/O
General-purpose digital I/O pin
SMCLK signal output
ADC10 analog input A4 (1)
ADC10 positive reference voltage (1)
JTAG test clock, input terminal for device programming and test
I/O
General-purpose digital I/O pin
Timer0_A, compare: Out0 output
ADC10 analog input A5 (1)
USI: clock input in I2C mode; clock input/output in SPI mode
JTAG test mode select, input terminal for device programming and test
I/O
General-purpose digital I/O pin
Timer0_A, capture: CCI1A input, compare: Out1 output
ADC10 analog input A6 (1)
USI: Data output in SPI mode
USI: I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
P1.3/
ADC10CLK/
A3/
VREF-/VEREF
P1.4/
SMCLK/
A4/
VREF+/VEREF+/
TCK
P1.5/
TA0.0/
A5/
SCLK/
TMS
5
6
7
P1.6/
TA0.1/
A6/
SDO/
SCL/
TDI/TCLK
8
P1.7/
A7/
SDI/
SDA/
TDO/TDI (2)
9
I/O
General-purpose digital I/O pin
ADC10 analog input A7 (1)
USI: Data input in SPI mode
USI: I2C data in I2C mode
JTAG test data output terminal or test data input during programming and test
XIN/
P2.6/
TA0.1
13
I/O
Input terminal of crystal oscillator
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
XOUT/
P2.7
12
I/O
Output terminal of crystal oscillator (3)
General-purpose digital I/O pin
RST/
NMI/
SBWTDIO
10
I
Reset
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/
SBWTCK
11
I
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DVCC
1
NA
Supply voltage
DVSS
14
NA
Ground reference
-
NA
QFN package pad connection to VSS recommended.
QFN Pad
(1)
(2)
(3)
4
MSP430G2x31 only
TDO or TDI is selected via JTAG instruction.
If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-toregister operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 4 shows examples of the three types of
instruction formats; Table 5 shows the address
modes.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 4. Instruction Word Formats
INSTRUCTION FORMAT
SYNTAX
OPERATION
Dual operands, source-destination
ADD R4,R5
R4 + R5 ---> R5
Single operands, destination only
CALL R8
PC -->(TOS), R8--> PC
Relative jump, un/conditional
JNE
Jump-on-equal bit = 0
Table 5. Address Mode Descriptions (1)
(1)
ADDRESS MODE
S
D
SYNTAX
EXAMPLE
OPERATION
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 -- --> R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) -- --> M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) -- --> M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) -- --> M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) -- --> M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) -- --> R11
R10 + 2-- --> R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 -- --> M(TONI)
S = source, D = destination
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
5
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Operating Modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– DCO's dc generator is disabled if DCO not used in active mode
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
6
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 6. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
Power-Up
External Reset
Watchdog Timer+
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV (2)
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (2) (3)
Watchdog Timer+
Timer_A2
Timer_A2
ADC10
TACCR1 CCIFG, TAIFG (2) (4)
Reset
0FFFEh
31, highest
(non)-maskable
(non)-maskable
(non)-maskable
0FFFCh
30
0FFFAh
29
0FFF8h
28
0FFF6h
27
maskable
0FFF4h
26
maskable
0FFF2h
25
maskable
0FFF0h
24
0FFEEh
23
0FFECh
22
maskable
0FFEAh
21
maskable
0FFE8h
20
I/O Port P2 (two flags)
P2IFG.6 to P2IFG.7 (2) (4)
maskable
0FFE6h
19
(2) (4)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
0FFDEh to
0FFC0h
15 to 0, lowest
(5)
ADC10IFG
(4)
PRIORITY
USIIFG, USISTTIFG (2) (4)
See
(2)
(3)
(4)
(5)
TACCR0 CCIFG
(4)
WORD
ADDRESS
USI
I/O Port P1 (eight flags)
(1)
WDTIFG
SYSTEM
INTERRUPT
P1IFG.0 to P1IFG.7
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are located in the module.
The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
7
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 7. Interrupt Enable Register 1 and 2
Address
7
6
00h
WDTIE
OFIE
NMIIE
ACCVIE
Address
5
4
1
0
ACCVIE
NMIIE
3
2
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
3
2
1
0
01h
Table 8. Interrupt Flag Register 1 and 2
Address
7
6
5
02h
WDTIFG
OFIFG
PORIFG
RSTIFG
NMIIFG
Address
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
Flag set on oscillator fault.
Power-On Reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set via RST/NMI pin
7
6
5
4
3
2
1
0
03h
8
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Memory Organization
Table 9. Memory Organization
MSP430G2231
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
2kB
0xFFFF to 0xFFC0
0xFFFF to 0xF800
Information memory
Size
Flash
256 Byte
010FFh to 01000h
RAM
Size
128B
027Fh to 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh to 0100h
0FFh to 010h
0Fh to 00h
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
9
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1µs. The basic
clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 10. DCO Calibration Data
(Provided From Factory In Flash Information Memory Segment A)
DCO FREQUENCY
1 MHz
CALIBRATION
REGISTER
SIZE
CALBC1_1MHZ
byte
010FFh
CALDCO_1MHZ
byte
010FEh
ADDRESS
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pull-up/pull-down resistor.
WDT+ Watchdog Timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
10
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 11. Timer_A2 Signal Connections – Device With ADC10
INPUT PIN NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
2 - P1.0
TACLK
TACLK
2 - P1.0
3 - P1.1
ACLK
ACLK
SMCLK
SMCLK
TACLK
INCLK
TA0
CCI0A
ACLK (internal)
CCI0B
VSS
GND
VCC
VCC
4 - P1.2
TA1
CCI1A
8 - P1.6
TA1
CCI1B
VSS
GND
VCC
VCC
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN
NUMBER
3 - P1.1
CCR0
TA0
7 - P1.5
4 - P1.2
CCR1
TA1
8 - P1.6
13 - P2.6
USI
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
ADC10 (MSP430G2x31 only)
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
11
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Peripheral File Map
Table 12. Peripherals With Word Access
MODULE
ADC10
REGISTER DESCRIPTION
ADC data transfer start address
Timer_A
ADC10SA
1BCh
ADC10CTL0
01B0h
ADC control 1
ADC10CTL0
01B2h
ADC memory
ADC10MEM
01B4h
Capture/compare register
TACCR1
0174h
Capture/compare register
TACCR0
0172h
TAR
0170h
Capture/compare control
TACCTL1
0164h
Capture/compare control
TACCTL0
0162h
Timer_A control
TACTL
0160h
TAIV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
WDTCTL
0120h
REGISTER
NAME
OFFSET
Timer_A interrupt vector
Watchdog Timer+
OFFSET
ADC control 0
Timer_A register
Flash Memory
REGISTER
NAME
Watchdog/timer control
Table 13. Peripherals With Byte Access
MODULE
ADC10
REGISTER DESCRIPTION
ADC analog enable
USI
ADC10AE0
04Ah
ADC data transfer control 1
ADC10DTC1
049h
ADC data transfer control 0
ADC10DTC0
048h
USI control 0
USICTL0
078h
USI control 1
USICTL1
079h
USICKCTL
07Ah
USI clock control
USI bit counter
USICNT
07Bh
USISR
07Ch
Basic clock system control 3
BCSCTL3
053h
Basic clock system control 2
BCSCTL2
058h
Basic clock system control 1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
USI shift register
Basic Clock System+
Port P2
Port P2 resistor enable
P2REN
02Fh
Port P2 selection
P2SEL
02Eh
P2IE
02Dh
Port P2 interrupt edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
P2IN
028h
Port P2 interrupt enable
Port P2 input
12
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Table 13. Peripherals With Byte Access (continued)
REGISTER
NAME
OFFSET
Port P1 resistor enable
P1REN
027h
Port P1 selection
P1SEL
026h
P1IE
025h
Port P1 interrupt edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
MODULE
Port P1
REGISTER DESCRIPTION
Port P1 interrupt enable
Special Function
P1OUT
021h
Port P1 input
P1IN
020h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
13
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
Voltage applied to any pin (2)
–0.3 V to VCC + 0.3 V
Diode current at any device pin
Storage temperature range, Tstg
(1)
±2 mA
(3)
Unprogrammed device
–55°C to 150°C
Programmed device
–55°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
(2)
(3)
Recommended Operating Conditions
MIN
VCC
Supply voltage
VSS
Supply voltage
TA
Operating free-air temperature
(1)
(2)
MAX
During program execution
1.8
3.6
During flash programming
2.2
3.6
0
Processor frequency (maximum MCLK frequency) (1) (2)
fSYSTEM
NOM
UNIT
V
V
–40
125
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
6
VCC = 2.7 V,
Duty cycle = 50% ± 10%
dc
12
VCC = 3.3 V,
Duty cycle = 50% ± 10%
dc
16
°C
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
System Frequency - MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
1.8 V
Note:
2.7 V
2.2 V
Supply Voltage - V
3.3 V 3.6 V
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Safe Operating Area
14
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
A.
See data sheet for absolute maximum and minimum recommended operating conditions.
B.
Silicon operating life design goal is 10 years at 110°C junction temperature (does not include package interconnect
life).
C.
The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
Figure 2. Operating Life Derating Chart
THERMAL INFORMATION
MSP430G2231
THERMAL METRIC (1)
PW
UNITS
14 PINS
θJA
Junction-to-ambient thermal resistance (2)
102.5
θJCtop
Junction-to-case (top) thermal resistance (3)
31.4
(4)
θJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter (5)
ψJB
Junction-to-board characterization parameter (6)
44.4
(7)
N/A
θJCbot
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Junction-to-case (bottom) thermal resistance
45.0
1.8
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
15
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
Active mode (AM)
current (1 MHz)
IAM,1MHz
(1)
TEST CONDITIONS
VCC
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
MIN
TYP
2.2 V
220
3V
300
MAX
UNIT
µA
390
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Typical Characteristics – Active Mode Supply Current (Into VCC)
5.0
4.0
Active Mode Current − mA
Active Mode Current − mA
f DCO = 16 MHz
4.0
3.0
f DCO = 12 MHz
2.0
f DCO = 8 MHz
1.0
TA = 85 °C
3.0
TA = 25 °C
VCC = 3 V
2.0
TA = 85 °C
TA = 25 °C
1.0
f DCO = 1 MHz
0.0
1.5
2.0
2.5
3.0
3.5
VCC = 2.2 V
4.0
VCC − Supply Voltage − V
Figure 3. Active Mode Current vs VCC, TA = 25°C
16
Submit Documentation Feedback
0.0
0.0
4.0
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 4. Active Mode Current vs DCO Frequency
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
Low-power mode 0
(LPM0) current (2)
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
ILPM2
Low-power mode 2
(LPM2) current (3)
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
ILPM3,LFXT1
Low-power mode 3
(LPM3) current (3)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
ILPM3,VLO
Low-power mode 3
current, (LPM3) (3)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
ILPM4
Low-power mode 4
(LPM4) current (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
ILPM0,1MHz
(1)
(2)
(3)
(4)
TA
VCC
25°C
2.2 V
MIN
TYP
MAX
UNIT
65
25°C
µA
22
2.2 V
125°C
25°C
2.2 V
125°C
25°C
2.2 V
125°C
25°C
85°C
µA
46
2.2 V
125°C
0.7
1.5
3
21
0.5
0.7
2
9.3
0.1
0.5
0.8
1.5
2
7.1
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
Typical Characteristics Low-Power Mode Supply Currents
3.00
2.50
2.75
2.25
ILPM4 – Low-Power Mode Current – µA
ILPM3 – Low-Power Mode Current – µA
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
2.50
2.25
2.00
1.75
1.50
Vcc = 3.6 V
1.25
Vcc = 3 V
1.00
Vcc = 2.2 V
0.75
0.50
Vcc = 1.8 V
0.25
0.00
-40
-20
0
20
40
60
TA – Temperature – °C
Figure 5. LPM3 Current vs Temperature
Copyright © 2012, Texas Instruments Incorporated
80
2.00
1.75
1.50
1.25
Vcc = 3.6 V
1.00
Vcc = 3 V
0.75
Vcc = 2.2 V
0.50
0.25
0.00
-40
Vcc = 1.8 V
-20
0
20
40
60
80
TA – Temperature – °C
Figure 6. LPM4 Current vs Temperature
Submit Documentation Feedback
17
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Schmitt-Trigger Inputs – Ports Px
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
VCC
MIN
RPull
Pullup/pulldown resistor
CI
Input capacitance
VIN = VSS or VCC
MAX
0.45 VCC
0.75 VCC
1.35
2.25
3V
For pullup: VIN = VSS
For pulldown: VIN = VCC
TYP
UNIT
V
0.25 VCC
0.55 VCC
3V
0.75
1.65
3V
0.3
1
V
3V
20
50
kΩ
35
5
V
pF
Leakage Current – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
High-impedance leakage current (1) (2)
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
VCC
MIN
MAX
TA = -40°C to 105°C
3V
±50
TA = 125°C
3V
±120
UNIT
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VOH
VOL
(1)
TEST CONDITIONS
I(OHmax) = –6 mA (1)
High-level output voltage
Low-level output voltage
I(OLmax) = 6 mA
(1)
VCC
MIN
TYP
MAX
UNIT
3V
VCC – 0.3
V
3V
VSS + 0.3
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fPx.y
Port output frequency
(with load)
Px.y, CL = 20 pF, RL = 1 kΩ
fPort_CLK
Clock output frequency
Px.y, CL = 20 pF (2)
(1)
(2)
18
(1) (2)
VCC
MIN
TYP
MAX
UNIT
3V
12
MHz
3V
16
MHz
A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
VCC = 2.2 V
P1.7
TA = 25°C
25
TA = 85°C
20
15
10
5
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
30
0
VCC = 3 V
P1.7
40
TA = 85°C
30
20
10
0
0
0.5
1
1.5
2
2.5
0
VOL − Low-Level Output Voltage − V
0.5
1
1.5
2
2.5
3
3.5
VOL − Low-Level Output Voltage − V
Figure 7.
Figure 8.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
0
VCC = 2.2 V
P1.7
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
TA = 25°C
−5
−10
−15
TA = 85°C
−20
TA = 25°C
−25
0
0.5
VCC = 3 V
P1.7
−10
−20
−30
TA = 85°C
−40
TA = 25°C
−50
1
1.5
2
VOH − High-Level Output Voltage − V
Figure 9.
Copyright © 2012, Texas Instruments Incorporated
2.5
0
0.5
1
1.5
2
2.5
3
3.5
VOH − High-Level Output Voltage − V
Figure 10.
Submit Documentation Feedback
19
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
POR/Brownout Reset (BOR) (1)
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(start)
See Figure 11
dVCC/dt ≤ 3 V/s
V(B_IT–)
See Figure 11 through Figure 13
dVCC/dt ≤ 3 V/s
1.35
V
Vhys(B_IT–)
See Figure 11
dVCC/dt ≤ 3 V/s
130
mV
td(BOR)
See Figure 11
t(reset)
Pulse length needed at RST/NMI pin to
accepted reset internally
(1)
0.7 × V(B_IT–)
V
2000
2.2 V/3 V
2
µs
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) +
Vhys(B_IT–)is ≤ 1.8 V.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 11. POR/Brownout Reset (BOR) vs Supply Voltage
20
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Typical Characteristics – POR/Brownout Reset (BOR)
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
t pw − Pulse Width − µs
1 ns
t pw − Pulse Width − µs
Figure 12. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
t pw − Pulse Width − µs
1000
tf
tr
t pw − Pulse Width − µs
Figure 13. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
21
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage =
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
Supply voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
V
RSELx = 14
2.2
3.6
V
RSELx = 15
3
3.6
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
3V
0.096
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
3V
0.12
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
3V
0.15
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
3V
0.21
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
3V
0.30
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
3V
0.41
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
3V
0.58
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
3V
0.80
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
3V
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
3V
1.6
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
3V
2.3
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
3V
3.4
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
3V
4.25
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
3V
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
3V
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
3V
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
15.25
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
21
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3V
1.35
ratio
SDCO
Frequency step between
tap DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
3V
1.08
ratio
Measured at SMCLK output
3V
50
Duty cycle
22
Submit Documentation Feedback
0.8
MHz
1.5
4.3
7.3
7.8
8.6
MHz
MHz
MHz
13.9
MHz
%
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Calibrated DCO Frequencies – Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
1-MHz tolerance over
temperature (1)
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
-40°C to 105°C
3V
-3
±0.5
+3
%
1-MHz tolerance over VCC
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
30°C
1.8 V to 3.6 V
-3
±2
+3
%
1-MHz tolerance overall
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
-40°C to 105°C
1.8 V to 3.6 V
-6
±3
+6
%
(1)
This is the frequency change from the measured frequency at 30°C over temperature.
Wake-Up From Lower-Power Modes (LPM3/4) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tDCO,LPM3/4
DCO clock wake-up time from
LPM3/4 (1)
tCPU,LPM3/4
CPU wake-up time from LPM3/4 (2)
(1)
(2)
VCC
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz
MIN
3V
TYP
MAX
1.5
UNIT
µs
1/fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4
DCO Wake Time − µs
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 14. DCO Wake-Up Time From LPM3 vs DCO Frequency
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
23
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
1.8 V to 3.6 V
fLFXT1,LF,logic
LFXT1 oscillator logic level
XTS = 0, XCAPx = 0, LFXT1Sx = 3,
square wave input frequency,
TA = -40°C to 125°C
LF mode
1.8 V to 3.6 V
OALF
Oscillation allowance for
LF crystals
Integrated effective load
capacitance, LF mode (2)
CL,eff
fFault,LF
(1)
(2)
(3)
(4)
XTS = 0, LFXT1Sx = 0 or 1
MIN
TYP
1.8 V to 3.6 V
MAX
32768
10000
32768
Hz
50000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
UNIT
Hz
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle, LF mode
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
2.2 V
30
Oscillator fault frequency,
LF mode (3)
XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4)
2.2 V
10
50
pF
70
%
10000
Hz
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift
TA
-40°C to 85°C
125°C
dfVLO/dVCC VLO frequency supply voltage drift
VCC
MIN
TYP
MAX
4
12
20
3V
-40°C to 125°C
3V
25°C
1.8 V to 3.6 V
23
UNIT
kHz
0.5
%/°C
4
%/V
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
TA0, TA1
24
Submit Documentation Feedback
VCC
MIN
TYP
fSYSTEM
3V
20
MAX
UNIT
MHz
ns
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
USI, Universal Serial Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fUSI
USI clock frequency
External: SCLK,
Duty cycle = 50% ±10%,
SPI slave mode
VOL,I2C
Low-level output voltage on SDA and SCL
USI module in I2C mode,
I(OLmax) = 1.5 mA
VCC
MIN
TYP
MAX
fSYSTEM
3V
UNIT
MHz
VSS
+ 0.4
VSS
V
Typical Characteristics – USI Low-Level Output Voltage on SDA and SCL
5.0
5.0
TA = 25°C
4.0
3.0
TA = 85°C
2.0
1.0
0.0
0.0
0.2
TA = 25°C
VCC = 3 V
0.4
0.6
0.8
1.0
VOL − Low-Level Output Voltage − V
Figure 15. USI Low-Level Output Voltage vs Output
Current
Copyright © 2012, Texas Instruments Incorporated
IOL − Low-Level Output Current − mA
I OL − Low-Level Output Current − mA
VCC = 2.2 V
4.0
TA = 85°C
3.0
2.0
1.0
0.0
0.0
0.2
0.4
0.6
0.8
1.0
VOL − Low-Level Output Voltage − V
Figure 16. USI Low-Level Output Voltage vs Output
Current
Submit Documentation Feedback
25
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
TEST CONDITIONS
Analog supply voltage
VAx
Analog input voltage
IADC10
IREF+
VCC
VSS = 0 V
(2)
ADC10 supply current
TA
(3)
Reference supply current,
reference buffer disabled (4)
All Ax terminals, Analog inputs
selected in ADC10AE register
fADC10CLK = 5.0 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
3V
-40°C to
125°C
-40°C to
125°C
3V
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
-40°C to
85°C
Reference buffer supply
current with ADC10SR = 1 (4)
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
-40°C to
85°C
CI
Input capacitance
Only one terminal Ax can be selected
at one time
-40°C to
125°C
3V
RI
Input MUX ON resistance
0 V ≤ VAx ≤ VCC
-40°C to
125°C
3V
IREFB,1
(1)
(2)
(3)
(4)
26
-40°C to
125°C
-40°C to
125°C
TYP
MAX
UNIT
2.2
3.6
V
0
VCC
V
0.6
1.64
mA
0.25
0.84
0.25
0.84
1.1
1.4
3V
Reference buffer supply
current with ADC10SR = 0 (4)
IREFB,0
MIN
mA
3V
mA
3.8
0.5
0.7
3V
mA
0.9
1000
27
pF
2000
Ω
The leakage current is defined in the leakage current table with Px.y/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
10-Bit ADC, Built-In Voltage Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC,REF+
Positive built-in reference
analog supply voltage range
IVREF+ ≤ 1 mA, REF2_5V = 0
VREF+
Positive built-in reference
voltage
IVREF+ ≤ IVREF+max, REF2_5V = 0
ILD,VREF+
Maximum VREF+ load
current (1) (2)
VREF+ load regulation
VCC
2.2
IVREF+ ≤ 1 mA, REF2_5V = 1
3
IVREF+ ≤ IVREF+max, REF2_5V = 1
3V
3V
(1)
MIN
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≉ 0.75 V,
REF2_5V = 0
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≉ 1.25 V,
REF2_5V = 1
TYP
MAX
UNIT
V
1.4
1.5
1.59
2.34
2.5
2.65
±1
V
mA
±2
3V
LSB
±2
VREF+ load regulation response
time (1) (2)
IVREF+ = 100 µA→900 µA,
VAx ≉ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB,
ADC10SR = 0
3V
400
ns
CVREF+
Maximum capacitance at pin
VREF+ (1) (2)
IVREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1
3V
100
pF
TCREF+
Temperature coefficient
IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA
3V
±190
ppm/
°C
tREFON
Settling time of internal
reference voltage to 99.9%
VREF (1) (2)
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
3.6 V
30
µs
tREFBURST
Settling time of reference buffer
to 99.9% VREF (1) (2)
IVREF+ = 0.5 mA,
REF2_5V = 1, REFON = 1,
REFBURST = 1, ADC10SR = 0
3V
2
µs
(1)
(2)
Minimum and maximum parameters are characterized up to TA = 105°C, unless otherwise noted.
Characterized at TA = -40°C to 105°C only.
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
27
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
10-Bit ADC, External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
VEREF+
TEST CONDITIONS
Positive external reference input
voltage range (2)
1.4
3
0
1.2
V
1.4
VCC
V
Differential external reference
input voltage range,
ΔVEREF = VEREF+ – VEREF–
VEREF+ > VEREF–
(1)
(2)
(3)
(4)
(5)
UNIT
VEREF– ≤ VEREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1 (3)
ΔVEREF
Static input current into VEREF–
MAX
VCC
VEREF+ > VEREF–
IVEREF–
TYP
1.4
Negative external reference input
voltage range (4)
Static input current into VEREF+
MIN
VEREF+ > VEREF–,
SREF1 = 1, SREF0 = 0
VEREF–
IVEREF+
VCC
V
(5)
0 V ≤ VEREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
3V
±1
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1 (3)
3V
0
0 V ≤ VEREF– ≤ VCC
3V
±1
µA
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC10SR = 0
fADC10CLK
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10OSC
ADC10 built-in
oscillator frequency
ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
tCONVERT
Conversion time
tADC10ON
Turn-on settling time
of the ADC
(1)
ADC10SR = 1
VCC
MIN
TYP
MAX
0.45
6.3
0.45
1.5
3V
3.7
6.3
3V
2.06
3.51
3V
(1)
MHz
MHz
µs
13 ×
ADC10DIV ×
1/fADC10CLK
fADC10CLK from ACLK, MCLK, or SMCLK,
ADC10SSELx ≠ 0
UNIT
100
ns
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)
MAX
UNIT
EI
Integral linearity error
PARAMETER
3V
±1
LSB
ED
Differential linearity error
3V
±1
LSB
EO
Offset error
3V
±1
LSB
EG
Gain error
3V
±1.1
±2
LSB
ET
Total unadjusted error
3V
±2
±5
LSB
28
Submit Documentation Feedback
TEST CONDITIONS
Source impedance RS < 100 Ω
VCC
MIN
TYP
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
10-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
ISENSOR
TEST CONDITIONS
Temperature sensor supply
current (1)
TCSENSOR
VCC
REFON = 0, INCHx = 0Ah,
TA = 25°C
ADC10ON = 1, INCHx = 0Ah
(2)
60
3V
3.55
tSensor(sample)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
3V
IVMID
Current into divider at channel 11
ADC10ON = 1, INCHx = 0Bh
3V
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID ≉ 0.5 × VCC
3V
tVMID(sample)
Sample time required if channel
11 is selected (5)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
3V
(2)
(3)
(4)
(5)
TYP
3V
Sample time required if channel
10 is selected (3)
(1)
MIN
MAX
UNIT
µA
mV/°C
30
µs
(4)
µA
1.5
V
1220
ns
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
No additional current is needed. The VMID is used during sampling.
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Flash Memory
over recommended ranges of supply voltage and up to operating free-air temperature, TA = 105°C (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
3V
1
5
mA
IERASE
Supply current from VCC during erase
3V
1
7
mA
10
ms
(1)
tCPT
Cumulative program time
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
2.2 V/3.6 V
20
ms
Program/erase endurance
-40°C ≤ TJ ≤
105°C
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
(2)
30
tFTG
tBlock,
Block program time for first byte or word
(2)
25
tFTG
tBlock, 1-63
Block program time for each additional byte or
word
(2)
18
tFTG
tBlock,
Block program end-sequence wait time
(2)
6
tFTG
tMass Erase
Mass erase time
(2)
10593
tFTG
tSeg Erase
Segment erase time
(2)
4819
tFTG
(1)
(2)
0
End
104
105
cycles
15
years
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
29
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
TEST CONDITIONS
(1)
MIN
CPU halted
MAX
1.6
UNIT
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2.2 V/3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V/3 V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge (1))
2.2 V/3 V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
fTCK
TCK input frequency (2)
RInternal
Internal pulldown resistance on TEST
(1)
(2)
TEST CONDITIONS
TA = -40°C to 105°C
TA = -40°C to 105°C
VCC
MIN
TYP
2.2 V/3 V
15
100
2.2 V
0
5
MHz
10
MHz
90
kΩ
3V
0
2.2 V/3 V
25
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (1)
TA = 25°C, over recommended ranges of supply voltage (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
30
TEST CONDITIONS
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
APPLICATION INFORMATION
Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger
To ADC10
INCHx
ADC10AE0.y
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y
PxOUT.y
0
ACLK
1
DVSS
0
DVCC
1
1
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
Bus
Keeper
EN
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 14. Port P1 (P1.0 to P1.2) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
ADC10AE.x
(INCH.y = 1)
P1.0/
P1.x (I/O)
I: 0; O: 1
0
0
TA0CLK/
TA0.TACLK
0
1
0
ACLK
1
1
0
A0
A0
X
X
1 (y = 0)
P1.1/
P1.x (I/O)
I: 0; O: 1
0
0
TA0.0/
TA0.0
1
1
0
TA0.CCI0A
0
1
0
A1
X
X
1 (y = 1)
ACLK/
A1
0
1
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
31
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Table 14. Port P1 (P1.0 to P1.2) Pin Functions (continued)
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1.2/
P1.x (I/O)
TA0.1/
TA0.1
A2/
32
2
P1DIR.x
P1SEL.x
ADC10AE.x
(INCH.y = 1)
I: 0; O: 1
0
0
1
1
0
TA0.CCI1A
0
1
0
A2
X
X
1 (y = 2)
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger
SREF2
VSS
0
To ADC10 VREF-
1
To ADC10
INCHx = y
ADC10AE0.y
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y
PxOUT.y
0
ADC10CLK
1
DVSS
0
DVCC
1
1
Bus
Keeper
EN
P1.3/ADC10CLK/A3/VREF-/VEREF-
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 15. Port P1 (P1.3) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
ADC10AE.x
(INCH.x = 1)
0
P1.3/
P1.x (I/O)
I: 0; O: 1
0
ADC10CLK/
ADC10CLK
1
1
0
A3
X
X
1 (y = 3)
VREF-/
VREF-
X
X
1
VEREF-
VEREF-
X
X
1
A3/
3
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
33
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger
To ADC10 VREF+
To ADC10
INCHx = y
ADC10AE0.y
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y
PxOUT.y
0
SMCLK
1
DVSS
0
DV CC
1
1
Bus
Keeper
EN
P1.4/SMCLK/A4/VREF+/VEREF+/TCK
PxIN.y
To Module
PxIE.y
EN
PxIRQ.y
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
Table 16. Port P1 (P1.4) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
P1.4/
P1.x (I/O)
I: 0; O: 1
0
0
0
SMCLK/
SMCLK
1
1
0
0
A4
X
X
1 (y = 4)
0
VREF+
X
X
1
0
VEREF+/
VEREF+
X
X
1
0
TCK
TCK
X
X
0
1
A4/
VREF+/
34
4
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Port P1 Pin Schematic: P1.5, Input/Output With Schmitt Trigger
To ADC10
INCHx
ADC10AE0.y
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y
PxOUT.y
DVSS
0
DVCC
1
1
0
1
From Module
Bus
Keeper
EN
P1.5/TA0.0/A5/TMS
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
Table 17. Port P1 (P1.5) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
USIP.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
P1.5/
P1.x (I/O)
I: 0; O: 1
0
0
0
0
TA0.0/
TA0.0
1
1
0
0
0
A5/
A5
X
X
X
1 (y = 5)
0
SCLK/
5
SCLK
X
X
1
0
0
TMS
TMS
X
X
0
0
1
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
35
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Port P1 Pin Schematic: P1.6, Input/Output With Schmitt Trigger
To ADC10
INCHx
ADC10AE0.y
USIPE6
PxDIR.y
1
from USI
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y or
USIP E6
PxOUT.y
DVSS
0
DV CC
1
1
0
1
From USI
Bus
Keeper
EN
P1.6/TA0.1/SDO/SCL/A6/TDI
PxSEL.y
PxIN.y
To Module
PxIE.y
EN
PxIRQ.y
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
USI in I2C mode: Output driver drives low level only. Driver is disabled in JTAG mode.
Table 18. Port P1 (P1.6) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
USIP.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
I: 0; O: 1
0
0
0
0
P1.6/
P1.x (I/O)
TA0.1/
TA0.1
1
1
0
0
0
TA0.CCR1B
0
1
0
0
0
A6
X
X
0
1 (y = 6)
0
SDO/
SDO
X
X
1
0
0
TDI/TCLK
TDI/TCLK
X
X
0
0
1
6
A6/
36
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger
To ADC10
INCHx
ADC10AE0.y
USIPE7
PxDIR.y
1
Direction
0: Input
1: Output
0
from USI
PxSEL.y
PxREN.y
PxSEL.y or
USIPE7
PxOUT.y
0
From USI
1
DVSS
0
DVCC
1
1
Bus
Keeper
EN
P1.7/SDI/SDA/A7/TDO/TDI
PxSEL.y
PxIN.y
To Module
PxIE.y
EN
PxIRQ.y
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
From JTAG
To JTAG
USI in I2C mode: Output driver drives low level only. Driver is disabled in JTAG mode.
Table 19. Port P1 (P1.7) Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
USIP.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
P1.7/
P1.x (I/O)
I: 0; O: 1
0
0
0
0
A7/
A7
X
X
0
1 (y = 7)
0
SDI/SDO
X
X
1
0
0
TDO/TDI
X
X
0
0
1
SDI/SDO
TDO/TDI
7
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
37
MSP430G2231-EP
SLAS862 – JUNE 2012
www.ti.com
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger
XOUT/P2.7
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
1
PxSEL.6
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
PxSEL.6
PxOUT.y
0
from Module
1
DV SS
0
DV CC
1
1
Bus
Keeper
EN
XIN/P2.6/TA0.1
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
Table 20. Port P2 (P2.6) Pin Functions
PIN NAME (P2.x)
x
XIN
FUNCTION
XIN
P2.6
TA0.1
6
P2.x (I/O)
TA0.1 (1)
(1)
BCSCTL3.LFXT1Sx = 11 is required.
38
Submit Documentation Feedback
CONTROL BITS / SIGNALS
P2DIR.x
P2SEL.6
P2SEL.7
0
1
1
I: 0; O: 1
0
X
1
1
X
Copyright © 2012, Texas Instruments Incorporated
MSP430G2231-EP
www.ti.com
SLAS862 – JUNE 2012
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
XIN/P2.6/TA0.1
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
PxDIR.y
from P2.6/XIN
1
PxSEL.7
1
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.7
PxOUT.y
0
from Module
1
DVSS
0
DV CC
1
1
Bus
Keeper
EN
XOUT/P2.7
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 21. Port P2 (P2.7) Pin Functions
PIN NAME (P2.x)
XOUT
P2.7
x
7
FUNCTION
XOUT
P2.x (I/O)
Copyright © 2012, Texas Instruments Incorporated
CONTROL BITS / SIGNALS
P2DIR.x
P2SEL.6
P2SEL.7
1
1
1
I: 0; O: 1
X
0
Submit Documentation Feedback
39
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
MSP430G2231QPW1EP
ACTIVE
TSSOP
PW
14
90
TBD
Call TI
Call TI
MSP430G2231QPW1REP
PREVIEW
TSSOP
PW
14
2000
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF MSP430G2231-EP :
• Catalog: MSP430G2231
• Automotive: MSP430G2231-Q1
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2012
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated