HYNIX HMP112V7EFR8C-S6

240pin DDR2 VLP Registerd DIMMs based on 1Gb E version
This Hynix DDR2 VLP (Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 1Gb E version DDR2 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb E version based VLP Registered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of
industry standard. It is suitable for easy interchange and addition.
ORDERING INFORMATION
Density
Org.
# of
DRAMs
# of
Ranks
Materials
Parity
Support
HMP112V7EFR8C-C4/Y5/S6
1GB
128Mbx72
9
1
Halogen Free
O
HMP125V7EFR4C-C4/Y5/S6
2GB
256Mbx72
18
1
Halogen Free
O
HMP351V7EMR4C-C4/Y5/S6
4GB
512Mbx72
36
2
Halogen Free
O
Part Name
SPEED GRADE & KEY PARAMETERS
C4 (DDR2-533)
Y5 (DDR2-667)
S6 (DDR2-800)
Unit
Speed@CL3
400
400
-
Mbps
Speed@CL4
533
533
400
Mbps
Speed@CL5
-
667
533
Mbps
Speed@CL6
-
-
800
Mbps
CL-tRCD-tRP
4-4-4
5-5-5
6-6-6
tCK
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3 / Sep. 2008
1
1240pin DDR2 VLP Registered DIMMs
FEATURES
•
JEDEC standard 1.8V +/- 0.1V Power Supply
•
VDDQ: 1.8V +/- 0.1V
•
All inputs and outputs are compatible with SSTL_1.8 interface
•
4 Bank architecture
•
Posted CAS
•
Programmable CAS Latency 3, 4, 5
•
OCD (Off-Chip Driver Impedance Adjustment)
•
ODT (On-Die Termination)
•
Fully differential clock operations (CK & CK)
•
Programmable Burst Length 4 / 8 with both sequential and interleave mode
•
Average Auto Refresh Period 7.8us under TCASE 85℃, 3.9us at 85℃ < TCASE ≤ 95 ℃
•
High Temperature Self-Refresh Entry enable features
•
PASR (Partial Array Self- Refresh)
•
8192 refresh cycles / 64ms
•
Serial presence detect with EEPROM
•
DDR2 SDRAM Package: 60ball FBGA
•
133.35 x 18.29 mm form factor
•
Lead-free Products are RoHS compliant
ADDRESS TABLE
Density
Organization Ranks
SDRAMs
# of
DRAMs
# of row/bank/column Address
Refresh
Method
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
8K / 64ms
1GB
128Mb x 72
1
128Mb x 8
9
2GB
256Mb x 72
1
256Mb x 4
18
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
4GB
512Mb x 72
2
256Mb x 4
36
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64m
Rev. 0.3 / Sep. 2008
1240pin DDR2 VLP Registered DIMMs
Input/Output Functional Description
Symbol
Type
Polarity
Pin Description
CK0
IN
Positive
Edge
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CK0
IN
Negative
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Edge
CKE[1:0]
IN
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
S[1:0]
IN
Active
Low
Enables the associated DDR2 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
ODT[1:0]
IN
Active
High
On-Die Termination signals.
RAS, CAS, WE
IN
Active
Low
When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define
the command being entered.
Vref
Supply
Reference voltage for SSTL18 inputs
VDDQ
Supply
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all
current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
BA[1:0]
IN
-
Selects which DDR2 SDRAM internal bank of four is activated.
During a Bank Activate command cycle, Address input defines the row address(RA0~RA13)
A[9:0],
A10/AP
A[13:11]
IN
-
DQ[63:0],
CB[7:0]
IN
-
DM[8:0]
IN
Active
High
VDD,VSS
Supply
During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged.
If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define
which bank to precharge.
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are
tied to VDD/VDDQ planes on these modules.
DQS[17:0]
I/O
Positive
Edge
DQS[17:0]
I/O
Negative
Negative line of the differential data strobe for input and output data
Edge
SA[2:0]
IN
-
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD
EEPROM address range.
SDA
I/O
-
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may
be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up.
SCL
IN
-
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from SCL to VDDSPD to act as a pull up on the system board.
VDDSPD
Supply
Positive line of the differential data strobe for input and output data
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane.
EEPROM supply is operable from 1.7V to 3.6V.
RESET
IN
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When
low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will
be set to low level (the PLL will remain synchronized with the input clock)
Par_In
IN
Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
Err_Out
OUT
TEST
Rev. 0.3 / Sep. 2008
Parity error found in the Address and Control bus
Used by memory bus analysis tools (unused on memory DIMMs)
1240pin DDR2 VLP Registered DIMMs
PIN DESCRIPTION
Pin
Pin Description
Pin
CK0
Clock Input, positive line
ODT[1:0]
CK0
Clock input, negative line
VDDQ
CKE0~CKE1 Clock Enable Input
Pin Description
On Die Termination Inputs
DQs Power Supply
DQ0~DQ63 Data Input/Output
RAS
Row Address Strobe
CB0~CB7
Data check bits Input/Output
CAS
Column Address Strobe
DQS(0~8)
Data strobes
WE
Write Enable
DQS(0~8)
Data strobes, negative line
Chip Select Input
DM(0~8),
Data Maskes/Data strobes
DQS(9~17)
Address input
DQS(9~17) Data strobes, negative line
S0,S1
A0~A9,
A11~A13
A10/AP
Address input/Autoprecharge
RFU
Reserved for Future Use
BA0,BA1
SDRAM Bank Address
NC
No Connect
SCL
Serial Presence Detect (SPD) Clock Input
TEST
Memory bus test tool
(Not Connected and Not Usable on DIMMs)
SDA
SPD Data Input/Output
VDD
Core Power
VDDQ
I/O Power
SA0~SA2
2
E PROM Address Inputs
Par_In
Parity bit for the Address and Control bus
VSS
Ground
Err_Out
Parity error found on the Address
VREF
Input/Output Reference
RESET
Reset Enable
CB0~CB7
VDDSPD
SPD Power
Data Check bit Inputs/Outputs
PIN LOCATION
Front Side
1 pin
121 pin
Rev. 0.3 / Sep. 2008
Back Side
64 pin
65 pin
184 pin
185 pin
120 pin
240 pin
1240pin DDR2 VLP Registered DIMMs
PIN ASSIGNMENT
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
1
VREF
41
VSS
81
DQ33
121
VSS
161
CB4
201
Name
VSS
2
VSS
42
CB0
82
VSS
122
DQ4
162
CB5
202
DM4/DQS13
3
DQ0
43
CB1
83
DQS4
123
DQ5
163
VSS
203
DQS13
4
DQ1
44
VSS
84
DQS4
124
VSS
164
DM8,DQS17
204
VSS
5
VSS
45
DQS8
85
VSS
125
DM0/DQS9
165
DQS17
205
DQ38
6
DQS0
46
DQS8
86
DQ34
126
DQS9
166
VSS
206
DQ39
7
DQS0
47
VSS
87
DQ35
127
VSS
167
CB6
207
VSS
8
VSS
48
CB2
88
VSS
128
DQ6
168
CB7
208
DQ44
9
DQ2
49
CB3
89
DQ40
129
DQ7
169
VSS
209
DQ45
10
DQ3
50
VSS
90
DQ41
130
VSS
170
VDDQ
210
VSS
11
VSS
51
VDDQ
91
VSS
131
DQ12
171
NC,CKE1
211
DM5/DQS14
DQS14
12
DQ8
52
CKE0
92
DQS5
132
DQ13
172
VDD
212
13
DQ9
53
VDD
93
DQS5
133
VSS
173
A15,NC
213
VSS
14
VSS
54
BA2,NC
94
VSS
134
DM1/DQS10
174
A14,NC
214
DQ46
15
DQS1
55
NC, Err_Out
95
DQ42
135
DQS10
175
VDDQ
215
DQ47
16
DQS1
56
VDDQ
96
DQ43
136
VSS
176
A12
216
VSS
17
VSS
57
A11
97
VSS
137
RFU
177
A9
217
DQ52
18
RESET
58
A7
98
DQ48
138
RFU
178
VDD
218
DQ53
19
NC
59
VDD
99
DQ49
139
VSS
179
A8
219
VSS
20
VSS
60
A5
100
VSS
140
DQ14
180
A6
220
RFU
21
DQ10
61
A4
101
SA2
141
DQ15
181
VDDQ
221
RFU
22
DQ11
62
VDDQ
102
NC(TEST)
142
VSS
182
A3
222
VSS
23
VSS
63
A2
103
VSS
143
DQ20
183
A1
223
DM6/DQS15
64
184
VDD
224
NC,DQS15
104
DQS6
144
DQ21
105
DQS6
145
VSS
VSS
106
VSS
146
DM2/DQS11
185
VSS
107
DQ50
147
DQS11
VDD
108
DQ51
148
NC, Err_Out
109
VSS
149
VDD
110
DQ56
150
A10/AP
111
DQ57
151
112
VSS
113
DQS7
WE
114
CAS
115
24
DQ16
25
DQ17
VDD
26
VSS
65
27
DQS2
66
28
DQS2
67
29
VSS
68
30
DQ18
69
31
DQ19
70
32
VSS
71
BA0
33
DQ24
72
VDDQ
34
DQ25
73
35
VSS
74
Key
Key
225
VSS
CK0
226
DQ54
186
CK0
227
DQ55
VSS
187
VDD
228
VSS
DQ22
188
A0
229
DQ60
DQ23
189
VDD
230
DQ61
VSS
190
BA1
231
VSS
152
DQ28
191
VDDQ
232
DM7/DQS16
153
DQ29
192
RAS
233
NC,DQS16
DQS7
154
VSS
193
S0
234
VSS
VSS
155
DM3/DQS12
194
VDDQ
235
DQ62
DQ63
36
DQS3
75
VDDQ
116
DQ58
156
DQS12
195
ODT0
236
37
DQS3
76
NC, S1
117
DQ59
157
VSS
196
A13,NC
237
VSS
38
VSS
77
NC, ODT1
118
VSS
158
DQ30
197
VDD
238
VDDSPD
39
DQ26
78
VDDQ
119
SDA
159
DQ31
198
VSS
239
SA0
40
DQ27
79
VSS
120
SCL
160
VSS
199
DQ36
240
SA1
80
DQ32
200
DQ37
NC= No Connect, RFU= Reserved for Future Use.
Note:
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity.
3. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules
(DIMMs)
Rev. 0.3 / Sep. 2008
1240pin DDR2 VLP Registered DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx72): HMP112V7EFR8C
DQS0
DQS0
DM0,DQS9
DQS9
RS0
DQS4
DQS4
DM4,DQS13
DQS13
DM/ NU/ /CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
/DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS1
DQS1
DM1,DQS10
DQS10
DQS
/DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
DQS2
DQS2
DM2,DQS11
DQS11
DQS
/DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQS3
DQS3
DM3,DQS12
DQS12
DQS
/DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
DQS
/DQS
D5
DM/ NU/ /CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM/ NU/ /CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
BA0- BA2**
A0- A15**
RAS
CAS
WE
CKE0
ODT0
DQS
D0-D8
VREF
D0–D8
VSS
D0–D8
/DQS
Serial PD
SCL
DM/ NU/ /CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
SDA
WP A0 A1 A2
/DQS
SA0 SA1 SA2
D7
/DQS
Signals for Address and Command Parity Function (Raw Card F, F and AC)
1:1
R
E
G
I
S
T
E
R
/RS0 to /CS-> /CS: SDRAMs D0-D8
Rev. 0.3 / Sep. 2008
C0
C1
RBA0 to RBA2->BA0-BA2: SDRAMs D0-D8***
/RRAS-> /RAS: SDRAMs D0-D8
CK0
/RCAS ->/CAS: SDRAMs D0-D8
CK0
/RWE ->/WE: SDRAMs D0-D8
RCKE0-> CKE0: SDRAMs D0-D8
/PCK7
RESET
Register
PAR_IN
PRO
QERR
Err_Out
The resistors on Par_In, A13, A14, A15, BA2 and the
signal line of Err_Out refer to the section:
“Register Options for unused Address inputs”
/RA0-RA15->A0-A15: SDRAMs D0- D8***
RST
PCK7
Vss
Vss
PAR_IN
100K ohms
RODT0-> ODT0: SDRAMs D0-D8
/RESET
Serial PD
D6
D8
S0*
VDD SPD
VDD/VDDQ
Note:
1.DQ-to-I/O wiring may be changed within a byte.
2.Unless otherwise noted, resistor values are 22 Ohms +/-5%.
DQS8
DQS8
DM8,DQS17
DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM/ NU/ /CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQS7
/DQS7
DM7,DQS16
DQS16
DM/ NU/ /CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/DQS
DQS6
DQS6
DM6,DQS15
DQS15
DM/ NU/ /CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS
DQS5
DQS5
DM5,DQS14
DQS14
DM/ NU/ /CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/ NU/ /CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
P
L
L
OE
PCK0-PCK6, PCK8, PKC9 → CK: SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 → CK: SDRAMs D0-D8
PCK7 → CK: Register
PCK7 → CK: Register
* S0 connects to DCS and VDD connects to CSR on the register. S1, CKE1 and ODT1 are NC
** A13-15, BA2 have the optional pull down resistors(100K ohms), which is not indicated here.
*** For Raw Card R and A Co, post register A14, A15 and BA2 are not connected to the SDRAMs.
And for Raw Card AC1, post register A14 and A15 are not connected to the SDRAMs.
1240pin DDR2 VLP Registered DIMMs
FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx72): HMP125V7EFR4C
VSS
RS0
DQS0
DQS0
Serial PD
DQS9
DQS9
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ0
DQ1
DQ2
DQ3
CS
DQS
DQS
D0
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
SCL
DQS
SCL
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ8
DQ9
DQ10
DQ11
CS
DQS
DQS
D1
DQS2
DQS2
DQ12
DQ13
DQ14
DQ15
SA0 SA1 SA2
DQS
DQS
D10
VDD SPD
Serial PD
VDD/VDDQ
D0–D17
VREF
D0–D17
VSS
D0–D17
DQS11
DQS11
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ16
DQ17
DQ18
DQ19
CS
DQS
DQS
D2
DQS3
DQS3
DQ20
DQ21
DQ22
DQ23
DQS
DQS
D11
CK0
DQS12
DQS12
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
/CS
DQS
/DQS
D3
DQS4
DQS4
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
/CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
/DQS
RESET
D12
I/O
I/O
I/O
I/O
DM
0
1
2
3
CS
DQS
DQS
D4
DQS5
DQS5
DQ36
DQ37
DQ38
DQ39
DQS
I/O
I/O
I/O
I/O
DM
0
1
2
3
CS
DQS
DQS
D5
DQ44
DQ45
DQ46
DQ47
DM
0
1
2
3
CS
I/O
I/O
I/O
I/O
DM
0
1
2
3
CS
I/O
I/O
I/O
I/O
DM
0
1
2
3
CS
I/O
I/O
I/O
I/O
DM
0
1
2
3
CS
DQS
DQ48
DQ49
DQ50
DQ51
I/O
I/O
I/O
I/O
DM
0
1
2
3
CS
DQS
DQS
D6
DQS7
DQS7
DQ52
DQ53
DQ54
DQ55
DQS
D14
DQS
I/O
I/O
I/O
I/O
DM
0
1
2
3
CS
DQS
DQS
D7
DQS8
DQS8
DQ60
DQ61
DQ62
DQ63
DQS
D15
DQS
** RESET, PCK7 and PCK7 connects to both Registers.
Other signals connects to one of two Registers.
Raw Card V has only one register.
*** A13-A15, BA2 have the optional pull down resistors
(100K ohms), which is not indicated here.
DQS16
DQS16
DQ56
DQ57
DQ58
DQ59
PCK7 → CK: Register
* S0 connects to DCS or Register A and CSR of Register B.
CSR of Register A and DCS of Register B connects to VDD.
DQS15
DQS15
DQS6
DQS6
PCK7 → CK: Register
OE
DQS
D13
I/O
I/O
I/O
I/O
PCK0 - PCK6, PCK8, PCK9 → CK: SDRAMs D0-D17
Note:
1.DQ-to-I/O wiring may be changed within a byte.
2.Unless otherwise noted, resistor values are 22 Ohms +/-5%.
DQS14
DQS14
DQ40
DQ41
DQ42
DQ43
PCK0 - PCK6, PCK8, PKC9 → CK: SDRAMs D0-D17
P
L
L
CK0
DQS13
DQS13
DQ32
DQ33
DQ34
DQ35
SDA
WP A0 A1 A2
D9
DQS10
DQS10
DQS1
DQS1
SDA
DQS
D16
**** For /raw /card U0 and V, post register A14, A15 and BA2
are not connected to the SDRAMs.
And for Raw Care U1, post register A14 and A15 are not
connected to the SDRAMs.
The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out
refer to the section:
“Register Options for unused Address inputs”
DQS17
DQS17
CB0
CB1
CB2
CB3
I/O
I/O
I/O
I/O
S0*
BA0-BA2***
DM
0
1
2
3
1:2
R
E
G
I
S
T
E
R
A0-A15***
RAS
CAS
WE
CKE0
ODT0
RESET**
CS
DQS
D8
DQS
CB4
CB5
CB6
CB7
PCK7**
PCK7**
Rev. 0.3 / Sep. 2008
DQS
D17
RS0 -> CS: SDRAMs D0-D17
Signals for Address and Command Parity Function (Raw Card H, U)
RBA0-RBA2->BA0-BA2: SDRAMs D0-D17****
RA0- RA15->A0-A15: SDRAMs D0-D17****
RRAS-> RAS: SDRAMs D0-D177
RCAS ->CAS: SDRAMs D0-D17
RWE-> WE: SDRAMs D0-D17
ROKE0-> CKE: SDRAMs D0-D17
RODT0-> ODT0: SDRAMs D0-D17
RST
DQS
Vss
VDD
PAR_IN
100K ohms
C0
C1
PAR_IN
Register A
PRO
QERR
VDD
VDD
C0
Register B
C1
PAR_IN
PRO
QERR
Err_Out
For R/C U, 0 ohm resistor is placed at the end of Err_Out just before the edge connector and is
not populated for the non-parity card.
1240pin DDR2 VLP Registered DIMMs
FUNCTIONAL BLOCK DIAGRAM
4GB(256Mbx72): HMP351V7EMR4C
VSS
RS0
RS1
DQS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQS9
DQS9
DM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D18
DQS1
DQS1
DQ8
DQ9
DQ10
DQ11
DQS DQS
D1
DQS DQS
D19
DM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
D2
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D20
DM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
D3
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D21
DM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
D8
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D26
DM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
D4
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D22
DM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
D5
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D23
S0*
S1*
BA0-BA2***
A0-A15***
RAS
CAS
WE
CKE0
CKE
ODT0
ODT1
RESET**
PCK7**
PCK7**
CS
D27
SCL
SCL
DQ12
DQ13
DQ14
DQ15
WP A0
DQS DQS
D10
DQS DQS
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D11
DQ28
DQ29
DQ30
DQ31
DQS DQS
D12
CB4
CB5
CB6
CB7
DQS DQS
D17
SDA
SDA
A1
A2
SA0 SA1 SA2
D28
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
VDD SPD
Serial PD
VDD/VDDQ
D0–D35
VREF
D0–D35
VSS
D0–D35
DQS DQS
D29
DQS DQS
D30
CK0
CK0
DQS DQS
RESET
P
L
L
OE
PCK0 to PCK6, PCK8, PKC9
→ CK: SDRAMs D0-D35
PCK0 to PCK6, PCK8, PCK9
→ CK: SDRAMs D0-D35
PCK7 → CK: Register
PCK7 → CK: Register
D35
DQ36
DQ37
DQ38
DQ39
DQS DQS
D13
DQS DQS
D31
DQ44
DQ45
DQ46
DQ47
DQS DQS
D14
DQS DQS
D32
DQS15
DQS15
DM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D24
DQS7
DQS7
DQ56
DQ57
DQ58
DQ59
DM
I/O 0
I/O 1
I/O 2
I/O 3
Serial PD
DQS DQS
DQS14
DQS14
DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
CS
DQS13
DQS13
DQS5
DQS5
DQ40
DQ41
DQ42
DQ43
CS
D9
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS17
DQS17
RS0
RS1
DQS4
DQS4
DQ32
DQ33
DQ34
DQ35
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
DQS12
DQS12
DQS8
DQS8
CB0
CB1
CB2
CB3
CS
DQS11
DQS11
DQS3
DQS3
DQ24
DQ25
DQ26
DQ27
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS10
DQS10
DM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ4
DQ5
DQ6
DQ7
DQ52
DQ53
DQ54
DQ55
DQS DQS
D15
DQS DQS
D33
DQS16
DQS16
DM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
D7
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D25
DQ60
DQ61
DQ62
DQ63
DQS DQS
D16
DQS DQS
D34
The resistors on Par_In, A13, A14, A15, BA2
and signal line of Err_Out refer to the section:
“Register Options for Unused Address inputs”
Signals for Address and Command Parity Function
1:2
R
E
G
I
S
T
E
R
RST
Rev. 0.3 / Sep. 2008
RS0 -> CS: SDRAMs D0-D17
Register 1
Register 2
RS1 -> CS: SDRAMs D18-D35
Vss
VDD
C1
C1
RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D35
VSS
VDD
C2
C2
RA0-RA15 -> A0-A15: SDRAMs D0-D35****
PRO1
PARIN1
PARIN1
PTYERR1
PAR_IN
RRAS -> RAS: SDRAMs D0-D35
PARIN2
PARIN2
PTYERR2
PRO2
100K ohms
RCAS -> CAS: SDRAMs D0-D35
Register 1 share a part of Addr/Cmd input signal set.
RWE -> WE: SDRAMs D0-D35
Register 2 share the other part of Addr/Cmd input signal set.
RCKE0 -> CKE: SDRAMs D0-D17
0 Ohm resistor on Err_Out is not populated for non-parity card.
RCKE1 -> CKE: SDRAMs D18-D35
Notes:
RODT0 -> ODT0: SDRAMs D0-D17
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 22 ohms +/-5%.
RODT1 -> ODT1: SDRAMs D18-D35
0 ohm
3. RS0 and RS1 altemate between the bottom and surface sides of the DIMM.
* S0 connects to DCS and S1 connects to CSR on Register1. S1 connects to DCS and S0 connects to CSR on Register 2.
** RESET, PCK7 and PCK7 connect to both Registers. Other signals connect to one of two Registers.
*** A13-15, BA2 have the optional pull down resistors(100K ohms), which is not indicated here.
**** For Raw Card AJ, post register A14, A15 are not connected to the SDRAMs.
Err_Out
1240pin DDR2 VLP Registered DIMMs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Note
VDD
- 1.0 V ~ 2.3 V
V
1
Voltage on VDDL pin relative to Vss
VDDL
-0.5V ~ 2.3 V
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
- 0.5 V ~ 2.3 V
V
1
VIN, VOUT
- 0.5 V ~ 2.3 V
V
1
Storage Temperature
TSTG
-50 ~ +100
Storage Humidity (without condensation)
HSTG
5 to 95
Voltage on VDD pin relative to Vss
Voltage on any pin relative to Vss
C
1
%
1
o
Note:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con
ditions for extended periods may affect reliablility.
OPERATING CONDITIONS
Parameter
Symbol
Rating
Units
DIMM Operating temperature (ambient)
TOPR
0 ~ +55
oC
DIMM Barometric Pressure (operating & storage)
PBAR
105 to 69
K Pascal
DRAM Component Case Temperature Range
TCASE
0 ~+95
o
C
Notes
1
2
Note:
1. Up to 9850 ft.
2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to
tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter
Min
Max
Unit
VDD
1.7
1.9
V
VDDL
1.7
1.9
V
VDDQ
1.7
1.9
V
1
Input Reference Voltage
VREF
0.49 x VDDQ
0.51 x VDDQ
V
2
EEPROM Supply Voltage
VDDSPD
1.7
3.6
V
Termination Voltage
VTT
VREF-0.04
VREF+0.04
V
Power Supply Voltage
Symbol
Note:
1.
2.
3.
VDDQ must be less than or equal to VDD.
Peak to peak ac noise on VREF may not exceed +/-2% VREF(dc)
VTT of transmitting device must track VREF of receiving device.
Rev. 0.3 / Sep. 2008
Note
3
1240pin DDR2 VLP Registered DIMMs
INPUT DC LOGIC LEVEL
Parameter
Symbol
Min
Max
Unit
Input High Voltage
VIH(DC)
VREF + 0.125
VDDQ + 0.3
V
Input Low Voltage
VIL(DC)
-0.30
VREF - 0.125
V
Notes
INPUT AC LOGIC LEVEL
Parameter
DDR2 400/533
Symbol
DDR2 667/800
Min
Max
Min
Max
Notes
Unit
AC Input logic High
VIH(AC)
VREF + 0.250
-
VREF + 0.200
-
V
AC Input logic Low
VIL(AC)
-
VREF - 0.250
-
VREF - 0.200
V
AC INPUT TEST CONDITIONS
Symbol
Condition
Value
Units
Notes
0.5 * VDDQ
V
1
VREF
Input reference voltage
VSWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
Notes:
1.
Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2.
The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges
and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3.
AC timings are referenced with input waveforms switching from VIL (ac) to VIH (ac) on the positive transitions
and VIH (ac) to VIL (ac) on the negative transitions.
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSWING(MAX)
VSS
delta TF
Falling Slew =
delta TR
VREF - VIL(ac) max
delta TF
Rising Slew =
< Figure: AC Input Test Signal Waveform>
Rev. 0.3 / Sep. 2008
VIH(ac)min - VREF
delta TR
1240pin DDR2 VLP Registered DIMMs
Differential Input AC logic Level
Symbol
Parameter
Min.
Max.
Units
Note
VID (ac)
ac differential input voltage
0.5
VDDQ + 0.6
V
1
VIX (ac)
ac differential cross point voltage
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as
CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC).
VDDQ
VTR
Crossing point
VID
VIX or VOX
VCP
VSSQ
< Differential signal levels >
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to
track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross.
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol
Parameter
Min.
Max.
Units
Note
VOX (ac)
ac differential cross point voltage
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
Note:
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to
track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross.
Rev. 0.3 / Sep. 2008
1240pin DDR2 VLP Registered DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Symbol
Parameter
SSTL_18
Units
Notes
VOTR
Output Timing Measurement Reference Level
0.5 * VDDQ
V
1
Notes:
1. The VDDQ of the device under test is referenced.
OUTPUT DC CURRENT DRIVE
Symbol
Parameter
SSTl_18
Units
Notes
IOH(dc)
Output Minimum Source DC Current
- 13.4
mA
1, 3, 4
IOL(dc)
Output Minimum Sink DC Current
13.4
mA
2, 3, 4
Notes:
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and
VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device
drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an
SSTL_18 receiver.
The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define
a convenient driver current for measurement.
Rev. 0.3 / Sep. 2008
1240pin DDR2 VLP Registered DIMMs
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz)
1GB: HMP112V7EFR8C
Pin
Symbol
Min
Max
Unit
CK0, CK0
CCK
7
11
pF
CKE, ODT
CI1
8
12
pF
CS
CI2
8
12
pF
Address, RAS, CAS, WE
CI3
8
12
pF
DQ, DM, DQS, DQS
CIO
6
9
pF
Symbol
Min
Max
Unit
CK0, CK0
CCK
7
11
pF
CKE, ODT
CI1
8
12
pF
CS
CI2
10
15
pF
Address, RAS, CAS, WE
CI3
8
12
pF
DQ, DM, DQS, DQS
CIO
6
9
pF
Symbol
Min
Max
Unit
CK0, CK0
CCK
9.5
10.5
pF
CKE, ODT
CI1
10.5
16
pF
CS
CI2
10.5
16
pF
Address, RAS, CAS, WE
CI3
10.5
16
pF
DQ, DM, DQS, DQS
CIO
17
21
pF
2GB: HMP125V7EFR4C
Pin
4GB: HMP351V7EMR4C
Pin
Note:
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Rev. 0.3 / Sep. 2008
1240pin DDR2 VLP Registered DIMMs
IDD SPECIFICATIONS (TCASE: 0 to 95oC)
1GB, 128M x 72 VLP Registered DIMM: HMP112V7EFR8C
Symbol
C4 (533@CL4)
Y5 (667@CL5)
S6 (800@CL6)
Unit
IDD0
1235
1280
1325
mA
IDD1
1325
1370
1415
mA
IDD2P
740
740
740
mA
IDD2Q
893
920
938
mA
IDD2N
965
1010
1055
mA
IDD3P-F
875
875
875
mA
IDD3P-S
758
758
758
mA
IDD3N
1055
1100
1145
mA
IDD4W
1730
1955
2180
mA
IDD4R
1730
1910
2090
mA
IDD5
2090
2135
2180
mA
IDD6
540
540
540
mA
IDD7
2225
2405
2720
mA
Notes
1
2GB, 256M x 72 VLP Registered DIMM: HMP125V7EFR4C
Symbol
C4 (533@CL4)
Y5 (667@CL5)
S6 (800@CL6)
Unit
IDD0
1820
1910
2000
mA
IDD1
2000
2090
2180
mA
IDD2P
830
830
830
mA
IDD2Q
1136
1190
1226
mA
IDD2N
1280
1370
1460
mA
IDD3P-F
1100
1100
1100
mA
IDD3P-S
866
866
866
mA
IDD3N
1460
1550
1640
mA
IDD4W
2810
3260
3710
mA
IDD4R
2810
3170
3530
mA
IDD5
3330
3420
3510
mA
IDD6
630
630
630
mA
IDD7
3800
4160
4790
mA
Notes:
1. IDD6 current values are guaranteed up to Tcase of 85oC max.
Rev. 0.3 / Sep. 2008
Notes
1
1240pin DDR2 VLP Registered DIMMs
4GB, 256M x 72 VLP Registered DIMM: HMP351V7EMR4C
Symbol
C4 (533@CL4)
Y5 (667@CL5)
S6 (800@CL6)
Unit
IDD0
2450
2630
2810
mA
IDD1
2630
2810
2990
mA
IDD2P
1010
1010
1010
mA
IDD2Q
1622
1730
1802
mA
IDD2N
1910
2090
2270
mA
IDD3P-F
1550
1550
1550
mA
IDD3P-S
1082
1082
1082
mA
IDD3N
2270
2450
2630
mA
IDD4W
3440
3980
4520
mA
IDD4R
3440
3890
4340
mA
IDD5
3960
4140
4320
mA
IDD6
810
810
810
mA
IDD7
4430
4880
5600
mA
Notes:
1. IDD6 current values are guaranteed up to Tcase of 85oC max.
Rev. 0.3 / Sep. 2008
Notes
1
1240pin DDR2 VLP Registered DIMMs
IDD Measurement Conditions
Symbol
Conditions
Units
IDD0
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin (IDD);
CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA
IDD1
Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK =
tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin (IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
mA
IDD2P
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2Q
Precharge quiet standby current; All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2N
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD3P
Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Fast PDN Exit MRS(12) = 0
Other control and address bus inputs are STABLE; Data bus inputs are FLOATSlow PDN Exit MRS(12) = 1
ING
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP =tRP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
mA
IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK
= tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD4R
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
AL = 0; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
mA
IDD5B
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA
IDD6
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data
bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85℃ max.
mA
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDD4R; - Refer to the following page for detailed timing conditions
mA
mA
mA
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with
all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC (max)
HIGH is defined as Vin ≥ VIHAC (min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
Rev. 0.3 / Sep. 2008
1240pin DDR2 VLP Registered DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
DDR2-800(S6)
DDR2-667(Y5)
DDR2-533 (C4)
DDR2-400 (E3)
Unit
Bin (CL-tRCD-tRP)
6-6-6
5-5-5
4-4-4
3-3-3
Parameter
min
min
min
min
CAS Latency
6
5
4
3
ns
tRCD
15
15
15
15
ns
tRP
15
15
15
15
ns
tRC
60
60
60
55
ns
tRAS
45
45
45
40
ns
AC Timing Parameters by Speed Grade
DDR2-400
Parameter
DDR2-533
Symbol
Unit Note
Min
Max
Min
Max
Data-Out edge to Clock edge Skew
tAC
-600
600
-500
500
ps
DQS-Out edge to Clock edge Skew
tDQSCK
-500
500
-500
450
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
CK
Clock Half Period
tHP
min
(tCL, tCH)
-
min
(tCL, tCH)
-
ns
System Clock Cycle Time
tCK
5000
8000
3750
8000
ps
DQ and DM input setup time
tDS
150
-
100
-
ps
1
DQ and DM input hold time
tDH
275
-
225
-
ps
1
Control & Address input Pulse Width for each input
tIPW
0.6
-
0.6
-
tCK
tDIPW
0.35
-
0.35
-
tCK
tHZ
-
tAC max
-
tAC max
ps
DQ and DM input pulse width for each input pulse width
for each input
Data-out high-impedance window from CK, /CK
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
ps
DQ low-impedance time from CK/CK
tLZ(DQ)
2*tAC min
tAC max
2*tAC min
tAC max
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
-
350
-
300
ps
tQHS
-
450
-
400
ps
DQ hold skew factor
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
ps
Write command to first DQS latching transition
tDQSS
WL - 0.25
WL + 0.25
WL - 0.25
WL + 0.25
tCK
DQS input high pulse width
tDQSH
0.35
-
0.35
-
tCK
DQS input low pulse width
tDQSL
0.35
-
0.35
-
tCK
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
tCK
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
tCK
Mode register set command cycle time
tMRD
2
-
2
-
tCK
Write preamble
tWPRE
0.35
-
0.35
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Rev. 0.3 / Sep. 2008
1240pin DDR2 VLP Registered DIMMs
- continued DDR2-400
Parameter
Address and control input setup time
Address and control input hold time
DDR2-533
Symbol
Unit Note
Min
Max
Min
Max
tIS
350
-
250
-
ps
tIH
475
-
375
-
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Auto-Refresh to Active/Auto-Refresh command period
tRFC
127.5
-
127.5
-
ns
Row Active to Row Active Delay for 1KB page size
tRRD
7.5
-
7.5
-
ns
Row Active to Row Active Delay for 2KB page size
tRRD
10
-
10
-
ns
Four Activate Window for 1KB page size
tFAW
37.5
-
37.5
-
ns
Four Activate Window for 2KB page size
tFAW
50
-
50
-
ns
CAS to CAS command delay
tCCD
2
2
tCK
Write recovery time
tWR
15
-
15
-
ns
Auto Precharge Write Recovery + Precharge Time
tDAL
tWR + tRP
-
tWR + tRP
-
tCK
Write to Read Command Delay
tWTR
10
-
7.5
-
ns
Internal read to precharge command delay
tRTP
7.5
Exit self refresh to a non-read command
tXSNR
tRFC + 10
Exit self refresh to a read command
tXSRD
200
-
200
-
tCK
-
2
-
tCK
Exit precharge power down to any non-read command
7.5
ns
tRFC + 10
ns
tXP
2
Exit active power down to read command
tXARD
2
2
tCK
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
6 - AL
tCK
tCKE
3
3
tCK
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
tAOND
2
2
2
2
tCK
tAON
tAC (min)
tAC(max)+1
tAC (min)
tAC(max)+1
ns
tAONPD
tAC(min)+2
2tCK+tAC(m
ax)+1
tAC(min)+2
2tCK+tAC(m
ax)+1
ns
tAOFD
2.5
2.5
2.5
2.5
tCK
tAOF
tAC (min)
tAC (max)+
0.6
tAC (min)
tAC (max)+
0.6
ns
tAOFPD
tAC (min)+2
2.5tCK+tAC(
max)+1
tAC(min)+2
2.5tCK+tAC(
max)+1
ns
ODT to power down entry latency
tANPD
3
3
tCK
ODT power down exit latency
tAXPD
8
8
tCK
OCD drive mode output delay
tOIT
0
tDelay
tIS + tCK + tIH
tREFI
-
7.8
-
7.8
us
2
tREFI
-
3.9
-
3.9
us
3
ODT turn-on
ODT turn-on (Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
Minimum time clocks remains ON after CKE
asynchronously drops LOW
Average periodic Refresh Interval
12
0
tIS + tCK + tIH
Note:
1. For details and notes, please refer to the relevant HYNIX component datasheet (H5PS1G[4,8]3EFR).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Rev. 0.3 / Sep. 2008
12
ns
ns
1240pin DDR2 VLP Registered DIMMs
Parameter
Symbol
DDR2-667
DDR2-800
min
max
min
max
Unit Note
DQ output access time from CK/CK
tAC
-450
+450
-400
+400
ps
DQS output access time from CK/CK
tDQSCK
-400
+400
-350
+350
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min(tCL,
tCH)
-
min(tCL,
tCH)
-
ps
Clock cycle time, CL=x
tCK
3000
8000
2500
tDS
100
-
50
-
ps
1
tDH
175
-
125
-
ps
1
Control & Address input pulse width for each
input
tIPW
0.6
-
0.6
-
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
-
0.35
-
tCK
Data-out high-impedance time from CK/CK
tHZ
-
tAC max
-
tAC max
ps
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
ps
DQ low-impedance time from CK/CK
tLZ(DQ)
2*tAC min
tAC max
2*tAC min
tAC max
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
-
240
-
200
ps
DQ hold skew factor
tQHS
-
340
-
300
ps
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
ps
First DQS latching transition to associated clock
edge
tDQSS
- 0.25
+ 0.25
- 0.25
+ 0.25
tCK
DQS input high pulse width
tDQSH
0.35
-
0.35
-
tCK
DQS input low pulse width
tDQSL
0.35
-
0.35
-
tCK
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
tCK
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
tCK
Mode register set command cycle time
tMRD
2
-
2
-
tCK
Write preamble
tWPRE
0.35
-
0.35
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Address and control input setup time
tIS
200
-
175
-
ps
Address and control input hold time
tIH
275
-
250
-
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Auto-Refresh to Active/Auto-Refresh command period
tRFC
127.5
-
127.5
-
ns
Active to active command period for 1KB page
size products
tRRD
7.5
-
7.5
-
ns
Active to active command period for 2KB page
size products
tRRD
10
-
10
-
ns
Four Active Window for 1KB page size products
tFAW
37.5
-
35
-
ns
Four Active Window for 2KB page size products
tFAW
50
-
45
-
ns
DQ and DM input setup time
(differential strobe)
DQ and DM input hold time
(differential strobe)
Rev. 0.3 / Sep. 2008
ps
1240pin DDR2 VLP Registered DIMMs
- continued Parameter
Symbol
DDR2-667
min
DDR2-800
max
min
max
CAS to CAS command delay
tCCD
2
Write recovery time
tWR
15
-
15
-
ns
Auto precharge write recovery + precharge time tDAL
2
Unit Note
tCK
WR+tRP
-
WR+tRP
-
tCK
Internal write to read command delay
tWTR
7.5
-
7.5
-
ns
Internal read to precharge command delay
tRTP
7.5
7.5
ns
tRFC +
10
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
Exit self refresh to a read command
tXSRD
200
-
200
-
tCK
Exit precharge power down to any non-read
command
tXP
2
-
2
-
tCK
Exit active power down to read command
tXARD
2
2
tCK
tXARDS
7 - AL
8 - AL
tCK
tCKE
3
3
tCK
tAOND
2
2
tAC (min)
tAC (max)
+0.7
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
tAON
ODT turn-on (Power-Down mode)
tAONPD
ODT turn-off delay
tAOFD
tAC(min)+2
2
2
tCK
tAC (min)
tAC (max)
+0.7
ns
2tCK+
tAC (min)
2tCK+
tAC(max)+1
+2
tAC(max)+1
2.5
2.5
ns
2.5
2.5
tCK
tAC (min)
tAC (max)
+0.6
ns
ODT turn-off
tAOF
tAC (min)
tAC (max)+
0.6
ODT turn-off (Power-Down mode)
tAOFPD
tAC (min)
+2
2.5tCK+
tAC (min)
2.5tCK+
tAC(max)+1
+2
tAC(max)+1
ns
ODT to power down entry latency
tANPD
3
3
tCK
ODT power down exit latency
tAXPD
8
OCD drive mode output delay
tOIT
0
Minimum time clocks remains ON after CKE
asynchronously drops LOW
Average periodic Refresh Interval
tDelay
8
12
tIS + tCK +
tIH
0
tIS + tCK
+ tIH
ns
ns
tREFI
-
7.8
-
7.8
us
2
tREFI
-
3.9
-
3.9
us
3
Note:
1. For details and notes, please refer to the relevant HYNIX component datasheet (H5PS1G[4,8]3EFR).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Rev. 0.3 / Sep. 2008
tCK
12
1240pin DDR2 VLP Registered DIMMs
PACKAGE OUTLINE
128Mx72 (1 rank) - HMP112V7EFR8C
Front
133.35
Detail A
63.0
5.175
18.29
PLL
Register
4.0 ± 0.1
Detail B
55.0
5.0
5.175
10.0
Back
Register
Detail of Contacts A
Side
Detail of Contacts B
4.00 max
0.8 ± 0.05
2.50 ± 0.20
3.80
0.20
2.50 ± 0.20
2.50
1.00
1.50 ± 0.10
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.3 / Sep. 2008
1.27 ± 0.10
max
1240pin DDR2 VLP Registered DIMMs
PACKAGE OUTLINE
256Mx72 (1 rank) - HMP125V7EFR4C
Front
133.35
Detail A
18.29
Detail B
63.0
5.175
PLL
Register
4.0 ± 0.1
55.0
5.0
5.175
Register
10.0
Back
Detail of Contacts A
4.00 max
0.8 ± 0.05
3.80
2.50 ± 0.20
2.50
2.50 ± 0.20
0.20
Side
Detail of Contacts B
1.00
1.50 ± 0.10
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.3 / Sep. 2008
1.27 ± 0.10
max
1240pin DDR2 VLP Registered DIMMs
PACKAGE OUTLINE
256Mx72 (2 rank) - HMP351V7EMR4C
Front
133.35
Detail A
63.0
5.175
18.29
PLL
Register
4.0 ± 0.1
Detail B
55.0
5.0
5.175
Register
10.0
Back
Side
Detail of Contacts A
Detail of Contacts B
0.8 ± 0.05
3.80
2.50 ± 0.20
2.50
2.50 ± 0.20
0.20
7.55 max
1.00
1.50 ± 0.10
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.3 / Sep. 2008
1.27 ± 0.10
max
1240pin DDR2 VLP Registered DIMMs
REVISION HISTORY
Revision
History
Date
0.1
Initial Release
Jul. 2008
0.2
Corrected typos and adjusted DIMM line-up
Aug. 2008
0.3
Editorial Correction
Sep. 2008
Rev. 0.3 / Sep. 2008
Remark