HYNIX HY5FS123235AFCP

HY5FS123235AFCP
512M (16Mx32) GDDR4 SDRAM
HY5FS123235AFCP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2/June. 2008
1
HY5FS123235AFCP
Revision History
Revision No.
History
Draft Date
Remark
0.0
Defined target spec.
Aug. 2006
Preliminary
0.1
Inserted AC timing and IDD value
Apr. 2007
Preliminary
1.0
1. Changed a marking method of tWL on page 57
2. Changed tWR from 24 to 20 on page 58.
3. Changed DLL on/off frequency to 2.5ns on page 57, page 59
(note 9) and page 60 (note 40).
5. Optimized IDD value and AC timing table on page 56, 57.
May. 2007
1.1
1. Revised typoes
May. 2007
1.2
1. Revised typoes on page 67
Jun. 2008
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
TABLE OF CONTENTS
FEATURES........................................................................................................................................................5
FEATURES..............................................................................................................................................5
FUNCTIONAL DESCRIPTION....................................................................................................................5
INITIALIZATION................................................................................................................................................6
REGISTER DEFINITION......................................................................................................................................8
MODE REGISTER.....................................................................................................................................8
EXTENDED MODE REGISTER..................................................................................................................12
EXTENDED MODE REGISTER2................................................................................................................15
EXTENDED MODE REGISTER3................................................................................................................16
COMMAND & ADDRESS.....................................................................................................................................17
Addressing.............................................................................................................................................17
Commands.............................................................................................................................................18
OPERATION.....................................................................................................................................................19
Deselect.................................................................................................................................................19
No Operation (NOP)................................................................................................................................19
MODE REGISTER SET..............................................................................................................................19
Activation...............................................................................................................................................19
Data Terminator Disable..........................................................................................................................20
Bank Restrictions....................................................................................................................................20
READ.....................................................................................................................................................21
READ and DLL Off Mode.........................................................................................................................24
WRITE...................................................................................................................................................25
PRECHARGE...........................................................................................................................................28
AUTO PRECHARGE.................................................................................................................................28
AUTO REFRESH.....................................................................................................................................28
SELF REFRESH.......................................................................................................................................29
Power Down..........................................................................................................................................31
READ and WRITE DBI............................................................................................................................36
CLOCKING, DATA CAPTURE....................................................................................................................41
Data Capture........................................................................................................................................41
Data Training.........................................................................................................................................42
Read Data Training Sequence.........................................................................................................42
Write Data Training Sequence........................................................................................................44
Changing Clock Frequency.....................................................................................................................46
DRIVER & TERMINATION..................................................................................................................................49
Programmable Impedance Output Buffer and Active Terminator...............................................................49
Impedance Control................................................................................................................................49
Data Terminator Disable........................................................................................................................50
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HY5FS123235AFCP
LPTERM...............................................................................................................................................51
OPERATING CONDITIONS..................................................................................................................................52
Absolute Maximum Ratings......................................................................................................................52
AC & DC Characteristics...........................................................................................................................53
1.5V I/O Driver Values.............................................................................................................................61
1.8V I/O Driver Values............................................................................................................................62
2.0V I/O Driver Values............................................................................................................................63
POD I/O SYSTEM..............................................................................................................................................64
PACKAGE SPECIFICATION.................................................................................................................................67
Ball-out..................................................................................................................................................67
Signals...................................................................................................................................................68
Mirror Function.......................................................................................................................................70
Package Dimensions...............................................................................................................................71
Vendor ID..............................................................................................................................................72
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
FEATURES
• Double-data rate architecture;
two data transfers per clock cycle
• Single ended READ strobe (RDQS) per byte
• Single ended WRITE strobe (WDQS) per byte
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge;
data and data mask referenced to both edges
of RDQS/WDQS
• Eight internal banks for concurrent operation
• Data mask (DM) for masking WRITE data
• Burst Length: 8 only
• Multiplexed addressing
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• On die termination (ODT)
• Calibrated output drive
• Programmable offset for both driver and termination
• POD_18 compatible inputs/outputs
• VDD and VDDQ: 1.8V +/- 5%, 2.0V +/- 5%
• CAS Latency : 7~22
FUNCTIONAL DESCRIPTION
The Hynix HY5FS123235AFCP is a high speed CMOS,
dynamic random access memory internally configured as
a eight bank DRAM.
These devices contain the following number of bits:
512M has 536,870,912 bits and eight banks
A single read or write access for the
Hynix HY5FS123235AFCP effectively consists of an 8N
data transfer every four clock-cycles at the inernal
DRAM core and eight corresponding n-bit wide, one-halfclock-cycle data transfers at the I/O pins.
Uni-directional data strobes are transmitted
externally, along with data, for use in data capture
at the receiver. RDQS is a strobe transmitted by the
GDDR4 SDRAM during READs. WDQS is the data strobe
sent by the memory controller during WRITEs.
RDQS is edge aligned with data for READs and WDQS is
center aligned with data for WRITEs.
The GDDR4 SDRAM operates from a differential clock
(CK and CK# the crossing of the CK going high and
CK# going low will be referred to as the positive edge
of CK). Commands (address and control signals)
are registered at the positive edge of CK.
Address is received on two consecutive rising edges of
CK. Input data is registered at both edges of WDQS,
and output data is referenced to both edges of RDQS,
as well as to both edges of CK.
Read and write accesses to the GDDR4 SDRAM are
burst oriented; accesses start at a selected location
and continue for a total of eight locations. Accesses begi
n with the registration of an ACTIVE command, which is
The Hynix HY5FS123235AFCP uses a double data rate
then followed by a READ or WRITE command.
architecture to achieve high speed operation.
The address bits registered coincident with the ACTIVE
The double data rate architecture is essentially an 8N
command are used to select the bank and the row to be
prefetch architecture with an interface designed to transfer accessed. The address bits registered coincident with the
two data words per clock cycle at the I/O pins.
READ or WRITE command are used to select the bank
and the starting column locaion for the burst access.
ORDERING INFORMATION
Part No.
HY5FS123235AFCP-06
HY5FS123235AFCP- 07
HY5FS123235AFCP- 08
HY5FS123235AFCP- 09
Power Supply
VDD/VDDQ = 2.0V
VDD/VDDQ = 1.8V
Clock Frequency
Max Data Rate
1.6GHz
3.2Gbps/pin
1.4GHz
2.8Gbps/pin
1.2GHz
2.4Gbps/pin
1.1GHz
2.2Gbps/pin
Interface
POD_18
Note: Above Hynix P/N’s and their homogeneous Subcomponents are RoHS(& Lead free) Compliant.
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
INITIALIZATION
GDDR4 SDRAMs must be powered up and initialized in a predefined manner as shown in Figure 1.
Operational procedures other than those specified may result in undefined operation.
The Mode Register and Extended Mode Registers do not have default values except EMR[A3:A2] and EMR3[A5].
If they are not programmed during the initialization sequence, it may lead to unspecified operation.
1
Apply Power to VDD
2
Apply power to VDDQ at same time or after power is applied to VDD
3
Apply VREF at same time or after power is applied to VDDQ
4
After power is stable, provide stable clock signals
5
Assert and hold RESET low
6
Wait a minimum of 200us
7
Set CKE# and A0 to the desired address & command on die termination settings,
then bring RESET High to latch in the logic state of CKE# and A0. Must be met
during this procedure. See Table 1 for the values and logic states for CKE# and A0
8
Bring CKE# low after tATH is satisfied
9
Wait at least 200us referenced from the beginning of tATS
10
Issue at least 2 NOP commands
11
Issue a PRECHARGE ALL command followed by NOP commands until tRP is satisfied
12
Issue MRS command to the mode register and the 3 extended mode registers in
any order. tMRD must be met during this procedure
13
Issue two AUTO REFRESH commands
14
After tRFC is satisfied from the second AUTO REFRESH command and tDL is
satisfied, the device is ready for operation
Figure 1: GDDR4 Initialization Sequence
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HY5FS123235AFCP
Table 1 Address and Control Termination Values
VALUE OHMS
CKE#
60
L
A0
H
120
H
H
240
H
L
RFU
L
L
VDD
VDDQ
VREF
T0
T1
T2
T3
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
Td0
Td1
Te0
Te1
Tf0
Tf1
Tg0
Tg1
RA
RA
ACT
NOP
CODE CODE CODE CODE CODE CODE CODE CODE
RA
RA
CODE CODE CODE CODE CODE CODE CODE CODE
RA
RA
BA
RA
CK#
CK
tCH tCL
RESET
tATS tATH
CKE#
tATS tATH
A0
CODE CODE CODE CODE CODE CODE CODE CODE
tIS tIH
CS#, RAS#,
CAS#, WE#
NOP
NOP
PRE
NOP MRS
NOP MRS NOP MRS NOP MRS
NOP
AR
NOP
AR
NOP
DM[0:3]
A9-A12
A2,A3,A7
ALL BANKS
A4
A8
tIS tIH
BA0,BA1,BA2
A1,A5,A6
BA0
=H
CODE
BA0
=L
CODE CODE CODE CODE CODE
High
RDQS[0:3]
High
WDQS[0:3]
High
DQ[0-31]
T=200us
Power-up:
VDD and
CK stable
T=200us
tRP
tMRD
tMRD
tMRD
Load Extended Load Extended Load Extended
Mode Register 3 Mode Register 2 Mode Register 1
tMRD
Load Mode
Register
tRFC
tRFC
tDL
DON’T CARE
Figure 2 : GDDR4 SDRAM Initialization
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HY5FS123235AFCP
REGISTER DEFINITION
MODE REGISTER (MR)
The Mode Register is used to define the specific mode of operation of the GDDR4 SDRAM. This includes the definition
of Write Latency, Write Recovery, DLL Reset, Test Mode and CAS latency as shown in Figure 3.
The Mode Register is programmed via the MODE REGISTER SET (MRS) command (with BA0=0, BA1=0 and BA2=0)
and will retain the stored information until it is reprogrammed or the device loses power (except bit A8, which is selfclearing).
Reprogramming the mode register will not alter the contents of the memory. The Mode Register must be loaded when
all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating
any subsequent operation. Violating either of these requirements will result in unspecified operation. Reserved states
should not be used, as unknown operation or incompatibility with future versions may result. RFU bits are reserved for
future use and must be programmed to 0.
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HY5FS123235AFCP
BA2
BA1
BA0
A12
0
0
0
RFU
A11
A10
A9
WL
A11
A10
A9
Write
Latency
0
0
0
RFU
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
A8
A7
DLL
TM
A6
A5
A4
A3
A2
A1
CAS Latency
A0
WR
A7
Test Mode
A2
A1
A0
WR
0
Normal
0
0
0
16
1
Test Mode
0
0
1
18
0
1
0
20
6
A8
DLL Rest
0
1
1
0
No
1
0
0
8
Yes
1
0
1
10
1
1
0
12
1
1
1
14
1
A6
A5
A4
A3
CAS Latency
0
0
0
0
16
0
0
0
1
17
0
0
1
0
18
0
0
1
1
19
0
1
0
0
20
0
1
0
1
21
0
1
1
0
22
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
Figure 3: Mode Register Definition
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HY5FS123235AFCP
Burst Length
Read and write accesses to the GDDR4 SDRAM are burst-oriented, with the burst length fixed at 8 and thus not
programmable in the MRS as with many other DRAMs. The burst length determines the maximum number of column
locations that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A3–Ai (where Ai is the most significant column address bit for a given
configuration) as the GDDR4 SDRAM has a fixed burst length of 8. Also GDDR4 SDRAM has a fixed start address of 000
within the block, thus A2-A0 does not select the access order within a burst and must be set to zero.
Table 2 Burst Order
Burst Length
Starting Column Address
Order of Access within a burst
Type = Sequential
A2 A1 A0
8
0 0 0
0-1-2-3-4-5-6-7
CAS Latency
The READ latency, or CAS latency, is the delay between the registration of a READ command and the availability of the
first piece of output data. The latency is set using bits A3-A6 and values of 7 - 20 are supported in the specification.
Vendor specifications should be checked for value(s) of CAS latency supported.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally
coincident with clock edge n + m.
Table 3 Cas Latency
Speed
-06
Allowable Operating Frequency (GHz)
CL 22
<=1.6
(RDBI)
-07
-08
-09
Rev. 1.2 /June. 2008
CL 21
CL20
CL19
CL18
CL17
CL16
CL 15
CL 14
<=1.6
<=1.4
(RDBI)
<=1.4
<=1.2
(RDBI)
<=1.2
<=1.1
(RDBI)
<=1.1
10
HY5FS123235AFCP
WRITE Latency
The WRITE latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability
of the first bit of input data. The latency can be set from 1 to 7 clocks depending on the operating frequency and desired
current draw. When the write latencies are set to small values (1,2,... clocks), the input receivers never turn off, in turn,
raising the operating power. When the WRITE latency is set to higher values (... 6, 7 clocks) the input receivers turn on
when the WRITE command is registered. Vendor specifications should be checked for value(s) of WL supported and the
specific value(s) of WL where the input receivers are always on or only turn on when the WRITE command is
registered.
If a WRITE command is registered at clock edge n, and the latency is m clocks, the data will be available nominally
coincident with clock edge n + m.
WRITE Recovery (WR)
WR must be programmed into bits A0-A2 with a value greater than or equal to RU {tWR/tCK}, where RU stands for
round up, tWR is the analog value from the vendor datasheet and tCK is the operating clock cycle time. the WR register bits are not a required function and may be implemented at the discretion of the memory manufacturer.
Test Mode
The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to zero, and bits
A0-A6 and A8-A12 set to the desired values. Test Mode is initiated by issuing a MODE REGISTER SET command with
bits A7 set to one, and bits A0-A7 and A9-A12 set to the desired values. Test mode functions are specific to each DRAM
vendor and their exact function are hidden from the user.
DLL Reset
The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A8 set to zero, and bits
A0-A7 and A9-A12 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with
bit A8 set to one, and bits A0-A7 and A9-A12 set to the desired values. When a DLL Reset is complete the GDDR4 SDRAM
Reset bit, A8 of the mode register is self clearing (i.e. automatically set to a zero by the GDDR4 SDRAM).
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HY5FS123235AFCP
EXTENDED MODE REGISTER (EMR)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include output drive strength selection, control of DBI, preamble selection and Vendor ID as shown in Figure 4.
The Extended Mode Register is programmed via the MODE REGISTER SET (MRS) command (with BA0=1, BA1=0 and
BA2=0) and will retain the stored information until it is reprogrammed or the device loses power. The Extended Mode
Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements will result in
unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
RFU bits are reserved for future use and must be programmed to 0.
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HY5FS123235AFCP
BA2
BA1
BA0
A12
A11
A10
A9
A8
A7
0
0
1
RFU
V-ID
MDBI
WDBI
RDBI
A6
DLL
A11
Vendor-ID
A7
DLL
0
Disable
0
Enable
1
Enable
1
Disable
A5
A4
A3
A2
DQTermination
Preamble
A1
DriverStrengths/
Termination
A1
A0
Driver-Strengths
/Termination
0
0
Auto Calibration
0
1
RFU
0
nominal
1
RFU
A10
Mode DBI
A8
Read DBI
1
0
DC Mode
0
Disable
1
1
AC Mode
1
Enable
A9
Write DBI
0
Disable
A3
A2
DQ-Termination
Enable
0
0
ALL OFF
1
A6
A5
A4
Preamble
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
RFU
1
1
0
RFU
1
1
1
RFU
A0
0
1
DQ OFF
1
0
1/4 ZQ DQ
1
1
1/2 ZQ DQ
Figure 4: Extended Mode Register Definition
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HY5FS123235AFCP
DRIVER Strengths/Termination
The Data Driver Impedance, DZ, is used to determine the value of the data drivers impedance. The Auto Calibration
option enables the Auto-Calibration functionality of the DRAM which controls the Pulldown-, Pullup-Driver Strength and
the Termination over process, temperature and voltage changes. The nominal option enables the factory setting for
the Pulldown, Pullup-Driver-Strength and for the Termination. The design target for the factory setting is 40Ohm
Pulldown, 60Ohm Pullup-Driver-Strength and 60/120Ohm for DQ-Termination, 60/120/240Ohm for CMD/ADDTermination with nominal process, voltage and temperature conditions. With the nominal option enabled,
Driver-Strength and Termination is expected to change with process, voltage and temperature variations.
AC timings are only guaranteed with Auto Calibration.
DQ Termination
DQ Termination is used in combination with Driver Strengths/Termination setting to define the value for the on-die
termination for the DQ, DM, and WDQS pins.
GDDR4 SDRAM’s DQ Termination supports values of 1/4 ZQ or 1/2 ZQ intended for a single-or-dual-loaded system.
DQ Termination is set with bits A2 and A3 during an MRS command to EMR. The ZQ value is controlled by the EMR
Driver Strengths/Termination setting.
The DQ Termination setting is also used to turn off the on-die termination on a GDDR4 SDRAM. If A3 & A2 is set 00,
all DQ, DM, WDQS and Command/Address terminators on the device are disabled. If A3 & A2 is set 01 all DQ, DM,
WDQS Terminations are switched off but Command/Address terminators are still enabled. GDDR4 adds a mode where
only the DQS termination is on(see EMR3 LPTERM). The LPTERM mode is only valid if A3 & A2 is set to either 10 or 11.
To assure that address/command termination is enabled during initialization, the GDDR4 SDRAM automatically sets
EMR bits A3 & A2 and EMR3 bit A5 to a default setting during the 200 us window after power/clock stabilization.
The default setting for EMR[A3:A2] is either 01, 10 or 11, and for EMR3[A5] is 0.
Preamble
The READ and WRITE preamble in GDDR4 SDRAMs is programmable using bits A4 - A6. Values of 1-5 tCK are
specified. Additional cycles of preamble may be required to attain the desired frequency. It is recommended that
Controller manufacturers support all values. Manufacturer datasheets should be consulted as the maximum number
of preamble cycles over clock frequency which is supported by the GDD4 SDRAm for Read commands is vendor
specific and will be defined by each vendor’s specification.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon
returning to normal operation after disabling the DLL for debugging or evaluation as well as low power operation.
(When the device exits self refresh mode in normal operation, the DLL is enabled automatically.) Any time the DLL is
enabled, tDL must be met before a READ command can be issued.
DBI
Data Bus Inversion (DBI) for READ and WRITE is selected independently using bit A8 for read and bit A9 for write.
The mode of DBI is selected using bit A10. For more details on DBI see DBI in the Operation section.
Vendor ID
Vendor ID is used to identify the manufacture of the GDDR4 SDRAM. For more details on Vendor ID see Section
entitled VENDOR ID, PARITY & SCAN for more details.
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HY5FS123235AFCP
EXTENDED MODE REGISTER 2 (EMR2)
The Extended Mode Register 2 controls functions beyond those controlled by the Mode Register and Extended Mode
Register; these additional functions include the offset for both the driver and termination as shown in Figure 5. The
Extended Mode Register 2 is programmed via the MODE REGISTER SET (MRS) command (with BA0=0, BA0=1 and
BA2=0) and will retain the stored information until it is reprogrammed or the device loses power. The Extended Mode
Register 2 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may
result. RFU bits are reserved for future use and must be programmed to 0.
BA2
BA1
BA0
0
1
0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
OCD-Termination
/Pull-Up-offset
RFU
A2
A1
A0
OCD-PullDown
Driver offset
A5
A4
A3
OCD-Termination
/Pull-Up-offset
A2
A1
A0
OCD-PullDown
Driver offset
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
2
0
1
0
2
0
1
1
3
0
1
1
3
1
0
0
-4
1
0
0
-4
1
0
1
-3
1
0
1
-3
1
1
0
-2
1
1
0
-2
1
1
1
-1
1
1
1
-1
Figure 5: Extended Mode Register 2 Definition
OCD PullDown Driver and Termination PullUp Driver offset
GDDR4 SDRAM adds the ability to add or subtract offsets from both the Driver and Terminator. See section entitled
DRIVER & TERMINATION for more details.
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HY5FS123235AFCP
EXTENDED MODE REGISTER 3 (EMR)
The Extended Mode Register 3 controls functions beyond those controlled by the Mode Register, Extended Mode
Register and Extended Mode Register 2; these additional functions include LPTERM and Parity as shown in Figure 6.
The Extended Mode Register 3 is programmed via the MODE REGISTER SET (MRS) command (with BA0=1, BA1=1
and BA2=0) and will retain the stored information until it is reprogrammed or the device loses power. The Extended
Mode Register 3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait
the specified time tMRD before initiating any subsequent operation. Violating either of these requirements will result in
unspecified operation.
If the user activates bits in the Extended Mode Register 3 in an optional field, either the optional field is activated (if
option is implemented in the device) or no action is taken by the device ( if option is not implemented). Reserved
states should not be used, as unknown operation or incompatibility with future versions may result. RFU bits are
reserved for future use and must be programmed to 0.
BA2
BA1
BA0
A12
0
1
1
RFU
A11
A10
A9
A8
A7
A6
DRAM Info
A7
A6
A5
A4
A3
LP
TERM
A5
LPTERM
0
Disabled
1
Enabled
0
Vendor ID
0
1
PERR_Info/optional
1
0
Vendor Specific
1
1
Vendor Specific
A1
A0
RFU
DRAM Info
0
A2
Figure 6: Extended Mode Register 3 Definition
LPTERM
GDDR4 SDRAM adds a low power mode which reduces power consumed for I/O termination by disabling the
termination for a subset of the pins. See Section entitled DRIVER & TERMINATION for more details.
DRAM Info
DRAM info is used to select either Parity info or Vendor ID info to be output.
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HY5FS123235AFCP
COMMAND & ADDRESS
Addressing
GDDR4 SDRAMs use a multiplexed address scheme to reduce pins required on the GDDR4 SDRAM as shown in Table
3. The addresses should be provided to the GDDR4 SDRAM in two parts that are latched into the memory with two
consecutive clock edges. Command protocols incorporating such as CS#, RAS#, CAS# and WE# should be issued at
the first rising edge of the clock and the half of addresses will be registered along with command inputs. Following this
cycle, the remaining half of addresses will be registered at the rising edge of the clock.
Table 4 Address Pairs
Clock
First
BA2
BA1
BA0
A12
A11
A10
A9
A8
Second
A6
A5
A1
A2
A3
A0
A7
A4
The commands such as ACTIVE, READ, READ with autoprecharge, WRITE, WRITE with autoprecharge,
Precharge, Precharge all, MODE REGISTER SET, Auto-refresh and Self-refresh would require two consecutive clocks to
fulfill single task. Only NOP command can be registered at single clock cycle. The clock reference for the AC timing is
defined as the first rising edge of the clock.
It is prohibited to issue any other command at the second clock cycle which has been reserved for the second half of
the addresses. for the preceding command.
Table 5 Addressing Scheme
16Mx32
Rev. 1.2 /June. 2008
Row address
A0~A11
Column address
A0~A7,A9
Bank address
BA0~BA2
Auto precharge
A8
Refresh
8K/32ms
Refresh period
3.9us
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HY5FS123235AFCP
Table 6 Truth Table Commands
NAME(FUNCTION)
CKE#
Previous Current CS# RAS# CAS# WE#
cycle
cycle
ADDR
NOTES
1, 7, 9
DESELECT (NOP)
L
X
H
X
X
X
X
NO OPERATION(NOP)
L
X
L
H
H
H
X
1, 7
ACTIVE (SELECT BANK & activate row)
L
L
L
L
H
H
Bank/Row
1, 3, 10
READ (Select bank and column, & start READ burst)
L
L
L
H
L
H
Bank/Col
1, 4, 10
WRITE (Select bank and column, & start WRITE burst)
L
L
L
H
L
L
Bank/Col
1, 4, 10
PRECHARGE (Deactivate row in bank or banks)
L
L
L
L
H
L
Code
1, 4, 5, 10
AUTO REFRESH
L
L
L
L
L
H
X
1, 6
SELF REFRESH ENTRY
L
H
L
L
L
H
X
1, 6
SELF REFRESH EXIT
H
L
POWER DOWN ENTRY
L
H
POWER DOWN EXIT
H
L
MODE REGISTER SET
L
L
DATA TERMINATOR DISABLE
L
L
H
X
X
X
X
1, 6
L
H
H
H
X
1, 6
H
X
X
X
X
1
L
H
H
H
X
1
H
X
X
X
X
1
L
H
H
H
X
1
L
L
L
L
Op-Code
1, 2, 10
H
H
L
H
X
1, 8
Notes:
1) H = Logic High Level; L = Logic Low Level; X = Don’t care.
2) BA0-BA2 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0, BA2=0 select the mode
register; BA0 = 1, BA1 = 0, BA2 = 0 select extended mode register; BA0 = 0, BA1 = 1, BA2 = 0 select extended
mode register 2; BA0 = 1, BA1 =1, BA2 = 0 select extended mode register 3; other combinations of BA0-BA2 are
reserved). A0-A12 provide the op-code to be written to the selected mode register.
3) BA0-BA2 provide bank address and A0 A11 provide row address.
4) BA0-BA2 provide bank address; A0-A7 and A9 provide column address; A8 HIGH enables the auto precharge
feature (nonpersistent), and A8 LOW disables the auto precharge feature.
5) A8 LOW: BA0-BA2 determine which bank is precharged.
A8 HIGH: all banks are precharged and BA0-BA2 are “Don’t Care.”
6) Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE#.
7) DESELECT and NOP are functionally interchangeable.
8) Used for bus snooping when the DQ termination is set to ZQ/2 in the EMRS and cannot be used during power-down
or self refresh.
9) The decode of the DESELECT command excludes the DATA TERMINATOR DISABLE command.
10) Address is received on two consecutive rising edges of CK
Table 7 Truth Table - DM Operations
FUNCTION
DM
DQ
Write Enable
L
Valid
NOTES
1
Write Inhibit
H
X
1
Notes: 1) Used to mask write data, provided coincident with the corresponding data.
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HY5FS123235AFCP
OPERATION
Deselect (NOP)
Activation
The DESELECT function (CS# HIGH) prevents new
commands from being executed by the GDDR4 SDRAM.
The GDDR4 SDRAM is effectively deselected. Operations
already in progress are not affected.
Before any READ or WRITE commands can be issued to
a bank in the GDDR4 SDRAM, a row in that bank must be
“opened”. This is accomplished by the ACTIVE command
(see Figure 8): BA0-BA2 select the bank, and the address
inputs select the row to be activated. Once a row is open,
a READ or WRITE command could be issued to that row,
subject to the tRCD specification.
A subsequent ACTIVE command to another row in the
same bank can only be issued after the previous row has
been closed. The minimum time interval between two
successive ACTIVE commands on the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum
time interval between two successive ACTIVE commands
on different banks is defined by tRRD. Figure 9 shows the
tRCD and tRRD definition.
The row remains active until a PRECHARGE command (or
READ or WRITE command with Auto Precharge) is issued
to the bank.
A PRECHARGE command (or READ or WRITE command
with Auto Precharge) must be issued before opening a
different row in the same bank.
No Operation (NOP)
The NO OPERATION (NOP) command is used to instruct
the selected GDDR4 SDRAM to perform a NOP (CS#
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations already in
progress are not affected.
MODE REGISTER SET
The mode registers are loaded via inputs A0 A12.
See mode register descriptions in the Register Definition
section. The MODE REGISTER SET command can only be
issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
M o d e R eg iste r S e t
CK#
CK
CKE#
R o w A ctiva tio n
CK#
CK
CKE#
LO W
CS#
CS#
RAS#
RAS#
CAS#
CAS#
W E#
W E#
A 0 ,A 2 ,A 3 ,A 4 ,A 7
A 8 -A 1 2
A 0 ,A 2 ,A 3 ,A 4,A 7
A 8 -A 1 2
B A 0 ,1 ,2
A 1 ,A 5 ,A 6
CO
A 8 ,9 ,1 0 ,1 1 ,1 2
CO
A 4 ,7 ,0 ,3 ,2
BA
CO
B A 0,1,2
A 1 ,5 ,6
R A = R o w A d d re ss
D O N ’T C A R E
C O = O p -co d e
B A = B a n k A d d re ss
E N A P = E n a b le A u to P re ch a rg e
D IS A P = D isa b le A u to P re ch arg e
Figure 7: MRS Command
Rev. 1.2 /June. 2008
B A 0,1 ,2
A 1 ,A 5,A 6
LO W
RA
A 8,9 ,1 0,1 1 ,1 2
RA
A 4 ,7 ,0 ,3 ,2
BA
B A 0 ,1 ,2
RA
A 1 ,5 ,6
R A = R o w A d d re ss
D O N ’T C A R E
C A = C o lu m n A d d ress
B A = B an k A d d ress
EN A P = E n a b le A u to Prech a rg e
D IS A P = D isa b le A u to P re ch arg e
Figure 8: ACTIVE command
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HY5FS123235AFCP
CK#
CK
Command
ACT
NOP
ACT
NOP
A0-A12
Row x
Row x
Row y
Row y
BA0-BA2
BA x
NOP
BA y
RD/WR
NOP
Col y
Col y
BA y
tRRD
tRCD
= Don’t Care
Figure 9: Bank Activation Command Cycle
Data Terminator Disable
Bus snooping for READ commands other than CS# is used to control the on-die termination in the dual load
configuration. See Section DRIVER & TERMINATION for more details on GDDR4 SDRAM Termination.
Bank Restrictions
For eight bank GDDR4 devices, there may be a need to limit the number of activates in a rolling window to ensure
that the instantaneous current supplying capability of the devices is not exceeded. To reflect the true capability of the
DRAM instantaneous current supply, the parameter tFAW (four activate window) is defined. No more than 4 banks may
be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up to
next integer value.
As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock
N, no more than three further activate commands may be issued in clocks N+1 through N+9.
It is also acceptable and preferable that GDDR4 SDRAMs have no restrictions on the number of banks activated.
CK#
T0
T1
T2
T3
ACT
ACT
ACT
Tm
Tm+1
Tm+2
Tm+3
Tm+4
ACT
ACT
ACT
ACT
CK
CMD ACT
t
RRD
t
RRD
t
t
RRD
t
FAW
RRD
t
t
RRD
t
RRD
3*t
FAW+ RRD
Figure 10: tFAW
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HY5FS123235AFCP
READ
READ burst is initiated with a READ command. as shown in Figure 11. The starting column and bank addresses are
provided at the READ command and the following clock cycle, and auto precharge is either enabled or disabled for that
access with the A8 pin. If auto precharge is enabled, the row being accessed is precharged at the completion of the
burst after tRAS min has been met or after the number of clock cycles programmed in EMR3 for RAS depending on the
implementation choice per DRAM vendor.
During READ bursts, the first valid data-out element from the starting column address will be available following the
CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the next positive
RDQS edge. The GDDR4 SDRAM drives the output data edge aligned to RDQS. And all outputs, i.e. DQs and RDQS, are
also edge aligned to the clock. Prior to the first valid RDQS rising edge, a cycle is driven and specified as the READ preamble. The single preamble consists of a half cycle High followed by a half cycle of Low driven by the GDDR4 SDRAM.
For the multi-cycle preamble it should be set in extended mode register. The cycle on RDQS consisting of a half cycle
Low coincident with the last data-out element followed by a half cycle High is known as the read postamble, and it will
be driven by the SDRAM. The SDRAM toggles RDQS only when it is driving valid data on the bus.
Upon completion of a burst, assuming no other command has been initiated; the DQs and RDQS will be in a Hi-Z state.
Data from any READ burst may be concatenated with data from a subsequent READ command. A continuous flow of
data can be maintained. The first data element from the new burst follows the last element of a completed burst.
The new READ command should be issued at least 4 cycles after the first READ command. A PRECHARGE can also be
issued to the SDRAM with the same timing restriction as the new READ command if tRAS is met. A WRITE can be
issued any time after a READ command as long as the bus turn around time is met. READ data cannot be truncated.
The data inversion flag is driven on the DM signal to identify whether the data is true or inverted data. If DM is HIGH,
the data will is inverted and not inverted when it recognizes DM is LOW. READ Data Inversion can be programmed as
a Disable (A8=0) or Enable (A8=1) in the EMRS.
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HY5FS123235AFCP
Figure 11: READ Command
T0
T1
T13
T14 T14n T15 T15n T16 T16n T17 T17n
COMMAND
READ
NOP
NOP
NOP
ADDRESS
Bank a,
Col n
T18
T19
NOP
NOP
CK#
CK
NOP
NOP
NOP
Col n
CL = 14
tRPST
tRPRE
RDQS
RPRE = 1
DQ
DM
DOn
DO
n+7
DBI
DBI
n+7
ODT Enabled
DQ ODT Disabled
DQ ODT ODT Enabled
RDQS ODT
ODT Enabled
RDQS ODT Disabled
ODT
Enabled
Snoop ODT
ODT Enabled
DQ RDQS ODT Disabled
ODT
Enabled
T0
T1
T13
T14 T14n T15 T15n T16 T16n T17 T17n
COMMAND
READ
NOP
NOP
NOP
ADDRESS
Bank a,
Col n
Col n
T18
T19
T20
NOP
NOP
NOP
CK#
CK
NOP
NOP
NOP
tRPST
CL = 15
tRPRE
RDQS
RPRE = 2
DQ
DM
DQ ODT ODT Enabled
DOn
DO
n+7
DBI
DBI
n+7
ODT Enabled
DQ ODT Disabled
RDQS ODT
ODT Enabled
RDQS ODT Disabled
ODT
Enabled
Snoop ODT
ODT Enabled
DQ RDQS ODT Disabled
ODT
Enabled
DON’T CARE
TRANSITIONING DATA
Note:
2 case is shown for an example. Actual supported RPRE numbers will be found in EMRS standard.
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HY5FS123235AFCP
Figure 12: Byte Lane READ Timing
T1
T0
T2
T2n
T3
T3n
T4n
T4
T5
T5n
T6
CK#
CK
t
CH tCL
DQSQ(max)
t
DQSQ(min)
t
RDQS1,6
DQ
DQ
t
DQSQ(max)
DQSQ(min)
t
T2
(Last data valid)
T2n
T2
(First data no longer valid)
t
ALL DQs and RDQS,
collectively5
T3
T4
T3n
T4n
T5
T2n
T3
T3n
T4
T4n
T5
T2n
T3
T3n
T4
T4n
T5
T5n
T5n
QH
T2
T5n
Shown for RPRE = 1
Figure 13: Byte Lane to CK/CK#
T1
T0
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
CK#
CK
t
t
CH
CL
t
DQSCK (MAX)
RDQS
ALL DQs and RDQS,
collectively
T2
t
T2n
T3
T3n
T4
T4n
T5
T5n
AC (MAX)
t
RDQS
ALL DQs and RDQS,
collectively
DQSCK (MIN)
T2
T2n
T3
T3n
T4
T4n
T5
T5n
t
AC (MIN)
Shown for RPRE = 1
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
Figure 14: READ to WRITE
T0
T1
T13
T14 T14n T15 T15n T16 T16n T17 T17n
COMMAND
READ
NOP
NOP
NOP
ADDRESS
Bank a,
Col n
Col n
T18
T19 T19n T20 T20n
CK#
CK
WRITE
NOP
Bank,
Col b
Col b
NOP
NOP
NOP
NOP
CL = 14
RDQS
DBI
t
WL=5
WDQS
DQ
DM
DQ ODT ODT Enabled
DOn
DO
n+7
DBIn
DO
n+7
DIb
DQ ODT Disabled
ODT Enabled
RDQS ODT
ODT Enabled
RDQS ODT Disabled
ODT Enabled
Snoop ODT
ODT Enabled
DQ RDQS ODT Disabled
ODT Enabled
DON’T CARE
TRANSITIONING DATA
Notes:
1. DO n = data-out from column n.
2. DI b = data-in from column b.
3. Seven subsequent elements of data-out appear in the programmed order following DO n.
4. Data-in elements are applied following DI b in the programmed order.
5. Shown with nominal tAC, and tDQSQ.
6. tDQSS in nominal case. RDQS will start driving HIGH one half-clock cycle prior to the first falling edge of RDQS.
READ and DLL Off Mode
The GDDR4 uses a DLL to synchronize the byte lane to the clock. Although the DLL provides accurate clocking of data
out, it requires a minimum operating frequency to function properly. The EXTENDED MODE REGISTER provides an
avenue to turn the DLL off for running at lower frequencies.
The GDDR4 devices default into the DLL off mode upon power-up. The device enters the DLL on mode of operation if
and when the DLL is enabled, via a MODE REGISTER SET Command to the Extended Mode Register. Once in the DLL
on mode, the device remains in that mode until powered down or turned off via the EXTENDED MODE REGISTER.
With the DLL off mode the output, DQ and DQS transitions may or may not align with CK and CK# transitions,
depending on clock frequency and CAS Latency settings.
The burst READ operation is a bit different from the standard DLL on mode. The time frame from the READ command
to first data out is defined by the CAS latency minus one plus tAC (DLL Off). Data moves from the DRAM cell to the
sense amp and is held in a buffer waiting for the appropriate clock cycle. The data will fire from the buffer tAC(DLL off)
after the clock edge prior to the programmed CAS latency.
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
T0
T1
T13
T14 T14n T15 T15n T16 T16n T17 T17n
COMMAND
READ
NOP
NOP
NOP
ADDRESS
Bank a,
Col n
Col n
T18
CK#
CK
NOP
NOP
NOP
NOP
CL = 14
RDQS
DQ
DO
n+7
DOn
t
AC(DLL Off)
DON’T CARE
TRANSITIONING DATA
Figure 15: DLL Off Timing
WRITE
WRITE bursts are initiated with a WRITE command (see Figure 16). The starting column and bank addresses are
provided at the WRITE command and the following clock cycle, and auto precharge is either enabled or disabled for
that access with the A8 pin. If auto precharge is enabled, the row being accessed is precharged at the completion of
the burst or after tRAS min is met or after the number of clock cycle programmed in EMR3 for RAS depending on the
implementation choice per DRAM vendor.
During WRITE bursts, the first valid data-in element will be registered on a rising of WDQS following the write latency
plus the number preamble set in the mode (and extended mode) register and subsequent data elements will be
registered on successive edges of WDQS. Prior to the first valid WDQS edge a cycle or cycles is/are needed and
specified as the WRITE Preamble. The cycle on WDQS following the last data-in element is known as the write
postamble and must be driven high by the controller it can not be left to float high using the on die termination.
A Valid strobe edge is defined as a strobe edge associated with data.
The time between the WRITE command and the first valid edge of WDQS (tDQSS) is specified relative to the write
latency and the number of write preamble (WL - 0.25CK and WL + 0.25CK), where WPRE is the number of write
preamble set in the extended mode register. All of the WRITE diagrams show the nominal case, and where the two
extreme cases (i.e., tDQSS [MIN] and tDQSS[MAX]) might not be intuitive, they have also been included.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain High and any
additional input data will be ignored. Data for any WRITE burst may not be truncated with a subsequent WRITE command. The new WRITE command can be issued on any positive edge of clock following the previous WRITE command
assuming the previous burst has completed. The new WRITE command should be issued at least 4 cycles after the
first WRITE command. Data for any WRITE burst cannot be truncated by a subsequent PRECHARGE command.
After the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
The data inversion flag receives the RDQS signal to identify whether to store the true or inverted data. If RDQS is
HIGH, the data will be stored after inversion inside the GDDR4 SDRAM and not inverted when it recognizes RDQS is
LOW. WRITE Data Inversion can be programmed as an Disable(A9=0) or Enable (A9=1) in the EMRS.
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HY5FS123235AFCP
Figure 16: WRITE Command
T0
T1
T2
T3
T4
WRITE
NOP
NOP
NOP
NOP
Bank a,
Col b
Col b
T4n
T7
T7n
T8
CK#
CK
COMMAND
ADDRESS
t
t
t
WL=4, WPRE=1
DQSS(NOM)
WDQS
DQSS
NOP
t
WPRE
DQ
WPST
DIb
DI
b+7
DBI
DBI
b+7
DM
RDQS
ODT
ODT Enabled
Snoop ODT
ODT Enabled
t
t
t
DQSS(NOM)
WDQS
WL=4, WPRE=2
NOP
DQSS
DQ
t
WPRE
WPST
DIb
DI
b+7
DIb
DI
b+7
DM
RDQS
ODT
ODT Enabled
Snoop ODT
ODT Enabled
DON’T CARE
TRANSITIONING DATA
Note:
WPRE=2 case is shown as an example. Actual supported WPRE values are found in the EMR.
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HY5FS123235AFCP
Figure 17: WRITE Capture
T0
T1
T2
T1n
T2n
T3
T4
T3n
T4n
T5
CK#
CK
W DQS
t
DQ
DQSL
t
DQSH
DI
n+7
DI n
DM
t
t
DS
DH
TRANSITIONING DATA
DON’T CARE
Show n for WPRE=1 tCK
Figure 18: WRITE to READ
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
Bank a,
Col b
Col b
T3n
T6
T6n
T7
T8
T12
T13
T24 T24n T25 T25n
READ
NOP
NOP
Bank a,
Col n
Col n
CK#
CK
NOP
NOP
NOP
tWTR = 5
NOP
t
t
DQSS(NOM)
WDQS
DQSS
CL = 13
t
t
WPRE
WPST
DIb
DQ
DI
b+7
DOn
DM
DBI
RDQS
DBI
DBI
b+7
DQ ODT
ODT Enabled
RDQS ODT
ODT Enabled
ODT Off
Snoop ODT
ODT Enabled
ODT Off
ODT Off
DON’T CARE
TRANSITIONING DATA
DI b = data-in for column b.
Seven subsequent elements of data-in are applied in the specified order following DI b.
tWTR is referenced from the first positive CK edge after the last written data.
The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be to
different devices, in which case tWTR is not required and the READ command could be applied earlier.
5. A8 is LOW with the WRITE command (auto precharge is disabled).
6. WRITE latency is set to 3.
7. The 8n prefetch architecture requires a 5-clock WRITE to READ turnaround time (tWTR).
1.
2.
3.
4.
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HY5FS123235AFCP
PRECHARGE
The PRECHARGE command (see Figure 19) is used to deactivate the open row in a particular bank or the open row in
all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE
command is issued.
Input A8 determines whether one or all banks are to be precharged. In case where only one bank is to be precharged,
inputs BA0-BA2 select the bank. Otherwise BA0-BA2 are treated as “Dont Care”.
Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE command
being issued. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the
previously open row is already in the process of precharging.
P re ch a rg e
CK#
CK
CKE# LO W
CS#
RAS#
CAS#
W E#
A 9 -A 1 2
A 0 ,A 2 ,A 3 ,A 7
EN AP
A8
D IS A P
B A 0 -B A 2
A 1 ,A 5 ,A 6
BA
B A = B a n k A d d r e s s ( if A 8 is L O W ;
O t h e r w is e “ D o n ’ t C a r e ” )
Figure 19: PRECHARGE command
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual bank precharge function as described above, but
without requiring an explicit command. This is accomplished by using A8 (A8 = High), to enable Auto Precharge in
conjunction with a specific READ or WRITE command.
A precharge of the bank / row that is addressed with the READ or WRITE command is automatically performed upon
completion of the read or write burst. Auto Precharge is non persistent in that it is either enabled or disabled for each
individual READ or WRITE command.
Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharing time (tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation
section of this specification.
AUTO REFRESH
AUTO REFRESH command (see Figure 20) is used during normal operation of the GDDR4 SDRAM. This command is
non persistent, so it must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. The GDDR4 SDRAM requires AUTO REFRESH
commands at an average periodic interval of tREFI. The values of tREFI for different densities are listed in Table 4.
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HY5FS123235AFCP
A u to -R e fr e s h
CK#
CK
CKE# LOW
S e lf-R e fre s h
CK#
CK
C K E # H IG H
CS#
CS#
RAS#
RAS#
CAS#
CAS#
W E#
W E#
A 9 -A 1 2
A 0 ,A 2 ,A 3 ,A 7
A 9 -A 1 2
A 0 ,A 2 ,A 3 ,A 7
A8
A8
B A 0 -B A 2
A 1 ,A 5 ,A 6
B A 0 -B A 2
A 1 ,A 5 ,A 6
Figure 20: AUTO REFRESH command
Figure 21: SELF REFRESH command
SELF REFRESH
The SELF REFRESH command (see Figure 21) can be used to retain data in the GDDR4 SDRAM, even if the rest of the
system is powered down. When in the self refresh mode, the GDDR4 SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE# is disabled(HIGH). The DLL
is automatically disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF
REFRESH. The on-die termination is also disabled upon entering Self Refresh except for CKE# and enabled upon
exiting Self Refresh. (tXSRD must occur before a read command can be issued, tXSNR must occur before a non-read
command can be issued.) Input signals except CKE# are Dont Care during SELF REFRESH.
The procedure for exiting self refresh (see Figure 22) requires a sequence of commands. First, CK and CK# must be
stable prior to CKE# going back LOW. Once CKE# is LOW, the GDDR4 SDRAM must have NOP commands issued for
tXSNR because time is required for the completion of any internal refresh in progress.
A simple algorithm for meeting both refresh and DLL requirements and output calibration is to apply NOPs for tXSRD
cycles before applying any other command to allow the DLL to lock and the output drivers to recalibrate.
If the GDDR4 device enters SELF REFRESH with the DLL disabled the GDDR4 device will exit SELF REFRESH with the
DLL disabled.
Rev. 1.2 /June. 2008
29
HY5FS123235AFCP
CK#
CK
T0
T1
T2
T3
T4
Tm
Tm +1
t
IS
Tm +2
t
XSNR
t
CKE#
t
t
RP
CMD NOP
NOP
IS
Auto
Refresh
Enter
Self Refresh
Mode
t
NOP
Tn
XSRD
CKE
NOP
NOP
Exit
Self Refresh
Mode
NOP
Non
READ
READ
Figure 22: Self Refresh Entry and Exit
Note:
1. Device must be in the “All banks idle” state prior to entering Self Refresh mode.
2. Minimum CKE# pulse width must satisfy tCKE.
3. After issuing Self Refresh command, two more NOPs should be issued.
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
Power-Down
GDDR4 SDRAMs require CKE# to be active at all times that an access is in progress: from the issuing of a READ or
WRITE command until completion of the burst. For READs, a burst completion is defined when the Read Postamble
is satisfied; For WRITEs, a burst completion is defined when the write postamble is satisfied.
Figure 23 shows Powerdown entry and exit. Powerdown is entered when CKE# is registered HIGH. If powerdown
occurs when all banks are idle, this mode is referred to as precharge powerdown; if power-down occurs when there
is a row active in any banks, this mode is referred to as active powerdown. Entering power-down deactivates the
input and output buffers, excluding CK, CK#, RESET and CKE#. However, powerdown duration is limited by the
refresh requirements of the device. While in powerdown, CKE# and RESET must be HIGH and a stable clock signal m
ust be maintained at the inputs of the GDDR4 SDRAM, while all other input signals are “Don’t Care”.
The power-down state is synchronously exited when CKE# is registered LOW (in conjunction with a NOP or
DESELECT command). A valid executable command may be applied tPDEX cycles later.
CK#
CK
T0
T1
T2
T3
T4
Tm
Tm+1
t
CKE#
t
t
RP
CMD NOP
VALID
No READ/WRITE
Access in progress
IS
NOP
t
NOP
IS
Tm+2
t
Tn
PDEX
CKE
NOP
Enter
Power Down
Mode
NOP
NOP
VALID
Exit
Power Down
Mode
Figure 23: Power-Down Entry and Exit
Note:
1. Minimum CKE# pulse width must satisfy tCKE.
2. After issuing Power Down command, two more NOPs should be issued.
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
Table 8 Truth Table – CKE#
CKE#n-1
CKE#
H
H
Power-Down
CURRENT STATE
H
H
H
L
H
L
L
H
L
L
L
L
COMMANDn
ACTIONn
X
Maintain Power-Down
Self Refresh
X
Maintain Self Refresh
Power-Down
SELECT or NOP
Exit Power-Down
Self Refresh
DELECT or NOP
Exit Self Refresh
All Banks Idle
DELECT or NOP
Precharge Power-Down Entry
H
Bank(s) Active
DELECT or NOP
Active Power-Down Entry
H
All Banks Idle
AUTO REFRESH
Self Refresh Entry
NOTES
See Table 9
5
1-3
Notes
1. CKE#n is the logic state of CKE# at clock edge n; CKE#n-1 was the state of CKE# at the previous clock edge.
2. Current state is the state of the GDDR4 SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSRD period.
A minimum of tDL is needed for the DLL to lock before applying a READ command if the DLL was disabled.
Table 9 Truth Table - Current State Bank n - Command To Bank n
CURRENT STATE
Any
Idle
Row Active
Read (Auto Precharge
Disabled)
Write (Auto Precharge
Disabled)
Rev. 1.2 /June. 2008
CS#
RAS#
CAS#
WE#
H
X
X
X
DESELECT (NOP/continue previous operation)
COMMAND/ACTION
NOTES
L
H
H
H
NO OPERATION (NOP/continue previous operation)
L
L
H
H
ACTIVE (select and activate row)
L
L
L
H
AUTO REFRESH
4
L
L
L
L
MODE REGISTER SET
4
L
H
L
H
READ (select column and start READ burst)
6
L
H
L
L
WRITE (select column and start WRITE burst)
6
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
5
L
H
L
H
READ (select column and start new READ burst)
6
L
H
L
L
WRITE (select column and start WRITE burst)
L
L
H
L
PRECHARGE (only after the READ burst is complete)
L
H
L
H
READ (select column and start READ burst)
L
H
L
L
WRITE (select column and start new WRITE burst)
L
L
H
L
PRECHARGE (only after the WRITE burst is complete)
6, 8
5
6, 7
6
5, 7
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Notes
1. This table applies when CKE#n1 was LOW and CKE#n is LOW (see Table 8) and after tXSNR has been met
(if the previous state was self refresh).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands
shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled.
Write: A WRITE burst has been initiated, with auto precharge disabled.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and Table 9, and according to
Table 10.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met.
Once tRCD is met, the bank will be in the row active state.
Read w/Auto-Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto-Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command;
COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met.
Once tRC is met, the GDDR4 SDRAM will be in the all banks idle state.
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has
been met. Once tMRD is met, the GDDR4 SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, all banks will be in the idle state.
READ or WRITE: Starts with the registration of the ACTIVE command and ends the last valid data nibble.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for
precharging.
9. Reads or Writes listed in the Command/Action column include Reads or Writes with auto precharge enabled and
Reads or Writes with auto precharge disabled.
10. Requires appropriate DM masking.
11. A WRITE command may be applied after the completion of the READ burst
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
Table 10 Truth Table – Current State Bank n – Command To Bank m
CURRENT STATE
Any
Idle
Row Activating,
Active, or Precharging
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
Read
(With Auto
Precharge)
Write
(With Auto
Precharge)
CS#
RAS#
CAS#
WE#
H
X
X
X
DESELECT (NOP/continue previous operation)
COMMAND/ACTION
NO OPERATION (NOP/continue previous operation)
NOTES
L
H
H
H
X
X
X
X
Any Command Otherwise Allowed to Bank m)
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start READ burst)
6
L
H
L
L
WRITE (select column and start WRITE burst)
6
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start new READ burst)
6
L
H
L
L
WRITE (select column and start WRITE burst)
6
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start READ burst)
L
H
L
L
WRITE (select column and start new WRITE burst)
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start new READ burst)
6
L
H
L
L
WRITE (select column and start WRITE burst)
6
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start READ burst)
6
L
H
L
L
WRITE (select column and start new WRITE burst)
6
L
L
H
L
PRECHARGE
6, 7
6
Notes
1. This table applies when CKE#n-1 was LOW and CKE#n is LOW (see Table 9) and after tXSNR has been met
(if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown
are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable).
Exceptions are covered in the notes below.
3. Current state definitions: Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled.
Write: A WRITE burst has been initiated, with auto precharge disabled.
Read with Auto Precharge Enabled: See following text, Write with Auto Precharge Enabled: See following text
3a. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access
period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed
with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in
the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was
disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins.
During the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, ACTIVE,
PRECHARGE, READ and WRITE commands to the other bank may be applied. In either case, all other related limitations apply
(e.g., contention between read data and write data must be avoided).
3b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is
summarized below.
Rev. 1.2 /June. 2008
34
HY5FS123235AFCP
Table 11 Minimum Delay Between Commands to Different Banks with Auto
Precharge Enabled
From Command
WRITE
with AUTO
PRECHARGE
READ
with AUTO
PRECHARGE
To Command
Minimum delay
(with concurrent auto precharge)
READ or READ with AUTO PRECHARGE
[WL + (BL/2)] tCK + tWTR
WRITE or WRITE with AUTO PRECHARGE
(BL/2) tCK
PRECHARGE
2 tCK
ACTIVE
2 tCK
READ or READ with AUTO PRECHARGE
(BL/2) * tCK
WRITE or WRITE with AUTO PRECHARGE
[CL+(BL/2) + 2 - WL] * tCK
PRECHARGE
2 tCK
ACTIVE
2 tCK
CL = CAS latency (CL) rounded up to the next integer
BL = Burst length
WL = WRITE latency
4. AUTO REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.
5. All states and sequences not shown are illegal or reserved.
6. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
7. Requires appropriate DM masking.
Rev. 1.2 /June. 2008
35
HY5FS123235AFCP
READ and WRITE DBI
The GDDR4 Data Bus Inversion (DBI) logic reduces the AC power (DBIac) as shown in the flow chart in Figure 24a for
READs. The GDDR4 DBI logic reduces the AC power as shown in the flow chart in Figure 25a for WRITEs.
GDDR4 DBI logic reduces the DC power (DBIdc) as shown in the flow chart in Figure b for READs.
The GDDR4 DBI logic reduces the DC power as shown in the flow chart in Figure b for WRITEs.
The mapping of the DBI flag for READs and WRITEs are as follows:
Table 12 DBI Flag mapping for READ
Data
DBI Flag
DQ[7:0]
DM[0]
DQ[15:8]
DM[1]
DQ[23:16]
DM[2]
DQ[31:24]
DM[3]
Table 13 DBI Flag mapping for WRITE
Data
DBI Flag
DQ[7:0]
RDQS[0]
DQ[15:8]
RDQS[1]
DQ[23:16]
RDQS[2]
DQ[31:24]
RDQS[3]
Note:
When the DBI Flag equals 1 the Data is inverted,
The timing diagram in Figure a shows the READ timing of the DM and the read data DQ.
The timing diagram in Figure 26b shows the WRITE timing of the RDQS and the write data DQ.
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
Burst Read Start
Set Previous data and
DM to High
Check different bit count
between previous data
and next data
No
Yes
Difference Count
More than 4
DM = 0
Do not invert next Data
DM = 1
Invert next Data
No
Burst End?
Yes
Back to Back
Read?
Yes
No
End
Figure 24: a Flow Chart READ DBIac
Burst Read Start
Set DM to High
Check different bit count
between all data high
and next data
No
Yes
Difference Count
More than 4
DM = 0
Do not invert next Data
DM = 1
Invert next Data
No
Burst End?
Yes
Back to Back
Read?
Yes
No
End
Figure 24: b Flow Chart READ DBIdc
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HY5FS123235AFCP
Burst WRITE Start
Set Previous data and
RDQS to High
Check different bit count
between previous data
and next data
No
Yes
Number of 1's
More than 4
RDQS = 0
Do not invert next Data
RDQS = 1
Invert next Data
No
Burst End?
Yes
Back to Back
Write?
Yes
No
End
Figure 25: a Flow Chart WRITE DBIac
Burst Write Start
Set RDQS to High
Check different bit count
between all data high
and next data
No
Yes
Number of 1's
More than 4
RDQS = 0
Do not invert next Data
RDQS = 1
Invert next Data
No
Burst End?
Yes
Back to Back
Write?
Yes
No
End
Figure 25: b Flow Chart WRITE READ DBIdc
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HY5FS123235AFCP
Figure 26: a) READ DBI Timing
CK
CK#
DQ
DM
RDQS
Figure 26: B) WRITE DBI Timing
CK
CK#
DQ
RDQS
WDQS
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
Figure 27: a) Block Diagram For READS
8 bit
8 bit
R ead D ata
DQ
Load on R ead
C o m parator
> 4 bit difference
DM
D R A M Logic
D C O ptim izw d O r
First D ata in Sequence = 1
8 bit
DQ
8 bit
R ead D ata
DM
M em ory Co ntroller Lo gic
Load on R ead
Figure 27: b) Block Diagram For WRITES
8 bit
8 bit
W rite Data
DQ
Load on Write
Comparator
> 4 bit difference
DM
Memory Controller Logic
DC Optimizwd Or
First Data in Sequence = 1
8 bit
DQ
8 bit
Data to be Written into Memory Arry
DM
DRAM Logic
Load on Write
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
CLOCKING, DATA CAPTURE
Data Capture
The Data Strobe (DQS) functionality for GDDR4 SDRAMs includes both a uni-directional, single-ended read strobe per
byte, and a uni-directional, single-ended write strobe per byte.
Write Data Strobe (WDQS) is center-aligned with Write Data and Read Data Strobe(RDQS) is edge-aligned with Read
Data. WDQS0 is assigned to DQ0~DQ7 and DM0, WDQS1;DQ8~DQ15 and DM1, WDQS2;DQ16~DQ23 and DM2,
WDQS3;DQ24~DQ31 and DM3. RDQS0 is assigned to DQ0~DQ7, RDQS1;DQ8~DQ15, RDQS2;DQ16~DQ23,
RDQS3;DQ24~DQ31.
Vref = 0.7VDDQ
WDQS
Vref = 0.7VDDQ
Write Data
t
DS tDH
RDQS
Vref = 0.7VDDQ
Read Data
Vref = 0.7VDDQ
t
DQSQ
t
QH
Figure 28: WDQS and RDQS
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
DataTraining
GDDR4 includes a training scheme that uses normal WRITE and READ operations for data training. Before starting
data training, the GDDR4 SGRAM must be powered up and initialized in a predefined manner to prevent undefined
operations. READ data training is started by going through step 1~ step 8 sequentially. After the READ data training is
completed, the WRITE data training can be started or vice versa. The preferred manner is READ data training first and
then WRITE data training.tCKL is defined as the low speed clock frequency used to train READs and is specified by the
user. tSHFC is the Stable High Frequency Clock that has been trained.
READ Data Training Sequence
Step1: The GDDR4 SGRAM must be initialized properly and set to the low speed clock frequency.
Step2: Issue a WRITE command to load the data pattern at tCKL.
The Memory Contoller Logic defines the data pattern for the training.
During the WRITE, REFRESH commands can be used if required.
Step 3: After completing the WRITE at tCKL, the clock frequency is then changed to the target frequency.
A DLL reset is required after changing the frequency. The READ command must occur within 10ms to
prevent data loss in case there is no REFRESH command.
Step 4. The controller needs to select a DQ(or Byte) to be trained and set a minimum delay.
Step 5: Issue normal READ commands. During normal READ operation, REFRESH commands can be issued
if required.
Step 6: After the READ command is issued, if the step is not Max. then go to Step 5. Repeat Step 5 and Step 6 until
all of the delay steps are scanned.
Step 7. If all DQs(or Byte) are not checked, then go to Step 4. Repeat Step 4 to Step 7 until all the DQs are scanned.
Step 8. If all completed, then END of READ data training
Rev. 1.2 /June. 2008
42
HY5FS123235AFCP
Figure 29 :a) Read data training Flowchart
Figure 29 :b) Read Data Training Timing Diagram
Rev. 1.2 /June. 2008
43
HY5FS123235AFCP
WRITE Data Training Sequence
The WRITE data training procedure is almost the same as the READ data training procedure. WRITE data training
does not require the frequency change that is required in READ data training. To make sure the WRITE completes correctly, the low speed clock frequency is selected for the WRITE operation during the READ data training. Whereas
WRITE data training case does not require such a frequency change because read data is already trained.
Step 1.START of WRITE data training
Step 2. The controller needs to select a DQ(or Byte) to be trained, and then set minimum delay.
Step 3. Issue WRITE command and then READ the data for the validation. During the WRITE and READ
operations, REFRESH commands can be issued if required.
Step 4.Increase a delay step. If the step is not Max. then go to Step 1. Repeat Steps 3~4 until scan all the delay steps.
Step 5. If all DQ(or Byte) is not checked, go to Step 2. Repeat Steps 2~5 until scan all DQs(or bytes)
Step 6. END of WRITE data training
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
Figure 30 :a) Write Data Training Flowchart
Figure 30 :b) DRAM Write Data Training Timing diagram
Rev. 1.2 /June. 2008
45
HY5FS123235AFCP
Changing Clock Frequency
( Not only frequency but also VDD change sequence as below.)
Clock Frequency Change Sequence - AREF commands
Step 1) Wait until all commands have finished, all banks are idle.
Step 2) Only NOP or DESELECT or AREF commands may be issued (must meet setup/hold relative to clock while clock
is changing) to GDDR4 SDRAM for the entire sequence unless stated to do otherwise. AREF commands must fulfill
AREF burst requirements.
Step 3) If new clock period is between the range of tCK (Max DLL Off) to tCK (Min DLL Off), then turn DLL off via EMRS
register write.
Step 4) Change the clock frequency and wait until clock is stabilized.
Step 5) If new clock period is smaller than tCK(Max DLL On), then turn DLL on via EMRS register write.
Step 6) Self Ref. Insert
Step 7) If the DLL is enabled, then complete steps 6a and 6b:
7a) Reset the DLL by writing to the MRS register.
7b) Wait tDL clock cycles before issuing any commands to the GDDR4 SDRAM.
Step 8) GDDR4 SDRAM is ready for normal operation.
Clock Frequency Change Sequence - NOP/DESELECT commands
Step 1) Wait until all commands have finished, all banks are idle.
Step 2) Send NOP or DESELECT (must meet setup/hold relative to clock while clock is changing) to GDDR4 SGRAM for
the entire sequence unless stated to do otherwise. The user must take are of AREF requirements.
Step 3) If new clock period is between the range of tCK(Max DLL Off) to tCK (Min DLL Off), then turn DLL off via EMRS
register write.
Step 4) Change the clock frequency and wait until clock is stabilized.
Step 5) If new clock period is smaller than tCK(Max DLL On), then turn DLL on via EMRS register write.
Step 6) Self Ref. Insert
Step 7) If the DLL is enabled, then complete steps 6a and 6b:
7a) Reset the DLL by writing to the MRS register.
7b) Wait tDL clock cycles before issuing any commands to the GDDR4 SDRAM.
Step 8) GDDR4 SDRAM is ready for normal operation.
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
Tm
Tn
Tn+1
Tn+2
Tp
Tr
Ts
Ts+1
Ts+2
Ts+3
MRS
NOP
NOP
NOP
NOP
CODE
CODE
A8,A7
A8=H
A7=L
BA0,BA1
BA0=L
BA1=L
T0
T1 Change Frequency of Clock
CK
CK#
t
IS
CKE#
t
DL
t
IS
t
CKE
COMMAND
NOP
NOP
NOP
NOP
Self
Ref.
NOP
NOP
NOP
NOP
NOP
Enter
Self Refresh
Mode
Exit
Self Refresh
Mode
A0-A6,A9-A11
BA2
BA2=L
Reset DLL
DON’T CARE
tDL
First Command Cycle
Figure 31: DLL is on and new frequency range DLL is on
T0
T1 Change Frequency
of Clock
Tm
Tm+1
Tn
Tn+1
Tn+2
Tr
Ts
Ts+1
Tz
NOP
MRS
NOP
NOP
CODE
CODE
CODE
CODE
A8,A7
A8=
CODE
A7=L
A8=H
A7=L
BA0,BA1
BA0=L
BA1=L
A8=H
BA2=L
BA2=L
CK
Tp
CK#
t
IS
CKE#
t
DL
t
IS
t
CKE
COMMAND
NOP
NOP
NOP
NOP
MRS
NOP
Self
Ref.
Enter
Self Refresh
Mode
A0-A6,A9-A11
BA2
DON’T CARE
Turn DLL on
NOP
NOP
NOP
NOP
Exit
Self Refresh
Mode
Reset DLL
tDL
First Command Cycle
Figure 32: DLL is off and new frequency range DLL is on
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
T0
T1 Change Frequency of Clock
Tm
Tm+1
Tm+2
Tm+3
Tm+4
MRS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A0-A6,A9-A11
CODE
CODE
A8,A7
A8=CODE
A7=H
CK
CK#
CKE#
COMMAND
NOP
BA0=H
BA1=L
BA0,BA1
BA2=L
BA2
Turn DLL off
First Command Cycle
DON’T CARE
Figure 33: DLL is on and new frequency range DLL is off
CK
CK#
T0
T1 Change Frequency of Clock
NOP
NOP
Tm
Tm+1
Tm+2
Tm+3
Tm+4
NOP
NOP
NOP
NOP
CKE#
COMMAND
NOP
NOP
NOP
A0-A6,A9-A11
A8,A7
BA0,BA1
BA2
First Command Cycle
DON’T CARE
Figure 34: DLL is off and new frequency range DLL is off
Rev. 1.2 /June. 2008
48
HY5FS123235AFCP
DRIVER & TERMINATION
Programmable Impedance Output Buffer and Active Terminator
GDDR4 SDRAM use a programmable impedance output buffer. This enables a user to match the driver impedance to
the system. To adjust the impedance, an external precision resistor (RQ) is connected between the ZQ pin and Vss.
The value of the resistor must be six times the desired driver impedance. For example, a 240ohm resistor is required
for an output impedance of 40ohm. To ensure that output impedance is one-sixth the value of RQ (within 10 percent),
the range of RQ is 210ohm to 270ohm (35ohm45ohm output impedance). RESET, CK and CK# are not internally
terminated. CK and CK# need to be terminated on the system using external one percent resistors to Vdd.
The output impedance is updated during all AUTO REFRESH commands to compensate for variations in supply
voltage and temperature. The output impedance updates are transparent to the system. Impedance updates do not
affect device operation, and all data sheet timing and current specifications are met during an update.
The device will power up with an output impedance set to nominal, close to 40ohm. To guarantee optimum output
driver impedance after power-up, the GDDR4 SDRAM needs 350 clock cycles after the clock is applied and stable to
calibrate the impedance. The user can operate the part with fewer than 350 clock cycles, but optimal output impedance is not guaranteed.
The value of RQ is also used to calibrate the internal address/command termination resistors. The termination values
are selectable at power up using CKE# and A0 with values of 60, 120 and 240ohm supported. The value of RQ is used
to calibrate the internal DQ termination resistors. The two termination values that are selectable are 1/4 of RQ and
1/2 of RQ.
Impedance Control
GDDR4 SDRAM output driver impedance and termination impedance is programmable through EMRS. The offset
impedance step values may be non-linear and will vary across suppliers and across the yield distribution and across
temperature. The offsets are only applied to the DQ, DQM, RDQS and WDQS signals. No programmability is provided
for the address and command signals. With negative offset steps the Driver Strength will be decreased and the Ron
will be increased. With positive offset steps the Driver Strength will be increased and Ron will be decreased.
With negative offset steps the Termination value will be increased. With positive offset steps the Termination value will
be decreased. The Termination offset steps will be also applied to the Pullup Driver Strength settings. IV curves and AC
timings are only guaranteed with zero offset.
Auto-calibreaded/nominal
OCD impedance
EMRS2 controlled OCD
impedance offset
Auto-calibreaded ODTl
Pull-up impedance
EMRS2 controlled ODT
impedance offset
ODT pull-up impedance
OCD pull-down impedance
Figure 35: Off sets
Rev. 1.2 /June. 2008
49
HY5FS123235AFCP
Data Terminator Disable (BUS SNOOPING FOR READ COMMANDS)
Bus snooping for READ commands is used to control the on-die termination in the dual load configuration.
The GDDR4 SDRAM will disable the on-die termination when a READ command is detected, regardless of the state of
CS#, when the ODT for the DQ pins are set for dual loads.
The on-die termination is disabled x clocks after the READ command where x equals CL - 1 and stay off for a duration
of BL + 2. In a two-rank system, both DRAM devices snoop the bus for READ commands to either device and both will
disable the on-die termination if a READ command is detected. The on-die termination for all other pins on the device
are always on for both a single-rank system and a dual-rank system.
Figure 36: Data Terminator Disable Timing
T0
T1
T13
T14 T14n T15 T15n T16 T16n T17 T17n
COMMAND
READ
NOP
NOP
NOP
ADDRESS
Bank a,
Col n
Col n
T18
T19
NOP
NOP
CK#
CK
NOP
NOP
NOP
t
t
RPST
RPRE
CL = 14
RDQS
RPRE=1
DQ
DM
DOn
DO
n+7
DBIn
DO
n+7
DQ ODT
ODT Enabled
DQ ODT Disabled
ODT Enabled
RDQS ODT
ODT Enabled
RDQS ODT Disabled
ODT Enabled
Snoop ODT
ODT Enabled
DQ, RDQS ODT Disabled
ODT Enabled
Notes
1. DO n = data-out from column n.
2. Three subsequent elements of data-out appear in the specified order following DO n.
3. Shown with nominal tAC and tDQSQ.
4. RDQS will start driving high one-half clock cycle prior to the first falling edge.
5. The Data Terminators are disabled starting at CL - 1 and the duration is BL + 2.
6. READs to either rank disable both ranks termination regardless of the logic level of CS#.
Rev. 1.2 /June. 2008
50
HY5FS123235AFCP
LPTERM
As GDDR4 SDRAM gains adoption in mobile applications there is a desire from users to support a mode where
terminations can be disabled on the memory for the majority of the signals while maintaining termination on the
strobes for proper clocking of the interface. The intent is the GDDR4 SDRAM would be operated at a slower condition
possibly with the DLL disabled while still meeting the AC timings of the DRAM.
This feature is available during normal operation but requires the memory controller meet the device specifications by
operating at a reduced frequency. Absolute frequencies supported by the GDDR4 SDRAM are vendor specific. Control
of the Low power mode is accomplished through the mode register field defined in Table 13. The Low Power
Termination mode can only be enabled when DQ termination is enabled in the ZQ/2 or ZQ/4 mode.
Table 14 Low Power Termination Control
LPTERM
0
Disabled
1
Enabled
Table 14 defines the termination states for the each signal group. The value EMRS[Termination] is meant to reference
the value defined in the EMRS register for the state of ODT termination for actual termination impedance.
Table 15 Termination Support
Rev. 1.2 /June. 2008
Signal Group
LPTERM Disabled
LPTERM Enabled
CLK, CLK#
N/A
N/A
Address
Enabled
Disabled
RAS#, CAS#, WE#,CS#
Enabled
Disabled
CKE#
Enabled
Disabled
RDQS[3:0]
EMRS[Termination]
Disabled
WDQS[3:0]
EMRS[Termination]
EMRS[Termination]
DQ[31:0], DM[3:0]
EMRS[Termination]
Disabled
51
HY5FS123235AFCP
OPERATING CONDITIONS
Absolute Maximum Ratings
Voltage on Vdd Supply
Relative to Vss................................................... -0.5V to +2.5V
Voltage on VddQ Supply
Relative to Vss .................................................. -0.5V to +2.5V
Voltage on Vref and Inputs
Relative to Vss .................................................. -0.5V to +2.5V
Voltage on I/O Pins
Relative to Vss .................................................. -0.5V to VddQ +0.5V
Storage Temperature (plastic) ............................ -55℃ to +150℃
Short Circuit Output Current ................................ 50mA
*Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 16 Capacitance
PARAMETER
SYMBOL
MIN
MAX
UNITS
Ci0
1.0
2.0
pF
Input Capacitance: Command, Address and CKE#
Ci1
1.0
2.5
pF
Input Capacitance: CK, CK#
Ci2
1.0
2.0
pF
Input/Output Capacitance: DQs, DQS, DM
Rev. 1.2 /June. 2008
NOTES
52
HY5FS123235AFCP
AC & DC Characteristics
All GDDR4 SDRAMs are designed for 1.8V typical voltage supplies but may optionally support 1.5V typical voltage sup
plies. The GDDR4 SDRAM vendor may restrict VDD and VDDQ combinations. The supported VDD and VDDQ will be
vendor specific. The interface of GDDR4 with 1.8V VDDQ will follow the POD18 specification and GDDR4 SDRAMs
with 1.5V VDDQ will follow the POD15 specification.
Table 17 DC Operating Conditions (Recommanded operating condition; 0°C <= TC <= 85°C)
POD18
Parameter
Symbol
Min
Typ
Max
Unit
Note
Device Supply Volatage/
Output Supply Voltage
VDD/
VDDQ
1.710
1.8
1.890
V
1
1.90
2.0
2.10
V
1
Reference Voltage
VREF
0.69
*VDDQ
0.71
*VDDQ
V
2
DC Input Logic HIGH Voltage
VIH(DC)
VREF
+0.15
DC Input Logic LOW Voltage
VIL(DC)
V
VREF
-0.15
V
Input Leakage Current
Any Input 0V <= VIN <= VDD
(All other pins not under test = 0V)
I1
-5
5
uA
Output Leakage Current
(DQs are disabled;
oV < = Vout <= VDDQ)
Ioz
-5
5
uA
0.76
V
Output Logic LOW Voltage
VOL(DC)
Notes:
1. GDDR4 SDRAM is designed to tolerate PCB designs with separate VDD and VDDQ power regulators.
2. AC noise in the system is estimated at 50mV pk-pk for the purpose of DRAM design
Table 18 AC Operating Conditions
Parameter
Symbol
AC Input Logic HIGH Voltage
VIH (AC)
AC Input Logic LOW Voltage
VIL (AC)
Rev. 1.2 /June. 2008
(Recommanded operating condition; 0°C <= TC <= 85°C)
POD18
Min
Typ
Max
VREF
+0.25
Unit
Note
V
VREF
-0.25
V
53
HY5FS123235AFCP
VDDQ
VOH
System Nolse Margin
(Power/Ground, Cross talk,
Signal Integrity Attenuation)
VIH(AC)
VIH(DC)
V REF
V REF
V REF
V REF
+
+
+
+
AC Noise
DC Error
DC Error
AC Noise
VIL(DC)
VIL(AC)
VIL(AC)-Provides Margin
Between VOL(MAX) and
VIL(AC)
VOL(MAX)
Output
Input
Figure 37: Voltage Waveform
Rev. 1.2 /June. 2008
54
HY5FS123235AFCP
Table 19 Clock Input Operating Conditions
Parameter
Symbol
POD18
Min
Typ
Max
Unit
Note
Clock Input Mid-Point
Voltage; CK and CK#
VMP (DC)
1.16
-
1.36
V
1, 2
Clock Input Differential
Voltage; CK and CK#
VID (DC)
0.22
-
VDDQ
V
1, 3
Clock Input Differential
Voltage; CK and CK#
VID (AC)
0.5
-
VDDQ + 0.5
V
3
Clock Input Voltage Level;
CK and CK#
VIN
0.42
-
VDDQ + 0.3
V
Clock Input Crossing Point
Voltage; CK and CK#
VIX (AC)
VREF - 0.15
VDDQ*0.70
VDDQ + 0.15
V
2
Notes :
1. For AC operations, all DC clock requirements must be satisfied as well.
2. The value of VIX is expected to equal 70% VDDQ for the transmitting device and must track variations in the
DC level of the same.
3. VID is the magnitude of the difference between the input level in CK and the input level on CK#. The input reference
level for signals other than CK and CK# is VREF.
4. The CK and CK# input reference level (for timing referenced to CK and CK#) is the point at which CK and CK# cross.
5. CK and CK# input slew rate must be greater than 3V/ns for VDDQ=1.8V(typ)
Maximum Clock Level
CK
VMP(DC)
VIX(AC)
VID(DC)
VID(AC)
CK#
Minimum Clock Level
Figure 38: Clock Input Waveform
Rev. 1.2 /June. 2008
55
HY5FS123235AFCP
Table 20 IDD SPECIFICATIONS AND CONDITIONS
(Recommanded operating condition; 0°C <= TC <= 85°C)
PARAMETER/CONDITION
Unit:mA
SYMBOL
-06*
-07*
-08
-09
NOTES
OPERATING CURRENT: One bank; Active Precharge; tRC
(MIN); tCK= tCK (MIN);
DQ, DM, and DQS inputs changing twice per clock cycle;
Address and control inputs changing once per clock cycle;
IDD0
880
800
680
620
23
OPERATING CURRENT: One bank; Active Read Precharge;
Burst = 8; tRC (MIN); tCK = tCK (MIN); I(OUT) = 0mA;
Address and control inputs changing once per clock cycle;
WL = 4
IDD1
800
730
590
540
23
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks
idle; Power-down mode;
tCK = tCK (MIN); CKE# = HIGH
IDD2P
270
260
240
230
IDLE STANDBY CURRENT: CS# = HIGH;
All banks idle; tCK = tCK (MIN); CKE# = LOW; inputs
changing once per clock cycle
IDD2N
600
550
480
440
ACTIVE POWER-DOWN STANDBY CURRENT: One bank
active; Power-down mode;
tCK = tCK (MIN); CKE# = HIGH; WL=4
IDD3P
280
270
250
240
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE# = LOW;
One bank; Active Precharge;
tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
IDD3N
710
650
570
530
OPERATING CURRENT: Burst = 8; Reads; Continuous
burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); Iout =
0mA; WL = 4
IDD4R
1450
1300
1100
1000
OPERATING CURRENT: Burst = 8; Writes; Continuous
burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM,
and DQS inputs changing twice per clock cycle; WL = 4
IDD4W
1320
1210
1020
920
AUTO REFRESH CURRENT: tRC = tRFC(min);
All banks active
IDD5
1050
970
830
760
SELF REFRESH CURRENT: CKE# = HIGH
IDD6
35
35
30
30
Operating bank interleave read current
IDD7
1020
940
810
740
23
23
***) 1. Measured condition is Outputs open and ODT off.
2. IDD values of (-06*) and (-07*) are measured at 2.0V and the others are measures at 1.8V.
Rev. 1.2 /June. 2008
56
HY5FS123235AFCP
Table 21 AC Timings
(Recommanded operating condition; 0°C <= TC <=
-0685°C)
PARAMETER
SYMBOL
DQS output access time from CK/CK
-07
-08
-09
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
unit
notes
tDQSCK
-0.14
+0.14
-0.16
+0.16
-0.19
+0.19
-0.20
+0.20
ns
Clock high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
29
Clock low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
29
CL=20
0.6
2.5
-
-
-
-
-
-
ns
0.7
2.5
-
-
-
-
ns
0.8
2.5
Clock cycle time
tCK
CL=18
CL=17
CL=15
tCK
0.11
0.12
0.12
0.13
ns
25, 30
DQ and DM input hold time
tDH
0.11
0.12
0.12
0.13
ns
25, 30
Active terminaton
setup time
tATS
9
9
9
10
ns
Active termination
Hold time
tATH
9
9
9
10
ns
WDQS input high-level width
tDQSH
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
WDQS input low-level width
tDQSL
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
RDQS - DQ skew
tDQSQ
-0.10
0.10
-0.11
0.11
-0.11
0.11
-0.12
0.12
ns
tDQSS
WL-0.2
WL+
0.2
WL-0.2
WL+
0.2
WL-0.2
WL+
0.2
WL-0.2
WL+
0.2
tCK
RDQS falling edge to CK setup time
tDSS
0.25
0.25
0.25
0.25
tCK
RDQS falling edge from CK hold time
tDSH
0.25
0.25
0.25
0.25
tCK
tHP
0.45
0.45
0.45
0.45
tJ
-
DQ & RDQS high-impedance time
from CK/CK#
tHZ
-0.18
-018
-0.2
-0.2
ns
19
DQ & RDQS low-impedance time
from CK/CK#
tLZ
-0.18
-018
-0.2
-0.2
ns
19
Address and control input setup time
tIS
0.18
0.18
0.20
0.23
ns
17
Address and control input hold time
tIH
0.18
0.18
0.20
0.23
ns
17
Address and control input pulse width
tIPW
0.40
0.40
0.50
0.55
ns
38
MODE REGISTER SET command
period
tMRD
4
4
4
4
tCK
tDL
7K
7K
7K
7K
tCK
DLL enable to READ command delay
Rev. 1.2 /June. 2008
-
0.03
-
-
-
2~7
tDS
0.03
2~7
2~7
tWL
Jitter over 1~6 clock cycle error
-
ns
ns
DQ and DM input setup time
Half strobe period
2~7
2.5
Write Latency
Write command to 1st WDQS
latching transition
-
0.9
9,
10,
31,
36
0.03
-
tCK
0.03
25
32
tCK
57
HY5FS123235AFCP
Table 21. AC Timings
PARAMETER
SYMBOL
CTIVE to PRECHARGE command period
CTIVE to ACTIVE command period
-06
-07
-08
-09
unit note
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tRAS
42
70Kns
36
70Kns
34
70Kns
30
70Kns
tRC
62
53
50
44
tCK
UTO REFRESH command period
tRFC
73
63
60
53
tCK
EFRESH to REFRESH command interval
tREFC
32
32
32
32
ms
verage periodic refresh interval
tREFI
3.9
3.9
3.9
3.9
us
tRCDR
21
18
17
15
tCK
CTIVE to READ or WRITE delay
RECHARGE command period
tCK
tRCDW
12
11
9
8
tCK
tRP
20
17
16
14
tCK
DQS Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS Read postamble
tRPST
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
CTIVE bank A to ACTIVE bank B delay
olumn address to column address delay
xit Power-down
tRRD
12
11
9
8
tCK
tCCD(Rank1)
4
4
4
4
tCK
tCCD(Rank2)
6
6
6
6
tCK
tPDEX
9
+tIS
8
+tIS
7
+tIS
6
+tIS
tCK
33
39
Write preamble
tWPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK 21, 2
Write postamble
tWPST
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
WRITE recovery time
tWR
20
17
16
14
nternal write to Read command delay
tWTR
12
10
9
8
tCK
ank restriction rolling window
tFAW
6*RRD
6*RRD
6*RRD
6*RRD
tCK
xit Self refresh to non-READ command
tXSNR
150
130
110
100
tCK
xit SELF REFRESH to READ command
tXSRD
7K
7K
7K
7K
tCK
Timing Reference Load
tCK
60 Ohms
I/O
Z0 = 40 Ohms
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2/June. 2008
58
HY5FS123235AFCP
Table 21. AC Timings
PARAMETER
SYMBOL
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period
-06
-07
-08
-09
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tRAS
42
70Kns
36
70Kns
34
70Kns
30
70Kns
tRC
62
53
50
unit notes
tCK
44
tCK
AUTO REFRESH command period
tRFC
73
63
60
53
tCK
REFRESH to REFRESH command interval
tREFC
32
32
32
32
ms
Average periodic refresh interval
tREFI
3.9
3.9
3.9
3.9
us
tRCDR
21
18
17
15
tCK
tRCDW
12
11
9
8
tCK
tRP
20
17
16
14
RDQS Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
RDQS Read postamble
tRPST
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
ACTIVE to READ or WRITE delay
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B delay
33
tCK
tRRD
12
11
9
8
tCK
tCCD(Rank1)
4
4
4
4
tCK
tCCD(Rank2)
6
6
6
6
tCK
Exit Power-down
tPDEX
9
+tIS
8
+tIS
7
+tIS
6
+tIS
tCK
Write preamble
tWPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK 21, 22
Write postamble
tWPST
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
WRITE recovery time
tWR
20
17
16
14
Internal write to Read command delay
tWTR
12
10
9
8
tCK
Bank restriction rolling window
tFAW
6*RRD
6*RRD
6*RRD
6*RRD
tCK
Exit Self refresh to non-READ command
tXSNR
150
130
110
100
tCK
Exit SELF REFRESH to READ command
tXSRD
7K
7K
7K
7K
tCK
Column address to column address delay
Timing Reference Load
39
tCK
60 Ohms
I/O
Z0 = 40 Ohms
Rev. 1.2 /June. 2008
59
HY5FS123235AFCP
Note
1. All voltages referenced to VSS.
2. Tests for AC timing may be conducted at nominal supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage and temperature range specified.
3. Outputs measured with equivalent load (vendor specific) terminated with 60ohms to VDDQ.
4. All parameters assume proper device initialization.
5. AC and DC input and output voltage levels are defined in the section for Electrical Characteristics and AC/DC operating conditions.
6. AC timing and Idd tests may use a Vil-to-Vih swing of up to 1.0V in the test environment, but input timing is still referenced to
Vref (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under
normal use conditions. The minimum slew rate for the input signals used to test the device is 3 V/ns in the range between Vil(AC)
and Vih(AC).
7. The AC and DC input level specifications are a pseudo open drain design for improved high-speed signaling.
8. Vref is expected to equal 70 percent of VddQ for the transmitting device and to track variations in the DC level of the same.
Peak-to-peak noise on Vref may not exceed ± 2 percent of the DC value. Thus, from 70% of VddQ, Vref is allowed ± 25mV for
DC error and an additional ± 25mV for AC noise.
9. GDDR4 SDRAMs are required to support a minimum clock frequency of 400MHz for normal DLL-on operation, regardless of the
speed bin of the device.
10. If users need operation below 400MHz, they should use the DLL-off mode of the device.
11. Vid is the magnitude of the difference between the input level on CK and the input level on CK#.
12. The value of Vix is expected to equal 70 percent of VddQ for the transmitting device and must track variations in the DC level of
the same.
13. Idd is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at minimum CAS
latency and does not include the on-die termination current. Outputs are open during Idd measurements.
14. Enables on-chip refresh and address counters.
15. Idd specifications are tested after the device is properly initialized.
16. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference
level for signals other than CK/CK# is Vref.
17. Command/Address input slew rate = 3 V/ns. If the slew rate is less than 3 V/ns, timing is no longer referenced to the midpoint
but to the Vil(AC) maximum and Vih(AC) minimum points.
18. Inputs are not recognized as valid until Vref stabilizes. Exception: during the period before Vref stabilizes, MF, CKE# <= 0.3 x
VddQ is recognized as LOW.
19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to
a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
20. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
21. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus
turnaround.
22. It is recommended that WDQS be valid (HIGH or LOW) on or before the WRITE command.
23. MIN (tRC or tRFC) for Idd measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective
parameter. tRAS (MAX) for Idd measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device.
25. Referenced to each output group: RDQS0 with DQ0–DQ7, RDQS1 with DQ8–DQ15, RDQS2 with DQ16–DQ23, and RDQS with
DQ24–DQ31.
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
26. This limit is actually a nominal value and does not result in a fail value. CKE# is LOW during REFRESH command period
(tRFC [MIN]) else CKE# is HIGH (e.g., during standby).
27. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in
order to maintain a valid level. The inputs require the AC value to be achieved during signal transition edge, and the drive
should achieve the same slew rate through the AC values.
28. The input capacitance per pin group will not differ by more than this maximum amount for any given device.
29. CK and CK# input slew rate must be >= 3 V/ns.
30. DQ and DM input slew rates must not deviate from WDQS by more than 10 percent. If the DQ/DM/WDQS slew rate is less than
3 V/ns, timing is no longer referenced to the midpoint but to the Vil(AC) maximum and Vih(AC) minimum points.
31. The clock is allowed up to ± 90ps of jitter. Each timing parameter is allowed to vary by the same amount.
32. tHP (MIN) is the lesser of tDQSL minimum and tDQSH minimum actually applied to the device CK and CK# inputs, collectively
during bank active.
33. For READs and WRITEs with auto precharge the GDDR4 device will hold off the internal PRECHARGE command until tRAS (MIN)
has been satisfied.
34. The last rising edge of WDQS after the write postamble must be driven high by the controller. WDQS cannot be pulled high by
the on-die termination alone. For the read postamble the GDDR4 will drive the last rising edge of the read postamble.
35. The voltage levels used are derived from the referenced test load. In practice, the voltage levels obtained from a properly
terminated bus will provide significantly different voltage values.
36. Vih overshoot: Vih (MAX) = VddQ + 0.5V for a pulse width <= 500ps and the pulse width cannot be greater than 1/3 of
the cycle rate. Vil undershoot: Vil (MIN) = 0.0V for a pulse width <= 500ps and the pulse width cannot be greater than 1/3 of
the cycle rate.
37. The DLL must be reset when changing the frequency, follFowed by tDL.
38. The tIPW parameter defines the min pulse width for command/address. This is used to tell the input receiver designer the
max bandwidth to design to.
39. When read to read command is entered in Rank=2, the tCCD is 6clocks. And other cases are all 4 clocks.
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
1.5V I/O Driver Value
The Driver and Termination impedances are derived from the following test conditions under worst case process
corners:
1. Nominal 1.5V (VDD/VDDQ)
2. Power the GDDR4 device and calibrate the output drivers and termination to eliminate process variation at 25℃.
3. Reduce temperature to 10℃ recalibrate.
4. Reduce temperature to 0℃ and take the fast corner measurement
5. Raise temperature to 75℃ and recalibrate
6. Raise temperature to 85℃ and take the slow corner measurement
7. Reiterate 2 to 6 with VDD/VDDQ 1.455V,
8. Reiterate 2 to 6 with VDD/VDDQ 1.545V
9. All obtained Driver and Termination IV characteristics have to be bounded by the specified MIN and MAX IV
characteristics
Table 22 1.5V I/O Impedances
Pull-Down Characteristic at 40 ohms
Pull-up/Termination Characteristic at 60 ohms
Voltage (V)
MIN (mA)
MAX (mA)
Voltage (V)
MIN (mA)
MAX (mA)
0.1
2.25
2.75
0.1
-1.50
-1.83
0.2
4.50
5.50
0.2
-3.00
-3.67
0.3
6.75
8.25
0.3
-4.50
-5.50
0.4
9.00
11.00
0.4
-6.00
-7.33
0.5
11.25
13.75
0.5
-7.50
-9.17
0.6
13.50
16.50
0.6
-9.00
-11.00
0.7
15.75
19.25
0.7
-10.50
-12.83
0.8
18.00
22.00
0.8
-12.00
-14.67
0.9
20.25
24.75
0.9
-13.50
-16.50
1.0
22.50
27.50
1.0
-15.00
-18.33
1.1
24.75
30.25
1.1
-16.50
-20.17
1.2
27.00
33.00
1.2
-18.00
-22.00
1.3
29.25
35.75
1.3
-19.50
-23.83
1.4
31.50
38.50
1.4
-21.00
-25.67
1.5
33.75
41.25
1.5
-22.50
-27.50
Note: These values are targeted values are for the design. The design does not need to meet these values
but it is recommended that the design fits these curves.
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
1.8V I/O Driver Value
The Driver and Termination impedances are derived from the following test conditions under worst case process
corners:
1. Nominal 1.8V (VDD/VDDQ)
2. Power the GDDR4 device and calibrate the output drivers and termination to eliminate process variation at 25℃.
3. Reduce temperature to 10℃ recalibrate.
4. Reduce temperature to 0℃ and take the fast corner measurement
5. Raise temperature to 75℃ and recalibrate
6. Raise temperature to 85℃ and take the slow corner measurement
7. Reiterate 2 to 6 with VDD/VDDQ 1.710V
8. Reiterate 2 to 6 with VDD/VDDQ 1.890V
9. All obtained Driver and Termination IV characteristics have to be bounded by the specified MIN and MAX IV
characteristics
Table 23 1.8V I/O Impedances
Pull-Down Characteristic at 40 ohms
Voltage (V)
MIN (mA)
Pull-up/Termination Characteristic at 60 ohms
MAX (mA)
Voltage (V)
MIN (mA)
MAX (mA)
0.1
2.25
2.75
0.1
-1.50
-1.83
0.2
4.50
5.50
0.2
-3.00
-3.67
-5.50
0.3
6.75
8.25
0.3
-4.50
0.4
9.00
11.00
0.4
-6.00
-7.33
0.5
11.25
13.75
0.5
-7.50
-9.17
0.6
13.50
16.50
0.6
-9.00
-11.00
0.7
15.75
19.25
0.7
-10.50
-12.83
0.8
18.00
22.00
0.8
-12.00
-14.67
0.9
20.25
24.75
0.9
-13.50
-16.50
1.0
22.50
27.50
1.0
-15.00
-18.33
1.1
24.75
30.25
1.1
-16.50
-20.17
1.2
27.00
33.00
1.2
-18.00
-22.00
1.3
29.25
35.75
1.3
-19.50
-23.83
1.4
31.50
38.50
1.4
-21.00
-25.67
1.5
33.75
41.25
1.5
-22.50
-27.50
1.6
36.00
44.00
1.6
-24.00
-29.34
1.7
38.25
46.75
1.7
-25.50
-31.17
1.8
40.50
49.50
1.8
-27.00
-33.00
Note: These values are target values for the design. The desigen does not need to meet these values
but it is redommended that the design fits these curves.
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
2.0V I/O Driver Value
The Driver and Termination impedances are derived from the following test conditions under worst case process
corners:
1. Nominal 2.0V (VDD/VDDQ)
2. Power the GDDR4 device and calibrate the output drivers and termination to eliminate process variation at 25℃.
3. Reduce temperature to 10℃ recalibrate.
4. Reduce temperature to 0℃ and take the fast corner measurement
5. Raise temperature to 75℃ and recalibrate
6. Raise temperature to 85℃ and take the slow corner measurement
7. Reiterate 2 to 6 with VDD/VDDQ 1.90V
8. Reiterate 2 to 6 with VDD/VDDQ 2.10V
9. All obtained Driver and Termination IV characteristics have to be bounded by the specified MIN and MAX IV
characteristics
Table 24 2.0V I/O Impedances
Pull-Down Characteristic at 40 ohms
Pull-up/Termination Characteristic at 60 ohms
Voltage (V)
MIN (mA)
MAX (mA)
Voltage (V)
MIN (mA)
MAX (mA)
0.1
2.25
2.75
0.1
-1.50
-1.83
0.2
4.50
5.50
0.2
-3.00
-3.67
0.3
6.75
8.25
0.3
-4.50
-5.50
0.4
9.00
11.00
0.4
-6.00
-7.33
0.5
11.25
13.75
0.5
-7.50
-9.17
0.6
13.50
16.50
0.6
-9.00
-11.00
0.7
15.75
19.25
0.7
-10.50
-12.83
0.8
18.00
22.00
0.8
-12.00
-14.67
0.9
20.25
24.75
0.9
-13.50
-16.50
1.0
22.50
27.50
1.0
-15.00
-18.33
1.1
24.75
30.25
1.1
-16.50
-20.17
1.2
27.00
33.00
1.2
-18.00
-22.00
1.3
29.25
35.75
1.3
-19.50
-23.83
1.4
31.50
38.50
1.4
-21.00
-25.67
1.5
33.75
41.25
1.5
-22.50
-27.50
1.6
36.00
44.00
1.6
-24.00
-29.34
1.7
38.25
46.75
1.7
-25.50
-31.17
1.8
40.50
49.50
1.8
-27.00
-33.00
1.9
42.00
50.03
1.9
-28.99
-33.77
2.0
43.52
52.46
2.0
-30.22
-35.44
Note: These values are target values for the design. The desigen does not need to meet these values
but it is redommended that the design fits these curves.
Rev. 1.2 /June. 2008
64
HY5FS123235AFCP
POD I/O SYSTEM
The POD I/O system is optimized for small systems with data rates exceeding 2.0 Gbps. The system allows a single
Master device to control one, two or four slave devices. The POD driver uses a 40 Ohm output impedance that drives
into a 60 Ohm equivalent terminator tied to VDDQ. Single, dual and quad load systems are shown as follows:
VDDQ
Data Bit
240 Ohm
240 Ohm
Data Bit
120 Ohm
120 Ohm
Data Bit
60 Ohm
40 Ohm
240 Ohm
240 Ohm
4 Slaves
VDDQ
40 Ohm
2 Slaves
VDDQ
40 Ohm
1 Slave
Figure 39: System Configurations
The POD Master I/O cell is comprised of a 40 Ohm driver and terminator of 60 Ohms. The Master POD cell’s terminator
is disabled when the output driver is enabled. The basic cell is shown in Figure 40.
VDDQ
60 Ohm Terminator
Enabled when receiving
Output Data
Output Enable
DQ
VSSQ
60 Ohm pull-up and 40 Ohm pull-down
when transmitting
Figure 40: Master I/O Cell
Rev. 1.2 /June. 2008
65
HY5FS123235AFCP
The POD Slave I/O cell is comprised of a 40 ohm driver and programmable terminator of 60, 120 or 240 ohms. The
Slave POD cells terminator is disabled when the output driver is enabled or any other Slave output driver is enabled.
The basic cell is shown in Figure 41.
VDDQ
60 Ohm Terminator
Enabled when receiving
Read to other Slave
Output Data
Output Enable
DQ
VSSQ
60 Ohm pull-up and 40 Ohm pull-down
when transmitting
Figure 41: Slave I/O Cell
The POD Master and Slave I/O cells are intended to have their driver and terminators combined together to minimize
the area needed to implement the cell and reduce input capacitance. This is possible by using six 240 Ohm driver/
terminator sub cells that are connected in parallel. The combinations used are as follows.
Table 25 POD I/O Sub Cells
# of 240 ohm Sub Cells Enabled
Resulting Impedance
Use
1
240 Ohms
4 Slave loads
2
120 Ohms
2 Slave loads
4
60 Ohms
1 Slave load or Master terminator
6
40 Ohms
Master or Slave Driver
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
To ensure that the target impedance is achieved the POD I/O cell is designed to be calibrated to an
external 1% precision resistor.
The following procedure can be used to calibrate the cell:
1.) First calibrate the PMOS device against a 240 Ohm resister to VSS via the ZQ pin as illustrated in Figure 42.
• Set Strength Control to minimum setting
• Increase drive strength until comparator detects data bit is greater than VDDQ/2
• PMOS device is calibrated to 240 Ohms
2.) Then calibrate the NMOS device against the calibrated 240 Ohm PMOS device as illustrate in Figure 43.
• Set Strength Control to minimum setting
• Increase drive strength until comparator detects data bit is less than VDDQ/2
• NMOS device is now calibrated to 240 Ohms
VDDQ
S tre n g th c o n tro l [ 2 : 0 ]
3
C o m p a ra to r
240 O hm s
M a tc h
V D D Q /2
VSSQ
W h e n M a tc h P M O S le g is c a lib ra te d to 2 4 0 o h m s
Figure 42: PMOS Calibration
VDDQ
C a lib r a t e d P M O S S t r e n g t h
3
C o m p a ra to r
M a tc h
V D D Q /2
S tre n g th c o n tro l [2 :0 ]
3
VSSQ
Figure 43: NMOS Calibration
Rev. 1.2 /June. 2008
67
HY5FS123235AFCP
PACKAGE SPECIFICATION
Ball-out
1
2
3
4
VDDQ
VDD
VSS
ZQ
VSSQ
DQ0
DQ1
VDDQ
DQ2
VSSQ
5
6
7
8
9
10
11
12
A
MF
VSS
VDD
VDDQ
VSSQ
B
VSSQ
DQ9
DQ8
VSSQ
DQ3
VDDQ
C
VDDQ
DQ11
DQ10
VDDQ
WDQS0
RDQS0
VSSQ
D
VSSQ
RDQS1
WDQS1
VSSQ
VDDQ
DQ4
DM0
VDDQ
E
VDDQ
DM1
DQ12
VDDQ
VDD
DQ6
DQ5
VSSQ
F
VSSQ
DQ13
DQ14
VDD
VSS
VSSQ
DQ7
CAS#
G
CS#
DQ15
VSSQ
VSS
VDDQ
RAS#
CKE#
BA0
A1
H
BA1
A5
WE#
RFM
VDDQ
VSSA
RFU
PERR#
VREFC
J
VREFD
/NC
CK#
CK
VSSA
VDDA
A10
A0
A12
A2
VSS
K
VSS
BA2
A6
A8
A4
VDDA
VSS
VSSQ
DQ25
A11
A3
L
A9
A7
DQ17
VSSQ
VSS
VDD
DQ24
DQ27
VSSQ
M
VSSQ
DQ19
DQ16
VDD
VDDQ
DQ26
DM3
VDDQ
N
VDDQ
DM2
DQ18
VDDQ
VSSQ
WDQS3
RDQS3
VSSQ
P
VSSQ
RDQS2
WDQS2
VSSQ
VDDQ
DQ28
DQ29
VDDQ
R
VDDQ
DQ21
DQ20
VDDQ
VSSQ
DQ30
DQ31
VSSQ
T
VSSQ
DQ23
DQ22
VSSQ
VDDQ
VDD
VSS
SEN
U
RESET
VSS
VDD
VDDQ
Figure 44: GDDR4 SDRAM 136ball BGA Ballout
Note: Top View, MF = LOW
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
Signals
Table 26 Ballout Description
FBGA BALL-OUT
SYMBOL
TYPE
DESCRIPTION
J10, J11
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK#.
H3
CKE#
Input
Clock Enable: CKE# LOW activates and CKE# HIGH deactivates
the internal clock, input buffers, and output drivers. Taking
CKE# HIGH provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE# is synchronous for POWERDOWN entry and exit, and for SELF REFRESH entry. CKE# is
asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE# must be maintained LOW throughout read and
write accesses. Input buffers (excluding CK, CK#, and CKE#)
are disabled during POWER- DOWN. Input buffers (excluding
CKE#) are disabled during SELF REFRESH.
G9
CS#
Input
Chip Select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH. CS# provides for
external bank selection on systems with multiple banks. CS# is
considered part of the command code.
H2, G4, H10
RAS#, CAS#, WE#
Input
Command Inputs: RAS#, CAS#, and WE# (along with CS#)
define the command being entered.
E(3, 10), N(3, 10)
DM0-DM3
Input
Input Data Mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with
that input data during a WRITE access. DM is sampled on the
rising and falling edges of WDQS. DM is used as the flag for
READ DBI
Miltiplexed with Address
H(4, 9), K10
BA0-BA2
Input
Bank Address Inputs: BA0, BA1 and BA2 define to which bank
an ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Miltiplexed with Bank
Address
H(4, 9), K10
A0-A12
Input
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A8) for READ/WRITE commands, to select one location out of
the memory array in the respective bank. A8 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one bank (A8 LOW, bank selected by BA0-BA2) or all
banks (A8 HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command. BA0-BA2 define
which mode register (mode register or specific extended mode
register) is loaded during the MODE REGISTER SET command.
B(2, 3), C(2,3), E2,
F(2, 3), G3
DQ0-7
I/O
B(10, 11), C(10, 11),
E11, F(10, 11), G10
DQ8-15
I/O
L10, M(10, 11), N11,
R(10, 11), T(10, 11)
DQ16-23
I/O
Miltiplexed with other
Address
K(2, 3, 11), L(4, 9)
Rev. 1.2 /June. 2008
Data Input/Output
Data Input/Output
Data Input/Output
69
HY5FS123235AFCP
Table 27 Ballout Description
FBGA BALL-OUT
SYMBOL
TYPE
L3, M(2, 3) N2, R(2, 3), T(2,3)
DQ24-31
I/O
D(3, 10), P(3, 10)
RDQS(0-3)
Output
D(2, 11), P(2, 11)
WDQS(0-3)
Input
DESCRIPTION
Data Input/Output
READ Data Strobe: Output with read data. RDQS is edge-aligned
with read data. RDQS is used as the flag for WRITE DBI.
WRITE Data strobe: Input with write data.
WDQS is center-aligned to the input data.
J2
RFU
A(1, 12), C(1, 4, 9, 12), (E1, 4,
9, 12), H(1,9), N(1, 4, 9, 12),
R(1, 4, 9, 12), U(1, 12)
VddQ
Supply
Reserved for Future Use
B(1, 4, 9, 12), D(1, 4, 9, 12),
F(4,9), G(2, 11), L(2, 11),
M(4,9), P(1, 4, 9, 12),
T(1, 4, 9, 12)
VssQ
Supply
A(2, 11), F(1, 12), K(1, 12)
M(1, 12), U(2,11)
Vdd
Supply
A(3, 10), G(1, 12), J(1, 12),
K(4, 9), L(1,12), U(3,10)
Vss
Supply
J(4, 9)
Vref
Supply
Reference Voltage.
J3
PERR#
Output
Parity error
DQ Power Supply: +1.5V ± 0.045V or +1.8V ± 0.09V or
+2.0V ± 0.1V. Isolated on the die for improved noise immunity.
DQ Ground: Isolated on the die for improved noise immunity.
Power Supply: +1.5V ± 0.045V or +1.8V ± 0.09V or
+2.0V ± 0.1V
Ground.
A9
MF
H11
RFM
Reference
When the MF ball is tied LOW, RFM receiver is disabled and it
recommended to be driven to a static LOW state. However, either
static HIGH or floating state on this pin will not cause any
problem for the GDDR4 SGRAM.When the MF ball is tied HIGH,
RAS(H2) becomes RFM due to mirror function and the receiver is
disabled. It is recommended to be driven to a static LOW state.
However, either static HIGH or floating state on this pinwill not
cause any problem. for the GDDR4 SGRAM
A4
ZQ
Reference
External Reference Pin for autocalibration
U4
SEN
Input
Scan enable. Must tie to the ground when not in use.
U9
RESET
Input
Reset Pin. The RESET pin is a VDDQ CMOS input.
Rev. 1.2 /June. 2008
Mirror Function for clamshell mounting of DRAMs
70
HY5FS123235AFCP
Mirror Function
The GDDR4 SDRAM provides a mirror function (MF) ball to change the physical location of the control lines and all
address lines assisting in routing devices back to back. The MF ball will affect RAS#, CAS#, WE#, CS# ,CKE#, A0, A1,
A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, BA0, BA1 AND BA2 and only detects a DC input. The MF ball should be
tied directly to VSS or VDD depending on the control line orientation desired.
Table 27 illustrates the pin location in relation to the polarity of the MF pin. The MF pin does not transition under
normal operation. MF can only transition when either the RESET or SEN pin are asserted.
Table 28 Mirror Function Signal Mapping
PIN
Rev. 1.2 /June. 2008
MF LOGIC STATE
LOW
HIGH
RAS#
H2
H11
CAS#
G4
G9
WE#
H10
H3
CS#
G9
G4
CKE#
H3
H10
A0/A10
K2
K11
A1/BA0
H4
H9
A2/A12
K3
K10
A3/A11
L4
L9
A4/A8
K11
K2
A5/BA1
H9
H4
A6/BA2
K10
K3
A7/A9
L9
L4
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HY5FS123235AFCP
Package Dimensions
Figure 45: X -Y D im ensions
14
16 x 0.8= 12.8
B 2)
2)
1)
11x 0.8=8.8
0.8
0.8
11
3)
Stand-off 0.350mm +/-0.050
1) Bad Unit M arking (BUM ) - position and shape prelim inary
2) M iddle of Package
3) Package O rientation M ark A 1
hpackage 1.100mm +/-0.100
A
Figure 46: Package H eight
Table 29 Package Height Parameter
nominal
variation
hpackage
1.100 mm
+/- 0.100 mm
stand-off
0.350 mm
+/- 0.050mm
Note
1) The GDDR4 package height specification is compliant to MO-207, DR-2 applying Note 22.
Rev. 1.2 /June. 2008
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HY5FS123235AFCP
VENDOR ID, PARITY & SCAN
Vendor ID
The Manufacturers Vendor ID Code, V, is selected by issuing a MODE REGISTER SET command to EMRS(1) with bit
A11 set to 1, and bits A0-A10 and A12 set to the desired values. The DRAM Info command of EXTENDED MODE
REGISTER SET 3 must also be set to Vendor ID by setting bits A6 and A7 to 0. When the Vendor ID function is enabled
the GDDR4 SDRAM will provide its manufacturers vendor ID code on DQ[3:0] and revision identification on DQ[7:4].
The code will be driven onto the DQ bus after the EMRS that set A11 to 1. The DQ bus will be continuously driven until
an EMRS write sets A11 back to 0. The DQ bus will be in a Hi-Z state after tWRIDOFF max. The code can be sampled
by the controller after waiting tWRIDON max and before tWRIDOFF min.
Table 30 Vendor IDs
VENDOR
Rev. 1.2 /June. 2008
DQ(3:0)
Reserved
0
Samsung
1
Infineon
2
Elpida
3
Etron
4
Nanya
5
Hynix
6
Mosel
7
Winbond
8
ESMT
9
Reserved
A
Reserved
B
Reserved
C
Reserved
D
Reserved
E
Micron
F
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HY5FS123235AFCP
CK#
CK
T0
T1
T2
T5
T6
T7
T10
T11
T12
T13
T16
T17
MRS
NOP
NOP
MRS
NOP
NOP
NOP
NOP
MRS
NOP
NOP
NOP
CKE#
COMMAND NOP
DQ
Vendor Code Rev ID
A8, A10, A12,
A4, A0, A2
CODE
CODE
CODE
CODE
CODE
CODE
A9
A7
CODE
A7 = L
CODE
CODE
CODE
CODE
A11
A3
CODE
CODE
A11 = H
CODE
A11 = L
CODE
BA0, BA1, BA2,
A1, A5, A6
BA0,BA1=H
BA2=L
A1,A5=CODE
A6=L
BA0=H
BA1,BA2=L
CODE
BA0=H
BA1,BA2=L
CODE
High
RDQS
High
WDQS
tWRIDOFFmin
tMRD
tWRIDONmax
DON’T CARE
Figure 47: Vendor ID Timing
Note
1. Address is received on two consecutive rising edges of CK
Rev. 1.2 /June. 2008
74