Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM Document Title 4Bank x 4M x 32bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Feb. 2004 Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / Feb. 2004 1 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM DESCRIPTION The Hynix Mobile SDR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs. The Hynix HY5Y7A2DLM-HF is a 536,870,912bit CMOS Synchronous Dynamic Random Access Memory. It is organized as 4banks of 4,194,304x32. The Mobile SDR provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Mobile SDR also provides for special programmable options including Partial Array Self Refresh of a quarter bank, a half bank, 1bank, 2banks, or all banks, Temperature Compensated Self Refresh of 15, 45, 70, or 85 degrees oC. A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule). Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power reduction by removing power to the memory array within each SDR. By using this feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility. FEATURES ● Standard SDR Protocol ● Internal 4bank operation ● Voltage : VDD = 3.0V, VDDQ = 3.0V ● LVCMOS compatible I/O Interface ● Low Voltage interface to reduce I/O power ● ● ● Low Power Features - PASR(Partial Array Self Refresh) -TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) - Deep Power Down Mode Programmable CAS latency of 1, 2 or 3 90 Ball FBGA Package - HY5Y7A2DLM-HF - HY5Y7A2DLMP-HF : Lead : Lead Free ORDERING INFORMATION Part Number Clock Frequency CAS Latency Organization Interface HY5Y7A2DLM(P)-HF 133MHz 3 4banks x 4Mb x 32 LVCMOS This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / Feb. 2004 2 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM Ball CONFIGURALATION 1 2 3 A DQ26 DQ24 B DQ28 C 7 8 9 VSS VDD DQ23 DQ21 VDDQ VSSQ VDDQ VSSQ DQ19 VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ E VDDQ DQ31 NC NC DQ16 VSSQ F VSS DQM3 A3 A2 DQM2 VDD G A4 A5 A6 A10 A0 A1 H A7 A8 A12 NC BA1 A11 J CLK CKE A9 BA0 /CS /RAS K DQM1 NC NC /CAS /WE DQM0 L VDDQ DQS VSS VDD DQ7 VSSQ M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 R DQ13 DQ15 VSS VDD DQ0 DQ2 Rev. 0.1 / Feb. 2004 4 5 TOP View 6 3 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM PAD FUNCTION DESCRIPTIONS SYMBOL TYPE CLK INPUT Clock : The system clock input. All other inputs are registered to the SDR on the rising edge of CLK CKE INPUT Clock Enable : Controls internal clock signal and when deactivated, the SDR will be one of the states among power down, suspend or self refresh CS INPUT Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM BA0, BA1 INPUT Bank Address : Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A12 INPUT Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 RAS, CAS, WE INPUT Command Inputs : RAS, CAS and WE define the operation Refer function truth table for details UDQM, LDQM INPUT Data Mask:Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ31 I/O VDD/VSS SUPPLY Power supply for internal circuits VDDQ/VSSQ SUPPLY Power supply for output buffers NC - Rev. 0.1 / Feb. 2004 DESCRIPTION Data Input/Output:Multiplexed data input/output pin No connection : These pads should be left unconnected 4 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x 32 I/O Low Power Synchronous DRAM PASR, TCSR Extended Mode Register Self refresh logic & timer Internal Row Counter 4Mx32 BANK 3 CLK Refresh WE Column Active 4Mx32 BANK 0 Memory Cell Array Column Pre Decoder U/LDQM DQ0 I/O Buffer & Logic CAS 4Mx32 BANK 1 Sense AMP & I/O Gate RAS State Machine CS Row decoders Row decoders Row decoders Row decoders CKE 4Mx32 BANK 2 Row Pre Decoder Row Active DQ31 Column decoders Column Add Counter Bank Select A0 Burst Counter Burst Length A12 BA1 Address Buffers A1 Address Register Mode Register CAS Latency Data Out Control BA0 Rev. 0.1 / Feb. 2004 5 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 BA0 A11 A10 A9 A8 A7 0 0 0 0 OP Code 0 0 A6 A5 A4 CAS Latency OP Code A3 A2 BT A1 A0 Burst Length Burst Type A9 Write Mode A3 Burst Type 0 Burst Read and Burst Write 0 Sequential 1 Burst Read and Single Write 1 Interleave CAS Latency Burst Length A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 0 1 0 1 1 0 1 0 A2 A1 A0 1 0 0 0 2 0 1 3 0 Reserved 1 Burst Length A3 = 0 A3=1 0 1 1 0 1 2 2 0 1 0 4 4 0 1 1 8 8 Reserved 1 0 0 Reserved Reserved Reserved 1 1 0 Reserved 1 0 1 Reserved 1 1 1 Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Rev. 0.1 / Feb. 2004 6 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM BASIC FUNCTIONAL DESCRIPTION (Continued) Extended Mode Register BA1 BA0 A11 A10 A9 A8 A7 1 0 0 0 0 0 0 A6 A5 DS A4 A3 A2 TCSR A1 A0 PASR TCSR (Temperature compensated self Refresh) Temperature( oC) A4 A3 0 0 45 ~ 70 0 1 15 ~ 45 1 0 -25 ~ 15 1 1 70 ~ 85 1) Note 1) Just guarantee for extended and industrial part DS (Driver Strength) Driver Strength PASR (Partial Array Self Refresh) A6 A5 A2 A1 A0 0 0 Full 0 0 0 All Banks 0 1 1/2 Strength 0 0 1 Half of Total Bank (BA1=0) 1 0 1/4 Strength 0 1 0 Quarter of Total Bank (BA1=BA0=0) 1 1 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 One Eighth of Total Bank (Row Address MSB=0) 1 1 0 One Sixteenth of Total Bank (Row Address 2 MSBs=0) 1 1 1 Reserved Rev. 0.1 / Feb. 2004 Self Refresh Coverage 7 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM Power Up and Initialization Like a Synchronous DRAM, Mobile SDR must be powered up and initialized in a predefined manner. Power must be applied to VDD and VDDQ(simultaneously). The clock signal must be started at the same time. After power up, an initial pause of 200 usec is required. And a precharge all command will be issued to the Mobile SDR. Then, 8 or more Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a mode register set(MRS) command will be issued to program the specific mode of operation (Cas Latency, Burst length, etc.) And a extended mode register set command will be issued to program specific mode of self refresh operation(PASR & TCSR). The following these cycles, the Mobile SDR is ready for normal opeartion. Programming the registers Mode Register The mode register contains the specific mode of operation of the Mobile SDR. This register includes the selection of a burst length(1, 2, 4, 8, Full Page), a cas latency(1, 2, or 3), a burst type. The mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command. Extended Mode Register The extended mode register contains the specific features of self refresh opeartion of the Mobile SDR. This register includes the selection of partial arrays to be refreshed(half array, quarter array, etc.), tempearture range of the device(85, 70, 45, 15 oC) for reducing current consumption during self refresh. The extended mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by reprogramming the mode register through the execution of extended mode register set command. Bank(Row) Active The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects the bank, and the value on the A0-A12 selects the row. This row remains active for column access until a precharge command is issued to that bank. Read and write opeartions can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command. Read The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the sarting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.The length of burst and the CAS latency will be determined by the values programmed during the MRS command. Write The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. Rev. 0.1 / Feb. 2004 8 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM Precharge The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the precharge command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open row in a particular bank will be precharged. The bank(s) will be available when the minimum tRP time is met after the precharge command is issued. Auto Precharge The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If A10 is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated. Burst Termination The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst Stop command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts a burst cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the bank open. Data Mask The Data Mask comamnd is used to mask READ or WRITE data. During a READ operation, When this command is issued, data ouputs are disabled and become high impedance after two clock delay. During a WRITE operation, When this command is issued, data inputs can’t be written with no clock delay. Clock Suspend The Clock Suspend command is used to suspend the internal clock of DRAM. During normal access mode, CKE is keeping High. When CKE is low, it freezes the internal clock and extends data Read and Write operations. Power Down The Power Down command is used to reduce standby current. Before this command is issued, all banks must be precharged and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping CKE low, all of the input buffer except CKE are gated off. Auto Refresh The Auto Refresh command is used during normal operation and is similar to CBR refresh in Coventional DRAMs. This command must be issued each time a refresh is required. When an Auto Refresh command is issued , the address bits is “Don’t care”, because the specific address bits is generated by internal refresh address counter. Self Refresh The Self Refresh command is used to retain cell data in the Mobile SDR. In the Self Refresh mode, the Mobile SDR operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDR can accomplish an special Self Refresh operation by the specific modes(TCSR, PASR) programmed in extended mode registers. The Mobile SDR can control the refresh rate by the temperature value of TCSR (Temperature Compensated Self Refresh) and select the memory array to be refreshed by the value of PASR(Partial Array Self Refresh). The Mobile SDR can reduce the self refresh current(IDD6) by using these two modes. Deep Power Down The Deep Power Down Mode is used to achieve maximum power reduction by cutting the power of the whole memory array of the devices. For more information, see the special operation for Low Power consumption of this data sheet. Rev. 0.1 / Feb. 2004 9 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM COMMAND TRUTH TABLE Function ADDR A10 /AP CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X Op Code 2 Extended Mode Register Set H X L L L L X Op Code 2 No Operation H X L H H H X X Device Deselect H X H X X X X X Bank Active H X L L H H X Read H X L H L H Read with Autoprecharge H X L H L H Write H X L H L Write with Autoprecharge H X L H Precharge All Banks H X L Precharge selected Bank H X Burst stop H X Data Write/Output Enable H X X Data Mask/Output Disable H X X Auto Refresh H H L L L H X X Self Refresh Entry H L L L L H X X Self Refresh Exit L H H X X X L H H H X X Precharge Power Down Entry H L H X X X L H H H X X Precharge Power Down Exit L H H X X X L H H H X X Clock Suspend Entry H L H X X X L V V V X X Clock Suspend Exit L H X X Deep Power Down Entry H L X X Deep Power Down Exit L H X X Row Address BA V Column L V X Column H V L X Column L V L L X Column H V L H L X X H X L L H L X X L V L H H L X X X X V X L H H X L Note X 1 Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set. Rev. 0.1 / Feb. 2004 10 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM CURRENT STATE TRUTH TABLE (Sheet 1 of 4) Current State idle Row Active Read Command CS RAS CAS WE BA0/ BA1 A11-A0 L L L L L L H X X Auto or Self Refresh Start Auto or Self Refresh L L H L BA X Precharge No Operation L L H H BA Row Add. Bank Activate Activate the specified bank and row L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 4 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4 L H H H X X No Operation No Operation 3 H X X X X X Device Deselect No Operation or Power Down 3 L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge Precharge 7 L L H H BA Row Add. Bank Activate ILLEGAL 4 L H L L BA Col Add. A10 Write/WriteAP Start Write : optional AP(A10=H) 6 L H L H BA Col Add. A10 Read/ReadAP Start Read : optional AP(A10=H) 6 L H H H X X No Operation No Operation H X X X X X Device Deselect No Operation L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BA X Precharge Termination Burst: Start the Precharge L L H H BA Row Add. Bank Activate ILLEGAL L H L L BA Col Add. A10 Write/WriteAP Termination Burst: Start Write(optional AP) 8,9 L H L H BA Col Add. A10 Read/ReadAP Termination Burst: Start Read(optional AP) 8 L H H H X X No Operation Continue the Burst OP CODE OP CODE Mode Register Set Set the Mode Register Notes L Rev. 0.1 / Feb. 2004 OP CODE Action Description 14 5 13,14 13,14 13 4 11 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM CURRENT STATE TRUTH TABLE (Sheet 2 of 4) Current State Read Write Read with Auto Precharge Write with Auto Precharge Command CS RAS CAS WE BA0/ BA1 A11-A0 X X Action Description H X X X L L L L L L L H X X Auto or Self Refresh ILLEGAL L L H L BA X Precharge Termination Burst: Start the Precharge 10 L L H H BA Row Add. Bank Activate ILLEGAL 4 L H L L BA Col Add. A10 Write/WriteAP Termination Burst: Start Write(optional AP) 8 L H L H BA Col Add. A10 Read/ReadAP Termination Burst: Start Read(optional AP) 8,9 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 12 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 12 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst Rev. 0.1 / Feb. 2004 OP CODE OP CODE OP CODE Device Deselect Continue the Burst Mode Register Set ILLEGAL Notes 13,14 13 13,14 13 13,14 13 12 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM CURRENT STATE TRUTH TABLE (Sheet 3 of 4) Current State Precharging Row Activating Write Recovering Command CS RAS CAS WE BA0/ BA1 A11-A0 L L L L L L H X X Auto or Self Refresh ILLEGAL L L H L BA X Precharge No Operation: Bank(s) idle after tRP L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 4,12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4,12 L H H H X X No Operation No Operation: Bank(s) idle after tRP H X X X X X Device Deselect No Operation: Bank(s) idle after tRP L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Add. Bank Activate ILLEGAL 4,11,1 2 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 4,12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4,12 L H H H X X No Operation No Operation: Row Active after tRCD H X X X X X Device Deselect No Operation: Row Active after tRCD L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BA X Precharge ILLEGAL 4,13 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP Start Write: Optional AP(A10=H) L H L H BA Col Add. A10 Read/ReadAP Start Read: Optional AP(A10=H) L H H H X X No Operation No Operation: Row Active after tDPL OP CODE OP CODE Mode Register Set ILLEGAL Notes L Rev. 0.1 / Feb. 2004 OP CODE Action Description 13,14 13 13,14 13 13,14 13 9 13 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM URRENT STATE TRUTH TABLE (Sheet 4 of 4) Current State Write Recovering Write Recovering with Auto Precharge Refreshing Mode Register Accessing Command CS RAS CAS WE BA0/ BA1 A11-A0 X X Action Description Device Deselect No Operation: Row Active after tDPL Mode Register Set ILLEGAL Notes H X X X L L L L L L L H X X Auto or Self Refresh ILLEGAL L L H L BA X Precharge ILLEGAL 4,13 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 4,12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4,9,12 L H H H X X No Operation No Operation: Precharge after tDPL H X X X X X Device Deselect No Operation: Precharge after tDPL L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 13 L L H H BA Row Add. Bank Activate ILLEGAL 13 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 13 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 13 L H H H X X No Operation No Operation: idle after tRC H X X X X X Device Deselect No Operation: idle after tRC L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 13 L L H H BA Row Add. Bank Activate ILLEGAL 13 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 13 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 13 L H H H X X No Operation No Operation: idle after 2 clock cycles H X X X X X Device Deselect No Operation: idle after 2 clock cycles Rev. 0.1 / Feb. 2004 OP CODE OP CODE OP CODE 13,14 13 13,14 13,14 14 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM Note : 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. 14. Mode Register Set and Extended Mode Register Set is same command truth table except BA1. Rev. 0.1 / Feb. 2004 15 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM CKE Enable(CKE) Truth TABLE (Sheet 1 of 2) CKE Current State Self Refresh Command Previous Current Cycle Cycle CS RAS CAS WE BA0, BA1 A11A0 Notes H X X X X X X X INVALID 1 L H H X X X X X Exit Self Refresh with Device Deselect 2 L H L H H H X X Exit Self Refresh with No Operation 2 L H L H H L X X ILLEGAL 2 L H L H L X X X ILLEGAL 2 L H L L X X X X ILLEGAL 2 L L X X X X X X Maintain Self Refresh H X X X X X X X INVALID 1 H X X X X X L H 2 L H H H X X Power Down mode exit, all banks idle L X X X X X L X X X ILLEGAL 2 X X L X X Power Down L Deep Power Down Action H L L L X X X X X X Maintain Power Down Mode H X X X X X X X INVALID 1 L H X X X X X X Deep Power Down mode exit 5 L L X X X X X X Maintain Deep Power Down Mode Rev. 0.1 / Feb. 2004 16 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM CKE Enable(CKE) Truth TABLE (Sheet 2 of 2) Current State All Banks Idle Any State other than listed above CKE Command Previous Current Cycle Cycle CS RAS CAS WE BA0, BA1 Action A11A0 Notes H H H X X X H H L H X X H H L L H X H H L L L H X H H L L L L OP CODE H L H X X X H L L H X X H L L L H X H L L L L H X X Entry Self Refresh H L L L L L OP CODE Mode Register Set L X X X X X X X Power Down 4 H L L H H L X X Deep Power Down 4 H H X X X X X X Refer to operations of the Current State Truth Table H L X X X X X X Begin Clock Suspend next cycle L H X X X X X X Exit Clock Suspend next cycle L L X X X X X X Maintain Clock Suspend Refer to the idle State section of the Current State Truth Table X 3 3 3 Auto Refresh Mode Register Set Refer to the idle State section of the Current State Truth Table 4 3 3 3 4 Note : 1. For the given current state CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 3. The address inputs depend on the command that is issued. 4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 200usec. Rev. 0.1 / Feb. 2004 17 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM ABSOLUTE MAXIMUM RATING Parameter Symbol Rating Unit Ambient Temperature TA -25 ~ 70 oC Storage Temperature TSTG -55 ~ 125 o VIN, VOUT -1.0 ~ 4.6 V VDD -1.0 ~ 4.6 V VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W . oC . Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS . TSOLDER Soldering Temperature Time C 260 10 Sec DC OPERATING CONDITION (TA= -25 to 70oC ) Parameter Symbol Min Typ Max Unit Note Power Supply Voltage VDD 2.7 3.0 3.6 V 1 Power Supply Voltage VDDQ 2.7 3.0 3.6 V 1, 2 - VDDQ+0.3 V 1, 2 0.5 V 1, 2 Input High Voltage VIH 2.2 Input Low Voltage VIL -0.3 Note : 1. All Voltages are referenced to VSS = 0V 2. VDDQ must not exceed the level of VDD AC OPERATING TEST CONDITION (TA= -25 to 70 oC, VDD = 2.7 ~ 3.6V, VSS = 0V) Parameter Symbol Value Unit VIH / VIL 2.4/0.4 V Vtrip 0.5*VDDQ V Input Rise/Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage Voutref 0.5*VDDQ V AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Rev. 0.1 / Feb. 2004 CL pF Note 1 18 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM CAPACITANCE (TA= 25 oC, f=1MHz, VDD=3.3V) Parameter Input capacitance Data input / output capacitance Pin Symbol Min Max Unit CLK CI1 TBD TBD pF A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3 CI2 TBD TBD pF DQ0 ~ DQ31 CI/O TBD TBD pF Note 1. Vtt=0.5xVDDQ 50Ω Output ZO=50Ω 30pF DC CHARACTERRISTICS I (TA= -25 to 70oC) Parameter Symbol Min Max Unit Note Input Leakage Current ILI -1 1 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH 2.4 - V 3 Output Low Voltage VOL - 0.4 V 4 Note : 1. VIN = 0 to 3.0V. All other pins are not tested under VIN=0V. 2. DOUT is disabled. VOUT= 0 to 3.6V. 3. IOUT = - 0.1mA 4. IOUT = + 0.1mA Rev. 0.1 / Feb. 2004 19 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM DC CHARACTERISTICS II (TA= -25 to 70oC) Speed Parameter Symbol Test Condition Unit Note H Operating Current Precharge Standby Current in Power Down Mode IDD1 Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA 180 mA IDD2P CKE ≤ VIL(max), tCK = 15ns 1.0 mA IDD2PS CKE ≤ VIL(max), tCK = ∞ 0.7 mA IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 30 IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 14 IDD3P CKE ≤ VIL(max), tCK = 15ns 10 Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode 1 mA mA CKE ≤ VIL(max), tCK = ∞ 10 CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 50 IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 50 Burst Mode Operating Current IDD4 tCK ≥ tCK(min), IOL=0mA All banks active 240 mA Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active 360 mA Self Refresh Current IDD6 CKE ≤ 0.2V See Next Page mA Standby Current in Deep Power Down Mode IDD7 See p.24~25 140 uA IDD3PS IDD3N Active Standby Current in Non Power Down Mode mA 1 2 Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. See the tables of next page for more specific IDD6 current values. Rev. 0.1 / Feb. 2004 20 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM DC CHARACTERISTICS III - Low Power IDD6 Memory Array Temp. ( oC) 4 Banks 2 Banks 1 Bank 70 1260 860 620 uA 45 820 620 500 uA 15 660 500 400 uA Rev. 0.1 / Feb. 2004 Unit 21 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) B Parameter Symbol Unit Min Max 1000 Note CAS Latency=3 tCK3 7.5 CAS Latency=2 tCK2 9.5 Clock High Pulse Width tCHW 2.5 - ns 1 Clock Low Pulse Width tCLW 2.5 - ns 1 CAS Latency=3 tAC3 - 5.4 ns CAS Latency=2 tAC2 - 7 ns Data-out Hold Time tOH 2.5 - ns Data-Input Setup Time tDS 2 - ns 1 Data-Input Hold Time tDH 1 - ns 1 Address Setup Time tAS 2 - ns 1 Address Hold Time tAH 1 - ns 1 CKE Setup Time tCKS 2 - ns 1 CKE Hold Time tCKH 1 - ns 1 Command Setup Time tCS 2 - ns 1 Command Hold Time tCH 1 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1 - ns System Clock Cycle Time Access Time From Clock CLK to Data Output in High-Z Time ns ns 2 CAS Latency=3 tOHZ3 5.4 ns CAS Latency=2 tOHZ2 7 ns Note : 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. Rev. 0.1 / Feb. 2004 22 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) B Parameter Symbol Unit Min Max RAS Cycle Time tRC 65 - ns RAS to CAS Delay tRCD 19 - ns RAS Active Time tRAS 45 100K ns RAS Precharge Time tRP 19 - ns RAS to RAS Bank Active Delay tRRD 15 - ns CAS to CAS Delay tCCD 1 - CLK Write Command to Data-In Delay tWTL 0 - CLK Data-in to Precharge Command tDPL 2 - CLK Data-In to Active Command tDAL DQM to Data-Out Hi-Z tDQZ 2 - CLK DQM to Data-In Mask tDQM 0 - CLK MRS to New Command tMRD 2 - CLK CAS Latency=3 tPROZ3 3 - CLK CAS Latency=2 tPROZ2 2 Power Down Exit Time tDPE 1 - CLK Power Down Exit Time tDPE 1 - CLK Self Refresh Exit Time tSRE 1 - CLK Refresh Time tREF - 64 ms Precharge to Data Output High-Z Note tDPL+tRP CLK 1 Note : 1. A new command can be given tRC after self refresh exit. Rev. 0.1 / Feb. 2004 23 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM Special Operation for Low Power Consumption Deep Power Down Mode Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. Full initialization is required when the device exits from Deep Power Down Mode. Truth Table Current State Command CKEn-1 CKEn CS RAS CAS WE Idle Deep Power Down Entry H L L H H L Deep Power Down Deep Power Down Exit L H X X X X Deep Power Down Mode Entry The Deep Power Down Mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of the clock, while CKE is low. The following diagram illustrates deep power down mode entry. CLK CKE CS RAS CAS WE tRP Precharge if needed Rev. 0.1 / Feb. 2004 Deep Power Down Entry 24 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM Deep Power Down Mode (Continued) Deep Power Down Mode Exit Sequence The Deep Power Down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command. 1. Maintain NOP input conditions for a minimum of 200usec 2. Issue precharge commands for all banks of the device 3. Issue 8 or more auto refresh commands 4. Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extended mode register The following timing diagram illustrates deep power down mode exit sequence. CLK CKE CS RAS CAS WE 200µs Deep Power Down exit Rev. 0.1 / Feb. 2004 tRC tRP All Banks Precharge Auto refresh Auto refresh Mode Register Set Extended Mode Register Set New Command Accepted Here 25 Preliminary HY5Y7A2DLM-HF 4Banks x 4M x 32bits Synchronous DRAM PACKAGE INFORMATION 90 Ball 0.8mm pitch, 11mm x 13mm FBGA Unit [mm] 11.0 2.30 ± 0.10 6.40 BSC 0.80( Typ) A1 INDEX MARK 0.80( Typ) 0.450 ± 0.05 View 13.0 ± 0.10 11.20 BSC Bottom 6.50 ± 0.05 3.20 ± 0.05 0.340 ±0.05 5.50 ± 0.05 1.40 max Rev. 0.1 / Feb. 2004 26