HYNIX HYMD232726CL8-L

32Mx72 bits
Unbuffered DDR SDRAM DIMM
HYMD232726C(L)8-M/K/H/L
DESCRIPTION
Hynix HYMD232726C(L)8-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD232726C(L)8-M/K/
H/L series consists of nine 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix
HYMD232726C(L)8-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of industry
standard. It is suitable for easy interchange and addition.
Hynix HYMD232726C(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control
inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on
both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable
latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD232726C(L)8-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
256MB (32M x 72) Unbuffered DDR DIMM based on
32Mx8 DDR SDRAM
•
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
•
JEDEC Standard 184-pin dual in-line memory module
(DIMM)
•
Data inputs on DQS centers when write (centered
DQ)
•
Error Check Correction (ECC) Capability
•
•
2.5V +/- 0.2V VDD and VDDQ Power supply
Data strobes synchronized with output data for read
and input data for write
•
All inputs and outputs are compatible with SSTL_2
interface
•
Programmable CAS Latency 2 / 2.5 supported
•
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
•
tRAS Lock-out function supported
•
Internal four bank operations with single pulsed RAS
•
Auto refresh and self refresh supported
•
8192 refresh cycles / 64ms
•
•
Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
ORDERING INFORMATION
Part No.
Power Supply
HYMD232726C(L)8-H
HYMD232726C(L)8-L
Interface
Form Factor
SSTL_2
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
133MHz (*DDR266:2-2-2)
HYMD232726C(L)8-M
HYMD232726C(L)8-K
Clock Frequency
VDD=2.5V
VDDQ=2.5V
133MHz (*DDR266A)
133MHz (*DDR266B)
100MHz (*DDR200)
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Mar. 2003
1
HYMD232726C(L)8-M/K/H/L
PIN DESCRIPTION
Pin
Pin Description
Pin
Pin Description
CK0,/CK0,CK1,/CK1,CK2,/CK2
Differential Clock Inputs
VDDQ
DQs Power Supply
CS0
Chip Select Input
VSS
Ground
CKE0
Clock Enable Input
VREF
Reference Power Supply
/RAS, /CAS, /WE
Commend Sets Inputs
VDDSPD
Power Supply for SPD
A0 ~ A12
Address
SA0~SA2
E2PROM Address Inputs
BA0, BA1
Bank Address
SCL
E2PROM Clock
DQ0~DQ63
Data Inputs/Outputs
SDA
E2PROM Data I/O
CB0~CB7
Check Bit
WP
Write Protect Flag
DQS0~DQS8
Data Strobe Inputs/Outputs
VDDID
VDD Identification Flag
DM0~DM8
Data-in Mask
DU
Do not Use
VDD
Power Supply
NC
No Connection
PIN ASSIGNMENT
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
1
VREF
32
A5
62
VDDQ
93
VSS
124
VSS
154
Name
/RAS
2
DQ0
33
DQ24
63
/WE
94
DQ4
125
A6
155
DQ45
3
VSS
34
VSS
64
DQ41
95
DQ5
126
DQ28
156
VDDQ
4
DQ1
35
DQ25
65
/CAS
96
VDDQ
127
DQ29
157
/CS0
5
DQS0
36
DQS3
66
VSS
97
DM0
128
VDDQ
158
/CS1
6
DQ2
37
A4
67
DQS5
98
DQ6
129
DM3
159
DM5
7
VDD
38
VDD
68
DQ42
99
DQ7
130
A3
160
VSS
8
DQ3
39
DQ26
69
DQ43
100
VSS
131
DQ30
161
DQ46
DQ47
9
NC
40
DQ27
70
VDD
101
NC
132
VSS
162
10
NC
41
A2
71
NC
102
NC
133
DQ31
163
NC
11
VSS
42
Vss
72
DQ48
103
A13*
134
CB4
164
VDDQ
12
DQ8
43
A1
73
DQ49
104
VDDQ
135
CB5
165
DQ52
13
DQ9
44
CB0
74
VSS
105
DQ12
136
VDDQ
166
DQ53
14
DQS1
45
CB1
75
/CK2
106
DQ13
137
CK0
167
NC
15
VDDQ
46
VDD
76
CK2
107
DM1
138
/CK0
168
VDD
16
CK1
47
DQS8
77
VDDQ
108
VDD
139
VSS
169
DM6
17
/CK1
48
A0
78
DQS6
109
DQ14
140
DM8
170
DQ54
18
VSS
49
CB2
79
DQ50
110
DQ15
141
A10
171
DQ55
19
DQ10
50
VSS
80
DQ51
111
CKE1
142
CB6
172
VDDQ
20
DQ11
51
CB3
81
VSS
112
VDDQ
143
VDDQ
173
NC
21
CKE0
52
BA1
82
VDDID
113
BA2*
144
CB7
174
DQ60
22
VDDQ
83
DQ56
114
DQ20
175
DQ61
23
DQ16
53
DQ32
84
DQ57
115
A12
145
VSS
176
VSS
24
DQ17
54
VDDQ
85
VDD
116
VSS
146
DQ36
177
DM7
25
DQS2
55
DQ33
86
DQS7
117
DQ21
147
DQ37
178
DQ62
26
VSS
56
DQS4
87
DQ58
118
A11
148
VDD
179
DQ63
27
A9
57
DQ34
88
DQ59
119
DM2
149
DM4
180
VDDQ
28
DQ18
58
VSS
89
VSS
120
VDD
150
DQ38
181
SA0
29
A7
59
BA0
90
WP
121
DQ22
151
DQ39
182
SA1
30
VDDQ
60
DQ35
91
SDA
122
A8
152
VSS
183
SA2
31
DQ19
61
DQ40
92
SCL
123
DQ23
153
DQ44
184
VDDSPD
Key
key
* These are not used on this module but may be used for other module in 184pin DIMM family
Rev. 0.1 / Mar. 2003
2
HYMD232726C(L)8-M/K/H/L
FUNCTIONAL BLOCK DIAGRAM
/C S 0
DQS0
DM0
DQS4
DM4
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
/C S
DQS
D0
DQS1
DM1
D Q 32
D Q 33
D Q 34
D Q 35
D Q 36
D Q 37
D Q 38
D Q 39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D Q 40
D Q 41
D Q 42
D Q 43
D Q 44
D Q 45
D Q 46
D Q 47
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D Q 48
D Q 49
D Q 50
D Q 51
D Q 52
D Q 53
D Q 54
D Q 55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D Q 56
D Q 57
D Q 58
D Q 59
D Q 60
D Q 61
D Q 62
D Q 63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D4
DQS5
DM5
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ 8
DQ 9
D Q 10
D Q 11
D Q 12
D Q 13
D Q 14
D Q 15
/C S
DQS
D1
DQS2
DM2
/C S
DQS
D5
DQS6
DM6
D Q 16
D Q 17
D Q 18
D Q 19
D Q 20
D Q 21
D Q 22
D Q 23
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/C S
DQS
D2
DQS3
DM3
/C S
DQS
D6
DQS7
DM7
D Q 24
D Q 25
D Q 26
D Q 27
D Q 28
D Q 29
D Q 30
D Q 31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
/C S
DQ S
D3
/C S
DQS
D7
DQS8
DM8
/C S
*C lock W iring
DQ S
D8
C lock Input
SD R A M s
*C K 0,/C K 0
*C K 1,/C K 1
*C K 2,/C K 2
3 SDRAM s
3 SDRAM s
3 SDRAM s
* W ire p er clock lo ad ing tab le/wiring d iagram s
S erial P D
VD D SP D
SCL
VD D /VD D Q
SDA
WP
A0
A1
A2
SA0
SA 1
SA 2
VR EF
VS S
BA 0-B A 1
A0 - A 12
/R AS
/C AS
C KE 0
/W E
Rev. 0.1 / Mar. 2003
BA 0-BA 1 : SD R AM s D 0 - D 8
A 0 - A12 : S D R A M s D 0 - D 8
/R A S : SD R A M s D 0 - D 8
/C A S : SD R A M s D 0 - D 8
C K E : SD R A M s D 0 - D 8
/W E : S D R AM s D 0 - D 8
V D D ID
.
.
= =
.
. . . =.
..
SP D
D0 - D8
D0 - D8
D0 - D8
Strap:see N ote 4
N otes:
1. D Q -to-I/O wiring is shown as recom m ended
but m ay be changed
2. D Q /D Q S/D M /C KE /S relationships m ust be
m aintained as shown
3. D Q , D Q S, D M /D Q S resistors : 22O hm s+ /-5%
4. V D D ID strap connections
(for m em ory dev ice V D D , V D D Q ) :
S trap out :(open) : VD D = VD D Q
S trap In (V ss) : V D D = V D D Q
3
HYMD232726C(L)8-M/K/H/L
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
o
C
Storage Temperature
TSTG
-55 ~ 125
o
C
Voltage on Any Pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD relative to VSS
VDD
-0.5 ~ 3.6
V
Voltage on VDDQ relative to VSS
VDDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
IOS
50
mA
Power Dissipation
PD
9
W
Soldering Temperature ⋅ Time
TSOLDER
260 / 10
oC
/ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS= 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Power Supply Voltage
VDD
2.3
2.5
2.7
V
Power Supply Voltage
VDDQ
2.3
2.5
2.7
V
Input High Voltage
VIH
VREF + 0.15
-
VDDQ + 0.3
V
Input Low Voltage
VIL
-0.3
-
VREF - 0.15
V
Termination Voltage
VTT
VREF - 0.04
VREF
VREF + 0.04
V
Reference Voltage
VREF
0.49*VDDQ
0.5*VDDQ
0.51*VDDQ
V
Note
1
2
3
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
Input Differential Voltage, CK and /CK inputs
VID(AC)
Input Crossing Point Voltage, CK and /CK inputs
VIX(AC)
Max
Unit
Note
V
VREF - 0.31
V
0.7
VDDQ + 0.6
V
1
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.1 / Mar. 2003
4
HYMD232726C(L)8-M/K/H/L
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
VDDQ x 0.5
V
Termination Voltage
VDDQ x 0.5
V
AC Input High Level Voltage (VIH, min)
VREF + 0.31
V
AC Input Low Level Voltage (VIL, max)
VREF - 0.31
V
VREF
V
Output Timing Measurement Reference Level Voltage
VTT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (RT)
50
Ω
Series Resistor (RS)
25
Ω
Output Load Capacitance for Access Time Measurement (CL)
30
pF
Input Timing Measurement Reference Level Voltage
Rev. 0.1 / Mar. 2003
5
HYMD232726C(L)8-M/K/H/L
CAPACITANCE (TA=25oC, f=100MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Capacitance
A0 ~ A12, BA0, BA1
CIN1
TBD
TBD
pF
Input Capacitance
/RAS, /CAS, /WE
CIN2
TBD
TBD
pF
Input Capacitance
CKE0
CIN3
TBD
TBD
pF
Input Capacitance
CS0
CIN4
TBD
TBD
pF
Input Capacitance
CK0, /CK0, CK1, /CK1, CK2,/CK2
CIN5
TBD
TBD
pF
Input Capacitance
DM0 ~ DM8
CIN6
TBD
TBD
pF
Data Input / Output Capacitance
DQ0 ~ DQ63, DQS0 ~ DQS8
CIO1
TBD
TBD
pF
Data Input / Output Capacitance
CB0 ~ CB7
CIO2
TBD
TBD
pF
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
R T = 50 Ω
O utput
Z o= 50 Ω
VREF
C L = 30 pF
Rev. 0.1 / Mar. 2003
6
HYMD232726C(L)8-M/K/H/L
DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Input Leakage
Current
Symbol
Add, CMD, /CS, /CKE
CK, /CK
ILI
Min.
Max
-18
18
-12
12
Unit
Note
uA
1
Output Leakage Current
ILO
-5
5
uA
2
Output High Voltage
VOH
VTT + 0.76
-
V
IOH = -15.2mA
Output Low Voltage
VOL
-
VTT - 0.76
V
IOL = +15.2mA
Note :
1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2. DOUT is disabled, VOUT=0 to 2.7V
3. These values are device characteristics.
Rev. 0.1 / Mar. 2003
7
HYMD232726C(L)8-M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Speed
Test Condition
-M
-K
-H
-L
Unit Note
Operating Current
IDD0
One bank; Active Precharge; tRC=tRC(min);
tCK= tCK(min); DQ,DM and DQS inputs
changing twice per clock cycle; address and
control inputs changing once per clock cycle
945
855
855
810
mA
Operating Current
IDD1
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per
clock cycle
1350
1170
1170
1080
mA
Precharge Power Down
Standby Current
IDD2P
All banks idle; Power down - mode; CKE=Low,
tCK=tCK(min)
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing
once per clock cycle. VIN=VREF for DQ, DQS
and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode;
CKE=Low, tCK=tCK(min)
IDD3N
/CS=HIGH; CKE=HIGH; One bank; ActivePrecharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
540
450
450
450
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
2610
2250
2250
1710
IDD4W
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle
2610
2250
2250
1710
2070
1890
1890
1755
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at
100Mhz, 10*tCK for DDR266A & DDR266B at
133Mhz; distributed refresh
Self Refresh Current
IDD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Operating Current - Four
Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
Rev. 0.1 / Mar. 2003
180
450
360
1080
360
315
225
mA
mA
mA
mA
Normal
27
mA
Low Power
13.5
mA
2835
2745
2745
2520
mA
8
HYMD232726C(L)8-M/K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR266(2-2-2)
DDR266A
DDR266B
DDR200
Min
Max
Min
Max
Min
Max
Min
Max
Unit Note
Row Cycle Time
tRC
60
-
65
-
65
-
70
-
ns
Auto Refresh Row Cycle Time
tRFC
75
-
75
-
75
-
80
-
ns
Row Active Time
tRAS
45
120K
45
120K
45
120K
50
120K
ns
Active to Read with Auto
Precharge Delay
tRAP
15
-
20
-
20
-
20
-
ns
Row Address to Column Address
Delay
tRCD
15
-
20
-
20
-
20
-
ns
Row Active to Row Active Delay
tRRD
15
-
15
-
15
-
15
-
ns
Column Address to Column
Address Delay
tCCD
1
-
1
-
1
-
1
-
CK
Row Precharge Time
tRP
15
-
20
-
20
-
20
-
ns
Write Recovery Time
tWR
15
-
15
-
15
-
15
-
ns
Write to Read Command Delay
tWTR
1
-
1
-
1
-
1
-
CK
Auto Precharge Write Recovery +
Precharge Time
tDAL
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-
CK
7.5
12
7.5
12
7.5
12
8.0
12
ns
7.5
12
7.5
12
10
12
10
12
ns
System Clock
Cycle Time
CL = 2.5
CL = 2
tCK
16
15
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge
Skew
tAC
-0.75
0.75
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
DQS-Out edge to Clock edge
Skew
tDQSCK
-0.75
0.75
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
DQS-Out edge to Data-Out edge
Skew
tDQSQ
-
0.5
-
0.5
-
0.5
-
0.6
ns
Data-Out hold time from DQS
tQH
tHP
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns
1, 10
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
ns
1,9
tQHS
-
0.75
-
0.75
-
0.75
-
0.75
ns
10
Data Hold Skew Factor
Valid Data Output Window
tDV
Data-out high-impedance
window from CK, /CK
tHZ
-0.75
0.75
-0.75
0.75
-0.75
Data-out low-impedance window
from CK, /CK
tLZ
-0.75
0.75
-0.75
0.75
-0.75
Rev. 0.1 / Mar. 2003
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
ns
0.75
-0.8
0.8
ns
17
0.75
-0.8
0.8
ns
17
9
HYMD232726C(L)8-M/K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
Input Setup Time (fast slew rate)
DDR266(2-2-2)
DDR266A
- continued -
DDR266B
DDR200
Unit
Note
-
ns
2,3,5,6
1.1
-
ns
2,3,5,6
-
1.1
-
ns
2,4,5,6
-
1.1
-
ns
2,4,5,6
ns
6
Min
Max
Min
Max
Min
Max
Min
Max
tIS
0.9
-
0.9
-
0.9
-
1.1
Input Hold Time (fast slew rate)
tIH
0.9
-
0.9
-
0.9
-
Input Setup Time (slow slew rate)
tIS
1.0
-
1.0
-
1.0
Input Hold Time (slow slew rate)
tIH
1.0
-
1.0
-
1.0
tIPW
2.2
Write DQS High Level Width
tDQSH
0.35
-
0.35
-
0.35
-
0.35
-
CK
Write DQS Low Level Width
tDQSL
0.35
-
0.35
-
0.35
-
0.35
-
CK
Clock to First Rising edge of DQSIn
tDQSS
0.72
1.28
0.75
1.25
0.75
1.25
0.75
1.25
CK
Data-In Setup Time to DQS-In
(DQ & DM)
tDS
0.5
-
0.5
-
0.5
-
0.6
-
ns
6,7,
11~13
Data-in Hold Time to DQS-In (DQ
& DM)
tDH
0.5
-
0.5
-
0.5
-
0.6
-
ns
6,7,
11~13
DQ & DM Input Pulse Width
tDIPW
1.75
-
1.75
-
1.75
-
2
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
CK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
tWPRES
0
-
0
-
0
-
0
-
CK
Write DQS Preamble Hold Time
tWPREH
0.25
-
0.25
-
0.25
-
0.25
-
CK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
2
-
2
-
2
-
2
-
CK
Exit Self Refresh to Any Execute
Command
tXSC
200
-
200
-
200
-
200
-
CK
Average Periodic Refresh Interval
tREFI
-
15.6
-
15.6
-
15.6
-
15.6
us
Input Pulse Width
2.2
2.2
2.5
8
Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
For command/address input slew rate >=1.0V/ns
4.
For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
Rev. 0.1 / Mar. 2003
10
HYMD232726C(L)8-M/K/H/L
5.
CK, /CK slew rates are >=1.0V/ns
6.
These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by
design or tester correlation.
7.
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).
10.
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel
to n-channel variation of the output drivers.
11.
This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
12.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
ps
ps
0.5
0
0
0.4
+75
+75
0.3
+150
+150
I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below
VREF +/-310mV for a duration of up to 2ns.
I/O Input Level
13.
14.
15.
Delta tDS
Delta tDH
mV
ps
ps
+280
+50
+50
I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate
1=0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
ps
ps
0
0
0
+/-0.25
+50
+50
+/- 0.5
+100
+100
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transi tions through the DC region must be monotonic.
tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock
16.
For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
tRAS - BL/2 x tCK.
17.
tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced
to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
Rev. 0.1 / Mar. 2003
11
HYMD232726C(L)8-M/K/H/L
SIMPLIFIED COMMAND TRUTH TABLE
A10/
AP
Command
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
X
L
L
L
L
OP code
1,2
H
X
X
X
H
X
X
1
L
H
H
H
Device Deselect
No Operation
Bank Active
H
X
L
L
H
H
H
X
L
H
L
H
ADDR
RA
Read
BA
V
L
CA
Read with Autoprecharge
1
1,3
L
H
X
L
H
L
L
CA
Write with Autoprecharge
1
V
H
Precharge All Banks
H
X
L
L
H
L
Precharge selected Bank
1
V
H
Write
Note
1,4
H
X
1,5
L
V
1
X
Read Burst Stop
H
X
L
H
H
L
X
1
Auto Refresh
H
H
L
L
L
H
X
1
Entry
H
L
L
L
L
H
H
X
X
X
Exit
L
H
L
H
H
H
H
X
X
X
L
H
H
H
Self Refresh
Entry
H
X
1
1
L
Precharge
Power Down
Mode
1
X
Exit
Active Power
Down Mode
1
Entry
Exit
L
H
L
H
X
X
X
1
L
H
H
H
1
H
X
X
X
1
L
V
V
V
H
L
H
X
X
1
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. DM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 0.1 / Mar. 2003
12
HYMD232726C(L)8-M/K/H/L
PACKAGE DIMENSIONS
Front
131.35
Side
128.95
5.077
10.0
0.394
(2X)4.00
0.157
5.171
Rev. 0.1 / Mar. 2003
31.75
1.250
(Front)
1.27+/-0.10
2.30
0.91
(2) 0
2.5
0.098
3.18
0 .125MAX
17.80
0.700
133.35
5.25
0.050+/-.004
13
SERIAL PRESENCE DETECT
SPD SPECIFICATION
(32Mx72 Unbuffered DDR DIMM)
Rev. 0.1 / Mar. 2003
14
HYMD232726C(L)8-M/K/H/L
Bin Sort :M(DDR266(2-2-2),K([email protected]=2)
H([email protected]=2.5),L([email protected]=2)
SERIAL PRESENCE DETECT
Function Supported
Byte#
Hexa Value
Function Description
Note
M
0
Number of Bytes written into serial memory at module
manufacturer
1
Total number of Bytes in SPD device
2
Fundamental memory type
3
4
5
K
H
L
M
K
128 Bytes
H
L
80h
256 Bytes
08h
DDR SDRAM
07h
Number of row address on this assembly
13
0Dh
1
Number of column address on this assembly
10
0Ah
1
Number of physical banks on DIMM
1Bank
01h
6
Module data width
72 Bits
48h
7
Module data width (continued)
-
00h
8
Module voltage Interface levels(VDDQ)
9
DDR SDRAM cycle time at CAS Latency=2.5(tCK)
10
DDR SDRAM access time from clock at CL=2.5 (tAC)
11
Module configuration type
12
Refresh rate and type
13
SSTL 2.5V
7.5ns
7.5ns
04h
7.5ns
+/-0.75ns
8.0ns
75h
75h
75h
80h
2
+/-0.8ns
75h
75h
75h
80h
2
ECC
02h
7.8us & Self refresh
82h
Primary DDR SDRAM width
x8
08h
14
Error checking DDR SDRAM data width
x8
08h
15
Minimum clock delay for back-to-back random column
address(tCCD)
1 CLK
01h
16
Burst lengths supported
2,4,8
0Eh
17
Number of banks on each DDR SDRAM
18
CAS latency supported
4 Banks
04h
2, 2.5
0Ch
19
CS latency
0
01h
20
WE latency
1
02h
21
DDR SDRAM module attributes
Differential Clock Input
20h
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
C0h
22
DDR SDRAM device attributes : General
23
DDR SDRAM cycle time at CL=2.0(tCK)
24
DDR SDRAM access time from clock at CL=2.0(tAC)
7.5ns
7.5ns
10ns
+/-0.75ns
10ns
75h
75h
A0h
A0h
2
+/-0.8ns
75h
75h
75h
80h
2
25
DDR SDRAM cycle time at CL=1.5(tCK)
-
00h
26
DDR SDRAM access time from clock at CL=1.5(tAC)
-
00h
27
Minimum row precharge time(tRP)
15ns
20ns
20ns
20ns
3Ch
50h
50h
50h
28
Minimum row activate to row active delay(tRRD)
15ns
15ns
15ns
15ns
3Ch
3Ch
3Ch
3Ch
29
Minimum RAS to CAS delay(tRCD)
15ns
20ns
20ns
20ns
3Ch
50h
50h
50h
30
Minimum active to precharge time(tRAS)
45ns
45ns
45ns
50ns
2Dh
2Dh
2Dh
32h
31
Module row density
32
Command and address signal input setup time(tIS)
0.9ns
0.9ns
0.9ns
1.1ns
90h
90h
90h
B0h
33
Command and address signal input hold time(tIH)
0.9ns
0.9ns
0.9ns
1.1ns
90h
90h
90h
B0h
34
Data signal input setup time(tDS)
0.5ns
0.5ns
0.5ns
0.6ns
50h
50h
50h
60h
35
Data signal input hold time(tDH)
0.5ns
0.5ns
0.5ns
0.6ns
50h
50h
50h
60h
256MB
36~40 Reserved for VCSDRAM
2
2
40h
Undefined
00h
41
Minimum active / auto-refresh time ( tRC)
60ns
65ns
65ns
70ns
3Ch
41h
41h
46h
42
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
75ns
75ns
75ns
80ns
4Bh
4Bh
4Bh
50h
43
Maximum cycle time (tCK max)
12ns
12ns
12ns
12ns
30h
30h
30h
30h
44
Maximim DQS-DQ skew time(tDQSQ)
0.5ns
0.5ns
0.5ns
0.6ns
32h
32h
32h
3Ch
45
Maximum read data hold skew factor(tQHS)
0.75ns
0.75ns
0.75ns
0.75ns
75h
75h
75h
75h
F4h
8Eh
46~61 Superset information(may be used in future)
62
SPD Revision code
63
Checksum for Bytes 0~62
Rev. 0.1 / Mar. 2003
Undefined
00h
Initial release
-
00h
9Ch
C9h
15
HYMD232726C(L)8-M/K/H/L
SERIAL PRESENCE DETECT
- continued Function Supported
Byte #
Note
M
64
65~71
Hexa Value
Function Description
K
Manufacturer JEDEC ID Code
H
L
M
K
H
Hynix JEDEC ID
ADh
-
00h
Hynix(Korea Area)
HSA(United States Area)
HSE(Europe Area)
HSJ(Japan Area)
Singapore
Asia Area
0*h
1*h
2*h
3*h
4*h
5*h
48h
--------- Manufacturer JEDEC ID Code
72
Manufacturing location
73
Manufacture part number(Hynix Memory Module)
H
74
-------- Manufacture part number(Hynix Memory Module)
Y
59h
75
-------- Manufacture part number(Hynix Memory Module)
M
4Dh
76
Manufacture part number (DDR SDRAM)
D
44h
77
Manufacture part number(Memory density)
2
32h
78
Manufacture part number(Module Depth)
3
33h
79
------- Manufacture part number(Module Depth)
2
32h
80
Manufacture part number(Module type)
81
Manufacture part number(Data width)
82
-------Manufacture part number(Data width)
83
Manufacture part number(Refresh, # of Bank.)
84
Manufacture part number(Component Generation)
Blank
20h
7
37h
2
32h
6(8K refresh,4Bank)
36h
C
43h
85
Manufacture part number(Component configuration)
8
38h
86
Manufacture part number(Hyphen)
‘-’
2Dh
87
Manufacture part number(Minimum cycle time)
88~90
M
K
H
L
4Dh
4Bh
L
6
48h
4Ch
Manufacture part number(T.B.D)
Blank
20h
91
Manufacture revision code(for Component)
Blank
20h
92
Manufacture revision code (for PCB)
0
30h
93
Manufacturing date(Year)
-
-
94
Manufacturing date(Week)
-
-
3
95~98
Module serial number
-
-
4
99~127
Manufacturer specific data (may be used in future)
Undefined
00h
5
Undefined
00h
5
128~255 Open for customer use
3
Note :
1. The bank address is excluded
2. These value is based on the component specification
3. These bytes are programmed by code of date week & date year
4. These bytes apply to Hynix’s own Module Serial Number system
5. These bytes undefined and coded as ‘00h’
6. Refer to Hynix web site
Byte 85~86, Low power part
Byte #
85
86
Function Description
Manufacture part number(Low power part)
Manufacture part number(Component configuration)
Rev. 0.1 / Mar. 2003
Function Supported
M
K
H
L
8
L
Hexa Value
M
K
H
L
Note
4Ch
38h
16