GS71116TP/J/U SOJ, TSOP, FP-BGA Commercial Temp Industrial Temp 64K x 16 1Mb Asynchronous SRAM Features 10, 12, 15ns 3.3V VDD Center VDD & VSS SOJ 64K x 16 Pin Configuration • Fast access time: 10, 12, 15ns • CMOS low power operation: 100/85/70 mA at min. cycle time. • Single 3.3V ± 0.3V power supply • All inputs and outputs are TTL compatible • Byte control • Fully static operation • Industrial Temperature Option: -40° to 85°C • Package line up J: 400mil, 44 pin SOJ package TP: 400mil, 44 pin TSOP Type II package U: 6 mm x 8 mm Fine Pitch Ball Grid Array package Description The GS71116 is a high speed CMOS static RAM organized as 65,536-words by 16-bits. Static design eliminates the need for external clocks or timing strobes. Operating on a single 3.3V power supply and all inputs and outputs are TTL compatible. The GS71116 is available in a 6x8 mm Fine Pitch BGA package as well as in 400 mil SOJ and 400 mil TSOP Type-II packages. Pin Descriptions Symbol Address input DQ1 to DQ16 Data input/output CE Chip enable input LB Lower byte enable input (DQ1 to DQ8) UB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Top view 44 pin SOJ 16 17 18 27 26 25 24 23 19 20 21 22 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC Fine Pitch BGA 64K x 16 Bump Configuration Description A0 to A15 A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B DQ16 UB A3 A4 CE DQ1 Upper byte enable input (DQ9 to DQ16) C DQ14 DQ15 A5 A6 DQ2 DQ3 WE Write enable input D VSS DQ13 NC A7 DQ4 VDD OE Output enable input E VDD DQ12 NC NC DQ5 VSS VDD +3.3V power supply F DQ11 DQ10 A8 A9 DQ7 DQ6 VSS Ground NC No connect G DQ9 NC A10 A11 WE DQ8 H NC A12 A13 A14 A15 NC 6mm x 8mm, 0.75mm Bump Pitch Top View Rev: 1.06 6/2000 1/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. M GS71116TP/J/U TSOP-II 64K x 16 Pin Configuration A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 Top view 44 pin TSOP II 13 14 15 44 43 42 41 40 39 38 37 36 35 34 33 32 31 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC 30 29 28 16 17 18 19 20 21 22 27 26 25 24 23 Block Diagram A0 Address Input Buffer Row Decoder Column Decoder A15 CE WE Control OE _____ UB LB _____ Rev: 1.06 6/2000 Memory Array I/O Buffer DQ1 DQ16 2/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71116TP/J/U Truth Table CE OE WE LB UB DQ1 to DQ8 DQ9 to DQ16 VDD Current H X X X X Not Selected Not Selected ISB1, ISB2 L L Read Read L H Read High Z H L High Z Read L L Write Write L H Write Not Write, High Z H L Not Write, High Z Write L L L H X L L H H X X High Z High Z L X X H H High Z High Z IDD Note: X: “H” or “L” Absolute Maximum Ratings Parameter Symbol Rating Unit Supply Voltage VDD -0.5 to +4.6 V Input Voltage VIN -0.5 to VDD+0.5 (≤ 4.6V max.) V Output Voltage VOUT -0.5 to VDD+0.5 (≤ 4.6V max.) V Allowable power dissipation PD 0.7 W Storage temperature TSTG -55 to 150 oC Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Rev: 1.06 6/2000 3/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71116TP/J/U Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage for -12/15 VDD 3.0 3.3 3.6 V Supply Voltage for -10 VDD 3.135 3.3 3.6 V Input High Voltage VIH 2.0 - VDD+0.3 V Input Low Voltage VIL -0.3 - 0.8 V Ambient Temperature, Commercial Range TAc 0 - 70 o C Ambient Temperature, Industrial Range TAI -40 - 85 o C Note: 1. Input overshoot voltage should be less than VDD+2V and not exceed 20ns. 2. Input undershoot voltage should be greater than -2V and not exceed 20ns. Capacitance Parameter Symbol Test Condition Max Unit Input Capacitance CIN VIN=0V 5 pF Output Capacitance COUT VOUT=0V 7 pF Notes: 1. Tested at TA=25°C, f=1MHz 2. These parameters are sampled and are not 100% tested DC I/O Pin Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current IIL VIN = 0 to VDD -1uA 1uA Output Leakage Current ILO Output High Z VOUT = 0 to VDD -1uA 1uA Output High Voltage VOH IOH = - 4mA 2.4 Output Low Voltage VOL ILO = + 4mA Rev: 1.06 6/2000 0.4V 4/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71116TP/J/U Power Supply Currents 0 to 70°C Parameter Symbol -40 to 85°C Test Conditions 10ns 12ns 15ns 10ns 12ns 15ns IDD (max) CE ≤ VIL All other inputs ≥ VIH or ≤ VIL Min. cycle time IOUT = 0 mA 100mA 85mA 70mA 115mA 100mA 85mA Standby Current ISB1 (max) CE ≥ VIH All other inputs ≥ VIH or ≤VIL Min. cycle time 45mA 40mA 35mA 50mA 45mA 40mA Standby Current ISB2 (max) CE ≥ VDD - 0.2V All other inputs ≥ VDD - 0.2V or ≤ 0.2V Operating Supply Current Rev: 1.06 6/2000 10mA 5/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 15mA © 1999, Giga Semiconductor, Inc. GS71116TP/J/U AC Test Conditions Output Load 1 Parameter Conditions Input high level VIH=2.4V Input low level VIL=0.4V Input rise time tr=1V/ns Input fall time tf=1V/ns Input reference level 1.4V Output Load 2 Output reference level 1.4V 3.3V Output load Fig. 1& 2 DQ 50Ω VT=1.4V 589Ω DQ Note: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ. Rev: 1.06 6/2000 30pF1 6/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 5pF1 434Ω © 1999, Giga Semiconductor, Inc. GS71116TP/J/U AC Characteristics Read Cycle Parameter Symbol Read cycle time -10 -12 -15 Unit Min Max Min Max Min Max tRC 10 --- 12 --- 15 --- ns Address access time tAA --- 10 --- 12 --- 15 ns Chip enable access time (CE) tAC --- 10 --- 12 --- 15 ns Byte enable access time (UB, LB) tAB --- 4 --- 5 --- 6 ns Output enable to output valid (OE) tOE --- 4 --- 5 --- 6 ns Output hold from address change tOH 3 --- 3 --- 3 --- ns Chip enable to output in low Z (CE) tLZ* 3 --- 3 --- 3 --- ns Output enable to output in low Z (OE) tOLZ* 0 --- 0 --- 0 --- ns Byte enable to output in low Z (UB, LB) tBLZ* 0 --- 0 --- 0 --- ns Chip disable to output in High Z (CE) tHZ* --- 5 --- 6 --- 7 ns Output disable to output in High Z (OE) tOHZ* --- 4 --- 5 --- 6 ns Byte disable to output in High Z (UB, LB) tBHZ* --- 3.5 --- 3.5 --- 4 --- * These parameters are sampled and are not 100% tested Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL tRC Address tAA tOH Data Out Rev: 1.06 6/2000 Previous Data Data valid 7/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71116TP/J/U Read Cycle 2: WE = VIH tRC Address tAA CE tAC tHZ tLZ tAB UB, LB tBHZ tBLZ OE tOE Data Out tOHZ Data valid tOLZ High impedance Write Cycle Parameter Symbol Write cycle time -10 -12 -15 Unit Min Max Min Max Min Max tWC 10 --- 12 --- 15 --- ns Address valid to end of write tAW 7 --- 8 --- 10 --- ns Chip enable to end of write tCW 7 --- 8 --- 10 --- ns Byte enable to end of write tBW 7 --- 8 --- 10 --- ns Data set up time tDW 5 --- 6 --- 7 --- ns Data hold time tDH 0 --- 0 --- 0 --- ns Write pulse width tWP 7 --- 8 --- 10 --- ns Address set up time tAS 0 --- 0 --- 0 --- ns Write recovery time (WE) tWR 0 --- 0 --- 0 --- ns Write recovery time (CE) tWR1 0 --- 0 --- 0 --- ns Output Low Z from end of write tWLZ* 3 --- 3 --- 3 --- ns Write to output in High Z tWHZ* --- 4 --- 5 --- 6 ns * These parameters are sampled and are not 100% tested Rev: 1.06 6/2000 8/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71116TP/J/U Write Cycle 1: WE control tWC Address tAW tWR OE tCW CE tBW UB, LB tAS tWP WE tDW tDH Data valid Data In tWHZ tWLZ Data Out High impedance Write Cycle 2: CE control tWC Address tAW tWR1 OE tAS tCW CE tBW UB, LB tWP WE tDW Data valid Data In Data Out Rev: 1.06 6/2000 tDH High impedance 9/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71116TP/J/U Write Cycle 3: UB, LB control tWC Address tAW tWR1 OE tAS tCW CE tBW UB, LB tWP WE tDW Data valid Data In Data Out Rev: 1.06 6/2000 tDH High impedance 10/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71116TP/J/U 44 Pin, 400 mil SOJ Symbol L D c HE GE 23 E 44 - - 0.148 - - 3.759 A1 0.025 - - 0.635 - - A2 0.105 0.110 0.115 2.667 2.794 2.921 - 0.457 - 0.660 0.711 0.813 - 0.203 - 28.44 28.58 28.70 B c 22 e A2 A A1 A B B1 Detail A Q - 0.018 - 0.026 0.028 0.032 - 0.008 - D 1.120 1.125 1.130 E 0.395 0.400 0.405 10.033 10.160 10.287 e y Dimension in mm min nom max A B1 1 Dimension in inch min nom max - 0.05 - - 1.27 - HE 0.435 0.440 0.445 11.049 11.176 11.303 GE 0.360 0.370 0.380 9.144 9.398 9.652 L 0.082 0.087 0.106 2.083 2.210 2.70 y - Q 0o - 0.004 - - 0.102 - 7o 0o - 7o Note: 1. Dimension D& E do not include interlead flash 2. Dimension B1 does not include dambar protrusion / intrusion Rev: 1.06 6/2000 11/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71116TP/J/U 44 Pin, 400 mil TSOP-II D c 22 e B L L1 A1 A y Detail A Rev: 1.06 6/2000 A - - 0.047 - - 1.20 A1 0.002 - - 0.05 - - A2 0.037 0.039 0.041 0.95 1.00 1.05 B 0.01 0.25 0.35 0.45 c - - 0.15 - Q 0.014 0.018 0.006 - D 0.721 0.725 0.729 18.31 18.41 18.51 E 0.396 0.400 0.404 10.06 10.16 10.26 e A2 1 A HE 23 E 44 Dimension in inch Dimension in mm Symbol min nom max min nom max - 0.031 - - 0.80 - HE 0.455 0.463 0.471 11.56 11.76 11.96 L 0.016 0.020 0.024 0.40 0.50 0.60 L1 - 0.031 - - 0.80 - y - - 0.004 - - 0.10 Q o - o o - 5o 0 5 0 Note: 1. Dimension D& E do not include interlead flash 2. Dimension B does not include dambar protrusion / intrusion 3. Controlling dimension: mm 12/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71116TP/J/U 6mm x 8mm Fine Pitch BGA 0.36(typ) D H G F E D C B A 0.22 ± 0.05 1 0.75(typ). 3.75 3 4 5.25 Rev: 1.06 6/2000 13/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Ball Dia. 0.35 Pitch 0.75 6 5 Bottom View 2 pin A1 index 1.20(max) pin A1 index units: mm Top View 6.00 ± 0.10 8.00 ± 0.10 0.10 © 1999, Giga Semiconductor, Inc. GS71116TP/J/U Ordering Information * Part Number* Package Access Time Temp. Range GS71116TP-10 400 mil TSOP-II 10 ns Commercial GS71116TP-12 400 mil TSOP-II 12 ns Commercial GS71116TP-15 400 mil TSOP-II 15 ns Commercial GS71116TP-10I 400 mil TSOP-II 10 ns Industrial GS71116TP-12I 400 mil TSOP-II 12 ns Industrial GS71116TP-15I 400 mil TSOP-II 15 ns Industrial GS71116J-10 400 mil SOJ 10 ns Commercial GS71116J-12 400 mil SOJ 12 ns Commercial GS71116J-15 400 mil SOJ 15 ns Commercial GS71116J-10I 400 mil SOJ 10 ns Industrial GS71116J-12I 400 mil SOJ 12 ns Industrial GS71116J-15I 400 mil SOJ 15 ns Industrial GS71116U-10 Fine Pitch BGA 10 ns Commercial GS71116U-12 Fine Pitch BGA 12 ns Commercial GS71116U-15 Fine Pitch BGA 15 ns Commercial GS71116U-10I Fine Pitch BGA 10 ns Industrial GS71116U-12I Fine Pitch BGA 12 ns Industrial GS71116U-15I Fine Pitch BGA 15 ns Industrial Status Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS71116TP-10T Rev: 1.06 6/2000 14/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71116TP/J/U Revision History Rev. Code: Old; New Types of Changes Page #/Revisions/Reason Format or Content Format/Content 1. 2. GSI Logo GS71116 Rev 1.05 2/2000;Rev1.06 2/2000M (not posted) Content 1. 2. Took all referenced to 8ns and 9ns speed bins out. Heading, Power Supply Currents, Read and Writ eCycle table, Ordering information. GS71116 Rev1.05 2/2000; Rev1.06 6/2000 (previous rev not posted) Content 1. 2. Added Standby Current numbers back into Power Supply Currents table Noted that numbers were max. GS711Rev1.05 10/19991/ 2000K;Rev 5 2/2000L Rev: 1.06 6/2000 15/15 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc.