ETC KL5KUSB101-L

KL5KUSB101
USB to Ethernet Controller
General Description
The Kawasaki KL5KUSB101 Controller is a unique single chip solution to interface peripheral
devices to the Universal Serial Bus (USB) and Ethernet. The KL5KUSB101 has been specifically
designed to provide a simple solution to communicate with Ethernet applications as well as other
USB peripheral devices. This has been accomplished by its highly integrated functionality. The
USB controller consists of a central 16-bit processor, mask ROM, RAM buffer, clock generator,
Ethernet interface, UART, IRQ, Watchdog Timer, Serial interface, External Memory Interface and
SPORT Interface. The SIE (Serial Interface Engine) is fully compatible with the USB specification.
This USB to Ethernet controller is ideal for LAN (Local Area Network), HAN (Home Area
Network), Cable Modem, Set Top Boxes, or Mobile Networking applications.
Features
•
Advanced 16 Bit processor for USB transaction
processing and control data processing
•
USB interface ver. 1.0/1.1 compliant
•
Transceivers and SIE (Serial Interface Engine)
•
Internal Clock Generation
•
Utilizes low cost external crystal circuitry
•
1.5K x 16 Internal RAM buffer
•
Serial Interface for external EEPROM
•
Watchdog timer
•
Fully IEEE 802.3 compliant 10 Mbit/sec
Ethernet MAC Layer. Interfaces serially of
an external ENDEC PHY.
•
UART
•
External memory interface
•
100 pin QFP and LQFP package
Block Diagram
Txd
Rxd
UART
CK
EEPROM
Serial Interface
DIO
Timer 0
Watchdog
Timer
16 Bit
Processor
A15-0
Timer 1
SRAM Interface
D15-0
Cntrl.
16 Bit Address / Data Bus
2
INT 1-0
8
IRQ
10Mb/s
Ethernet
Interface
RAM
(3KB)
Mask ROM
(8KB)
Serial
Interface
Engine
Clock
Generator
X1
X2
USB Interface
Data -
Data +
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
1
KL5KUSB101
USB to Ethernet Controller
KL5KUSB101 Application Block Diagram
KL5KUSB101
USB
USB /
Ethernet
PHY
Transformer
Full duplex
10 Base – T
Ethernet
Serial
EEPROM
Optional
External
Memory
KL5KUSB101
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
XA_10
XA_9
XA_8
XA_7
XA_6
XA_5
XA_4
XA_3
XA_2
XA_1
nTST
nRESET
nXROMSEL
nXWR
nXRD
GND
nPDN
N/C
N/C
N/C
N/C
LED_ON
nXRAMSEL
IGND
nXBHE
A0
XA_14
OVDD
VDD
XA_15
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PHTCLK
PHRXCLK
PHCRS
PH_RXD0
X_PCLK
RXD
IRQ1
IRQ2
N/C
N/C
N/C
N/C
SDA
SCL
N/C
N/C
N/C
OGND
CLK
X2
XD_15
VDD
VDD
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VDD
GND
PHTXD0
PHCOL
PHTXEN
PHRXER
PHRXDV
PHTXER
PHLPBK
PHUTP
TXD
UGND
VP
VM
UVDD
N/C
N/C
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
XD_14
OGND
XD_13
XD_12
IGND
XD_11
XD_10
XD_9
XD_8
XD_7
XD_6
XD_5
XD_4
XD_3
XD_2
XD_1
XD_0
XA_13
XA_12
XA_11
Pin Diagram 100QFP
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
2
KL5KUSB101
USB to Ethernet Controller
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDD
XD_15
XD_14
OGND
XD_13
XD_12
IGND
XD_11
XD_10
XD_9
XD_8
XD_7
XD_6
XD_5
XD_4
XD_3
XD_2
XD_1
XD_0
XA_13
XA_12
XA_11
XA_10
XA_9
XA_8
Pin Diagram 100LQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
KL5KUSB101_L
XA_7
XA_6
XA_5
XA_4
XA_3
XA_2
XA_1
nTST
nRESET
nXROMSEL
nXWR
nXRD
GND
nPDN
N/C
N/C
N/C
N/C
LED_ON
nXRAMSEL
IGND
nXBHE
A0
XA_14
OVDD
UVDD
N/C
N/C
PHTCLK
PHRXCLK
PHCRS
PH_RXD0
X_PCLK
RXD
IRQ1
IRQ2
N/C
N/C
N/C
N/C
SDA
SCL
N/C
N/C
N/C
OGND
CLK
X2
XA_15
VDD
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VDD
GND
PHTXD0
PHCOL
PHTXEN
PHRXER
PHRXDV
PHTXER
PHLPBK
PHUTP
TXD
UGND
VP
VM
Pin Description
Pin #
QFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin #
LQFP
99
100
1
2
3
4
5
6
7
8
9
10
11
12
I/O
Pin Name
IN/OUT
IN
IN
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
IN
XD_15
VDD
VDD
AGND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VDD
Description
External Data Pins
VDD
VDD
GND
Open connection
Open connection
Open connection
Open connection
Open connection
Open connection
Open connection
Open connection
Open connection
VDD
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
3
KL5KUSB101
USB to Ethernet Controller
Pin #
QFP
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin #
LQFP
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
I/O
Pin Name
IN
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
NC
NC
IN
IN
IN
IN
IN/OUT
IN/OUT
IN
IN
NC
NC
NC
NC
OUT
OUT
IN
NC
NC
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
OUT
OUT
N/C
N/C
N/C
N/C
OUT
GND
PHTXD0
PHCOL
PHTXEN
PHRXER
PHRXDV
PHTXER
PHLPBK
PHUTP
TXD
UGND
VP
VM
UVDD
NC
NC
PHTXCLK
PHRXCLK
PHCRS
PH_RXD0
X_PCLK
RXD
IRQ1
IRQ2
NC
NC
NC
NC
SDA
SCL
PU#1
NC
NC
OGND
CLK
X2
XA_15
VDD
OVDD
XA_14
XA0
nXBHE
IGND
nXRAMSEL
LED_ON
N/C
N/C
N/C
N/C
nPDN
Description
GND
Transmit data to PHY
Collision input from PHY
Transmit Enable to PHY
Receive Data Error from PHY
Receive Data Valid from PHY
Transmit Data Error to PHY
Loopback input to PHY
UTP/STP input to PHY
UART TXD
USB GND
USB + Pin
USB – Pin
USB VDD
NC
NC
PHY Transmit Clock
PHY Receive Clock
PHY Carrier Sense
PHY Serial Receive Data
External PCLK
UART RXD
Edge sens. Interrupt
Edge sens. Interrupt
Open connection
Open connection
Open connection
Open connection
SDA / EEPROM Serial Data
SCL / EEPROM Serial Clock
Pull up to USB + Pin for High Speed
Open connection
Open connection
GND
48MHz Clock/Crystal Input
48MHz Crystal Output
External Address Pin
VDD
VDD
External Address Pin
External Address Pin
External byte High Enable (Active low)
GND
External RAM CS (Active low)
Turns on 3.3V to TX LED
Open connection
Open connection
Open connection
Open connection
Active low Powerdown mode signal to Phy
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
4
KL5KUSB101
USB to Ethernet Controller
Pin #
QFP
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin #
LQFP
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
I/O
Pin Name
IN
OUT
OUT
N/C
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
GND
nXRD
nXWR
nXROMSEL
nRESET
nTST
XA_1
XA_2
XA_3
XA_4
XA_5
XA_6
XA_7
XA_8
XA_9
XA_10
XA_11
XA_12
XA_13
XD_0
XD_1
XD_2
XD_3
XD_4
XD_5
XD_6
XD_7
XD_8
XD_9
XD_10
XD_11
IGND
XD_12
XD_13
OGND
XD_14
Description
GND
External Memory Read (Active low)
External Memory Write (Active low)
External ROM CS, active LO
Reset Pin
Test Pin, Disconnect for Normal Operation
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
GND
External Data Pins
External Data Pins
GND
External Data Pins
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
5
KL5KUSB101
USB to Ethernet Controller
Function Description
16 Bit Processor
The integrated 16 bit processor serves as a micro controller for USB peripherals. The
processor can execute approximately five million instructions per second. With this
processing power it allows the design of intelligent peripherals that can process data prior
to passing it on to the host PC, thus improving overall performance of the system. The
masked ROM (4K X 16) in the KL5KUSB101 or external memory contains a specialized
instruction set that has been designed for highly efficient coding of processing algorithms
and USB transaction processing.
The 16-bit processor is designed for efficient data execution by having direct access to
the RAM Buffer, external memory, I/O interfaces, and all the control and status registers.
The divide/multiply feature expands the capability of USB peripherals.
The processor supports prioritized vectored hardware interrupts. In addition, as many as
240 software interrupt vectors are available.
The processor provides six addressing modes, supporting memory-to-memory, memoryto-register,
register-to-register,
immediate-to-register
or
immediate-to-memory
operations. Register, direct, immediate, indirect, and indirect indexed addressing modes
are supported. In addition, there is an auto-increment mode in which a register, used as
an address pointer is automatically incremented after each use, making repetitive
operations more efficient both from a programming and a performance standpoint.
The processor features a full set of program control, logical, and integer arithmetic
instructions. All instructions are sixteen bits wide, although some instructions require
operands, which may occupy another one or two words. Several special “ short
immediate” instructions are available, so that certain frequently used operations with
small constant operand will fit into a 16-bit instruction.
The Processor – Divide/Multiply function
The processor’s divide/multiply function contains all the instructions of the base
processor that additionally includes integer divide and multiply instructions. A signed
multiply an instruction take two 16-bit operands and returns a 32-bit result. A signed
divide instruction divides a 32-bit operand by a 16-bit operand.
RAM Buffer
The USB controller contains a 3K byte (1.5K X 16) internal buffer memory. The memory
is used to buffer data and USB packets and accessed by the 16 Bit processor and the
SIE. USB transactions are automatically routed to the memory buffer. The 16-bit
processor has the ability to set up pointers and block sizes in buffer memory for USB
transactions. Data is read from the interface and is processed and packetized by the 16bit I/O processor.
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
6
KL5KUSB101
USB to Ethernet Controller
USB Interface
The USB controller meets the Universal Serial Bus (USB) specification ver 1.0. The
transceiver is capable of transmitting and receiving serial data at the USB’s full speed, 12
Mbits/sec data rate. The driver portion of the transceiver is differential, while the receive
section is comprised of a differential receiver and two single ended receivers. Internally,
the transceiver interfaces to the SIE logic. Externally, the transceiver connects to the
physical layer of the USB.
10Mb/sec Ethernet Interface
The KL5KUSB101 Controller has a built in 10 Mbit/sec 10-base T Ethernet MAC (Media
Access Controller) which is fully compliant with the IEEE 802.3 Ethernet standard. The
KL5KUSB101 connects externally to a 10 Base -T ENDEC PHY. The KL5KUSB101
Controller 16-bit processor has direct access to the registers of the MAC.
UART Interface
Supports a transfer rate of 900 to 115.2K baud.
Serial EEPROM Support
The USB Controller serial interface is used to provide access to external EEPROM’s.
The interface can support a variety of serial EEPROM formats.
SRAM Interface
An address port and 16-bit data port has been provided to interface to an external SRAM.
DC CHARACTERISTICS
U2E is implemented with Kawasaki’s 0.5um CMOS CBA and Embedded
Memory KZ300EM Technology. The followings are the description of chip electric
characteristics.
1. Absolute Maximum Ratings
Table 5.1 Absolute Maximum Ratings
Parameter
Symbol
Ratings
Supply Voltage
Vdd
–0.3 ~ 4.0
Input Voltage
Vin
–0.3 ~ 7.3
DC Output Current
Iout
±15
Storage Temperature
Tstg
–55 ~ 125
Unit
V
V
mA
°C
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
7
KL5KUSB101
USB to Ethernet Controller
2. Recommended Operating Conditions
Table 5.2 Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Operating supply voltage
Vdd
3.0
–
Operating ambient temperature
Ta
0
–
Max
3.6
70
Unit
V
°C
3. I/O Electrical DC Characteristics (Over Recommended Range)
Table 3.1 DC Characteristics (over recommended range)
Parameter
Symbol
Min Typ
Max Unit
Test Conditions
Input low voltage
VIL
–
–
0.8
V
Input high voltage
VIH
2.0
–
–
V
Input low current
IIL
–10
–
10
uA VIN = Gnd
Input high current
IIH
–10
–
10
uA VIN = Vdd
Output low voltage
VOL
–
–
0.4
V
IOL = 4mA
Output high voltage
VOH
2.4
–
–
V
IOH = –4mA
3-state leak current
IOZ
–10
–
10
uA VOH = Gnd or VOL =
Vdd
Active pull-up current
IPU
–25
–66
–160
uA VIN = Gnd or VOH =
Gnd
VIN = Gnd or Vdd
Standby current
IDDS
–
80
100
uA No inputs are cycling.
Outputs open.
Same conditions as
Suspend current
ISUSP
–
350
450
uA IDDS
except for CLKI input
buffer 48MHz toggling.
IDDOP1
Outputs open.
(in busy)
–
80
100
mA Vdd = Max.
dynamic operating
FCLKI = FMAX (
current
IDDOP2
(in idle)
–
40
50
mA 48MHz )
Input capacitance
Output capacitance
CIN
–
–
15
pF
COUT
–
–
15
pF
Fpin=1MHz, VIN =
Gnd.
Vin = 100 mVrms
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
8
KL5KUSB101
USB to Ethernet Controller
AC CHARACTERISTICS
U2E chip has 4 types of interfaces – USB port, Ethernet PHY port, SRAM
port and Serial EEPROM port. AC timing of these interfaces are described
below along with appropriate timing charts. Chip also requires the AC timing
of system clock input CLKI and system reset RESETN.
1. CLKI and RESETN Signal
Figure 1.1 CLKI and RESETN AC Timing
Tckh
CLKI
(IN)
Tpck
Tckl
RESETN
(IN)
Tprst
Table 1.1 CLKI AC Characteristics (over recommended range)
Symbol
Parameter
Min
Typ
Max Unit Not
e
Tpck
CLKI one cycle time
–
20.83
–
ns
1
Fck
CLKI frequency
–
48
–
MH
1
z
Tckh
CLKI high time
10
–
–
ns
1
Tckl
CLKI low time
10
–
–
ns
1
Note: 1) The clock is used as an USB sampling clock and to
generate the internal 32MHz clock pulse.
Table 1.2 RESETN AC characteristics (over recommended range)
Symbol
Parameter
Min
Typ
Max Unit Not
e
Tprst
RESETN low pulse
10
–
–
Tpc
2
width
k
Note: 2) RESETN is an asynchronous, low assert, reset signal.
Minimum assertion is 10 times of Tpck (210 ns).
2. USB Interface
The USB signals – VP and VM are the pair signals of the differential output driver and
receiver. The USB to Ethernet operates under USB Full speed (12Mb/s).
USB signals are fully compatible with USB spec rev 1.1.
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
9
KL5KUSB101
USB to Ethernet Controller
3. PHY Interface
USB to Ethernet exchanges the serial bit data and messages to the external PHY chip.
3.1 U2E to PHY transmit
Figure 3.1.1 USB to Ethernet to PHY Transmit AC Timing
Ttch
Ttck
PHYTCLK
(IN)
Ttcl
Tden1
Tden2
PHYTEN
(OUT)
Tdtd1
PHYTXD
Tdtd2
first
last
(OUT)
98.09.02 updated
Table 3.1.1 PHY Transmit AC Characteristics (over recommended range)
Symbol
Parameter
Min
Typ
Max Unit Not
e
Ttck
PHYTCLK period
–
100
–
ns
1
Ftck
PHYTCLK frequency
–
10
–
MH
1
z
Ttch
PHYTCLK high width
–
50
–
ns
–
Ttcl
PHYTCLK low width
–
50
–
ns
–
Tden1
PHYTEN assert delay
from PHYTCLK rise
–
–
30
ns
2
Tden2
PHYTEN negate delay
from PHYTCLK fall
0
–
–
ns
2
Tdtd1
PHYTXD valid delay
from PHYTCLK rise
–
–
28
ns
2
Tdtd2
PHYTEN valid delay
from PHYTCLK fall
0
–
–
ns
2
Note: 1) PHY generates the 10MHz clock.
2) 30pF capacitor external load is assumed.
Figure 3.1.2 PHY SQE function AC Timing at Transmit
PHYTEN
(OUT)
Tcol
Tpco
PHYCOL
(IN)
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
10
KL5KUSB101
USB to Ethernet Controller
Table 3.1.2 PHY SQE Transmit AC Characteristics (over recommended range)
Symbol
Parameter
Min
Typ
Max Unit Not
e
Tcol
PHYCOL assert delay
–
–
1.6
us
–
from PHYTEN fall
Tpco
PHYCOL low width
0.5
–
–
us
–
3.2 U2E to PHY receive
Figure 3.2.1 U2E from PHY Receive AC Timing
Trck
Trch
PHYRCLK
(IN)
Trcl
Tscd
Thcd
PHYCD
(IN)
Thrd
Tsrd
PHYRXD
first
last
(IN)
Table 3.2.1 Receive from PHY AC Characteristics (over recommended range)
Symbol
Parameter
Min
Typ
Max Unit Not
e
Trck
PHYRCLK period
–
100
–
ns
1
Frck
PHYRCLK frequency
–
10
–
MH
1
z
Trch
PHYRCLK high width
–
50
–
ns
–
Trcl
PHYRCLK low width
–
50
–
ns
–
Tscd
PHYCD setup time
to PHYRCLK rise
20
–
–
ns
–
Thcd
PHYCD hold time
from PHYTCLK rise
10
–
–
ns
–
Tsrd
PHYRXD setup time
to PHYRCLK fall
20
–
–
ns
–
Thrd
PHYRXD hold time
from PHYRCLK fall
10
–
–
ns
–
Note: 1) PHY generates the 10MHz clock.
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
11
KL5KUSB101
USB to Ethernet Controller
4. SRAM Interface
4.1 SRAM Read Access
Figure 4.1.1 SRAM Read AC Timing
Trc
SRAMA14-0
(OUT)
valid
Taa
Thad
SRAMWEN
(OUT)
Tpoe
SRAMOEN
(OUT)
Thoe
Toe
Tpcs
SRAMCSN
(OUT)
SRAMD7-0
Thcs
Tacs
don't care
valid
(IN)
Table 4.1.1 SRAM Read AC Characteristics (over recommended range)
Symbol
Parameter
Min
Typ
Max Unit Not
e
Trc
SRAM read cycle
31.25
–
–
ns
1,2
Frc
SRAM read frequency
–
–
32
MH
1,2
z
Taa
SRAMA valid to
SRAMD
–
–
17
ns
2
delay (address access)
Thad
SRAMD hold time from
SRAMD invalid
2
–
–
ns
2
Tpoe
SRAMOEN low width
31.25
–
–
ns
2
Toe
SRAMOEN assert to
SRAMD delay
–
–
10
ns
2
Thoe
SRAMD hold time
from SRAMOEN rise
0
–
–
ns
2
Tpcs
SRAMCSN low width
31.25
–
–
ns
1,2
Tacs
SRAMCSN assert to
SRAMD delay
–
–
17
ns
2
Thcs
SRAMD hold time
from SRAMCSN rise
0
–
–
ns
2
Note: 1) Same as the USB to Ethernet internal clock cycle time 1T (31.25 ns).
2) Outputs are assumed to have 30pF external capacitive load.
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
12
KL5KUSB101
USB to Ethernet Controller
4.2 SRAM Write Access
Figure 4.2.1 SRAM Write AC Timing
Twc
valid
SRAMA14-0
(OUT)
Tdaw
Tdwa
Tdcw
Tdwc
SRAMOEN
(OUT)
SRAMCSN
(OUT)
Tpwe
SRAMWEN
(OUT)
Tdrv
SRAMD7-0
Tval
Tts
valid
(OUT)
Table 4.2.1 SRAM Write AC Characteristics (over recommended range)
Symbol
Parameter
Min
Typ
Max Unit Not
e
Twc
SRAM write cycle
31.25
–
–
ns
1,2
Fwc
SRAM write frequency
–
–
32
MH
1,2
z
Tdaw
SRAMWEN assert
delay
0
–
–
ns
2
from SRAMA valid
Tdwa
SRAMA invalid delay
from SRAMWEN
0
–
–
ns
2
negate
Tdcw
SRAMWEN assert
delay
0
–
–
ns
2
from SRAMCSN assert
Tdwc
SRAMCSN negate
delay
0
–
–
ns
2
from SRAMWEN
negate
Tpwe
SRAMWEN low width
25
–
–
ns
2
Tdrv
SRAMD drive delay
from SRAMWEN
0
–
–
ns
2
assert
Tval
SRAMD valid
from SRAMWEN
–
–
15
ns
2
assert
Tts
SRAMD hold time
from SRAMWEN rise
0
–
–
ns
2
Note: 1) Same as the USB to Ethernet internal clock cycle time 1T (31.25 ns).
2) Outputs are assumed to have 30pF external capacitive load.
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
13
KL5KUSB101
USB to Ethernet Controller
5. Serial EEPROM interface
The USB to Ethernet device communicates with the Serial EEPROM (SEP) through I²C™
bus.
5.1 Serial EEPROM Access Start
Figure 5.1.1 SEP Access Start AC Timing
SEPSCL
(OUT)
Tdckr(st)
Tdckf(st)
SEPSDA
(OUT)
Table 5.1.1 SEP Access Start AC Characteristics (over recommended range)
Symbol
Parameter
Min
Typ
Max Unit Not
e
Tdckr(st) SEPSDA fall delay
4.7
–
–
us
1
from SEPSCL rise
Tdckf(st) SEPSCL fall delay
4.0
–
–
us
1
from SEPSDA fall
Note: 1) 30pF external capacitive load is assumed.
5.2 Serial EEPROM Access Stop
Figure 5.2.1 SEP Access Stop AC Timing
SEPSCL
(OUT)
Tdckr(sp)
SEPSDA
(OUT)
Table 5.2.1 SEP access stop AC characteristics (over recommended range)
Symbol
Parameter
Min
Typ
Max Unit Not
e
Tdckr(sp) SEPSDA rise delay
4.0
–
–
us
1
from SEPSCL rise
Note: 1) 30pF external capacitive load is assumed.
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
14
KL5KUSB101
USB to Ethernet Controller
5.3 Serial EEPROM Read Access
Figure 5.3.1 SEP Read Access AC Timing
SEPSCL
(OUT)
Tsd
Thd
valid
SEPSDA
(IN)
Table 5.3.1 SEP read access AC characteristics (over recommended range)
Symbol
Parameter
Min
Typ
Max Unit Not
e
Tsd
SEPSDA setup time
20
–
–
ns
1
from SEPSCL rise
Thd
SEPSDA hold time
0
–
–
ns
1
from SEPSCL fall
Note: 1) 30pF external capacitive load is assumed.
5.4 Serial EEPROM Write Access
Figure 5.4.1 SEP Write Access AC Timing
Tckf
Tpckh
SEPSCL
(OUT)
Tpckl
Tdd
SEPSDA
valid
(OUT)
Table 5.4.1 SEP Write Access AC Characteristics (over recommended range)
Symbol
Parameter
Min
Typ
Max Unit Not
e
Tsck
SEPSCL clock period
10
–
–
us
1
Fsck
SEPSCL frequency
–
–
100
kHz
1
Tpckl
SEPSCL low width
4.7
–
–
us
1
Tpckh
SEPSCL high width
4.0
–
–
us
1
Tdd
SEPSDA valid delay
2
–
20
ns
1
from SEPSCL fall
Note: 1) 30pF external capacitive load is assumed.
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
15
KL5KUSB101
USB to Ethernet Controller
6. Serial EEPROM Access Timing
Serial EEPROM Byte Write, Page Write, Current Address Read, Random Read
and Sequential Read Timings are shown below. Please refer to Serial EEPROM
datasheet ([12] 3-b) for more detail.
6.1 Serial EEPROM Byte Write
Figure 6.1.1 SEP Byte Write Timings
SEPSCL
(OUT)
SEPSDA
(L)
(I/O)
status
(L)
(L)
b2b1b0 0 Aa7a6a5a4a3a2a1a0 Ad7d6d5d4d3d2d1d0 A S
idle S 1 0 1 0
byte data
T control byte
K word address K
KP
(H)
S control
T
idle
NS
KT
(L)
control
A
K
Twr = max 10ms for internal wr operation
(ack polling needed to start next tran)
6.2 Serial EEPROM Page Write (up to 16 bytes)
Figure 6.2.1 SEP Page Write Timings
status
w
A dat N
idle S control A
T
K addrN K
(L)
(L)
A
K
(L)
dat
N+1
A
K
dat
N+1
(L)
A
K
(L)
max
N+15
A S idle (internal programming cycle)
KP
(L)
6.3 Serial EEPROM Byte Read from current address
Figure 6.3.1 SEP Byte Read Timings
SEPSCL
(OUT)
SEPSDA
(I/O)
status
(L)( 7 () 6 )( 5 () 4 () 3 () 2 () 1 )( 0 )
idle
S 1 0 1 0 b2 b1b0 1 Ad7d6d5d4 d3 d2d1d0 N S
control byte
read data
T
K
KP
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
16
KL5KUSB101
USB to Ethernet Controller
6.4 Serial EEPROM Byte Random Read
Figure 6.4.1 SEP Byte Random Read Timings
SEPSCL
(OUT)
SEPSDA
(I/O)
status
(L)
idle
(L)(7)(6)(5)(4)(3)(2)(1)(0)
(L)
S 1 0 1 0 b2b1b0 0 Aa7 a6 a5a4a3 a2a1a0 A S 1 0 1 0 b2b1b0 1 Ad7 d6d5d4d3 d2d1d0 N S
T control byte
K word address K T control byte
K
read data
KP
6.5 Serial EEPROM Sequential Read (up to final address)
Figure 6.5.1 SEP Sequential Read Timings
status
w
A S cntrl r
idle S cntrl w A
T
K addrN K T
(L)
(L)
A input
K
L input
L
(L) (dat N) AK(dat N+1)AK
dat
N+1
L last in
HS
P
AK
NK
Kawasaki LSI assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the
information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or
consequential damages. There are no warranties extended or granted by this document. The information herein is subject to change without notice
form Kawasaki LSI
November 1998 • Copyright 1998 • Kawasaki LSI • Printed in U.S.A
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.4
17