SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Features Description ■ ■ ■ ■ ■ ■ The S29C51004T/S29C51004B is a high speed 524,288 x 8 bit CMOS flash memory. Writing or erasing the device is done with a single 5 Volt power supply. The device has separate chip enable CE, write enable WE, and output enable OE controls to eliminate bus contention. The S29C51004T/S29C51004B offers a combination of: Boot Block with Sector Erase/Write Mode. The end of write/erase cycle is detected by DATA Polling of I/O7 or by the Toggle Bit I/O6. TheS29C51004T/S29C51004B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. The device also supports full chip erase. Boot block architecture enables the device to boot from a protected sector located either at the top (S29C51004T) or the bottom (S29C51004B). All inputs and outputs are CMOS and TTL compatible. The S29C51004T/S29C51004B is ideal for applications that require updatable code and data storage. ■ ■ ■ ■ ■ ■ ■ 512Kx8-bit Organization Address Access Time: 70, 90, 120 ns Single 5V ± 10% Power Supply Sector Erase Mode Operation 16KB Boot Block (lockable) 1K bytes per Sector, 512 Sectors – Sector-Erase Cycle Time: 10ms (Max) – Byte-Write Cycle Time: 35µs (Max) Minimum 10,000 Erase-Program Cycles Low power dissipation – Active Read Current: 20mA (Typ) – Active Program Current: 30mA (Typ) – Standby Current: 100 µA (Max) Hardware Data Protection Low VCC Program Inhibit Below 3.5V Self-timed write/erase operations with end-of-cycle detection – DATA Polling – Toggle Bit CMOS and TTL Interface Available in one versions – S29C51004T (Top Boot Block) ■ Packages: – 32-pin Plastic DIP – 32-pin TSOP-I – 32-pin PLCC S29C51004T/S29C51004B V1.0 May 2002 1 SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY 29 S C 51 004 T – DEVICE OPERATING VOLTAGE 51: 5V SPEED P = PDIP T = TSOP-I J = PLCC 70: 70ns 90: 90ns 12: 120ns BOOT BLOCK LOCATION T: TOP B: BOTTOM PKG. 51004-01 CE I/O7 I/O6 I/O5 I/O4 I/O3 A17 WE A16 A18 VCC A15 A7 5 29 A14 A6 A5 A4 A3 A2 A1 A0 I/O0 6 28 7 27 8 26 A13 A8 A9 A11 OE A10 CE I/O7 32 Pin PLCC Top View 9 25 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 I/O6 21 20 19 18 17 1 32 31 30 I/O5 11 12 13 14 15 16 2 I/O4 23 22 3 I/O3 8 9 10 28 27 32-Pin PDIP 26 Top View 25 24 4 GND A0 I/O0 I/O1 I/O2 GND 3 4 5 6 7 VCC WE A17 A14 A13 A8 A9 A11 OE A10 I/O2 A4 A3 A2 A1 32 31 30 29 1 2 I/O1 A18 A16 A15 A12 A7 A6 A5 Pin Names A12 Pin Configurations 51004-02 A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-Pin TSOP I Standard Pinout Top View 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 51004-04 S29C51004T/S29C51004B V1.0 May 2002 2 51004-03 A0–A18 Address Inputs I/O0–I/O7 Data Input/Output CE Chip Enable OE Output Enable WE Write Enable VCC 5V ± 10% Power Supply GND Ground NC No Connect SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Functional Block Diagram 4,194,304 Bit Memory Cell Array X-Decoder A0–A18 Address buffer & latches CE OE WE Control Logic Y-Decoder I/O Buffer & Data Latches I/O0–I/O7 51004-07 Capacitance (1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance CIN2 Control Pin Capacitance Test Setup Typ. Max. Units VIN = 0 6 8 pF VOUT = 0 8 12 pF VIN = 0 8 10 pF NOTE: 1. Capacitance is sampled and not 100% tested. 2. TA = 25°C, VCC = 5V ± 10%, f = 1 MHz. Latch Up Characteristics(1) Parameter Min. Max. Unit Input Voltage with Respect to GND on A9, OE -1 +13 V Input Voltage with Respect to GND on I/O, address or control pins -1 VCC + 1 V -100 +100 mA VCC Current NOTE: 1. Includes all pins except VCC. Test conditions: VCC = 5V, one pin at a time. AC Test Load +5.0 V IN3064 or Equivalent 2.7 kΩ Device Under Test IN3064 or Equivalent CL = 100 pF 6.2 kΩ IN3064 or Equivalent IN3064 or Equivalent 51004-08 S29C51004T/S29C51004B V1.0 May 2002 3 SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Absolute Maximum Ratings(1) Symbol Parameter Commercial Industrial Unit VIN Input Voltage (input or I/O pins) -2 to +7 -2 to +7 V VIN Input Voltage (A9 pin, OE) -2 to +13 -2 to +13 V VCC Power Supply Voltage -0.5 to +5.5 -0.5 to +5.5 V TSTG Storage Temerpature (Plastic) -65 to +125 -65 to +150 °C TOPR Operating Temperature 0 to +70 -40 to + 85 °C IOUT Short Circuit Current(2) 200 (Max.) 200 (Max.) mA NOTE: 1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. No more than one output maybe shorted at a time and not exceeding one second long. DC Electrical Characteristics (over the commercial operating range) Parameter Name Parameter Test Conditions VIL Input LOW Voltage VIH Min. Max. Unit VCC = VCC Min. — 0.8 V Input HIGH Voltage VCC = VCC Max. 2 — V IIL Input Leakage Current VIN = GND to VCC, VCC = VCC Max. — ±1 µA IOL Output Leakage Current VOUT = GND to VCC, VCC = VCC Max. — ±10 µA VOL Output LOW Voltage VCC = VCC Min., IOL = 2.1mA — 0.4 V VOH Output HIGH Voltage VCC = VCC Min, IOH = -400µA 2.4 — V ICC1 Read Current CE = OE = VIL, WE = VIH, all I/Os open, Address input = VIL/VIH, at f = 1/tRC Min., VCC = VCC Max. — 30 mA ICC2 Write Current CE = WE = VIL, OE = VIH, VCC = VCC Max. — 40 mA ISB TTL Standby Current CE = OE = WE = VIH, VCC = VCC Max. — 1 mA ISB1 CMOS Standby Current CE = OE = WE = VCC – 0.3V, VCC = VCC Max. — 100 VH Device ID Voltage for A9 CE = OE = VIL, WE = VIH 11.5 12.5 V IH Device ID Current for A9 CE = OE = VIL, WE = VIH, A9 = VH Max. — 50 µA S29C51004T/S29C51004B V1.0 May 2002 4 µA SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY AC Electrical Characteristics Read Cycle Parameter Name -70 Parameter -90 -12 Min. Max. Min. Max. Min. Max. Unit tRC Read Cycle Time 70 — 90 — 120 — ns tAA Address Access Time — 70 — 90 — 120 ns tACS Chip Enable Access Time — 70 — 90 — 120 ns tOE Output Enable Access Time — 35 — 45 — 60 ns tCLZ CE Low to Output Active 0 — 0 — 0 — ns tOLZ OE Low to Output Active 0 — 0 — 0 — ns tDF OE or CE High to Output in High Z 0 30 0 40 0 50 ns tOH Output Hold from Address Change 0 — 0 — 0 — ns Program (Erase/Program) Cycle Parameter Name Parameter -70 -90 -12 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit tWC Write Cycle Time 70 — — 90 — — 120 — — ns tAS Address Setup Time 0 — — 0 — — 0 — — ns tAH Address Hold Time 45 — — 45 — — 50 — — ns tCS CE Setup Time 0 — — 0 — — 0 — — ns tCH CE Hold Time 0 — — 0 — — 0 — — ns tOES OE Setup Time 0 — — 0 — — 0 — — ns tOEH OE High Hold Time 0 — — 0 — — 0 — — ns tWP WE Pulse Width 35 — — 45 — — 50 — — ns WE Pulse Width High 20 — — 30 — — 35 — — ns tDS Data Setup Time 30 — — 30 — — 30 — — ns tDH Data Hold Time 0 — — 0 — — 0 — — ns tWHWH1 Programming Cycle — — 35 — — 35 — — 35 µs tWHWH2 Sector Erase Cycle — — 10 — — 10 — — 10 ms tWHWH3 Chip Erase Cycle — — 3.0 — — 3.0 — — 3.0 sec tWPH S29C51004T/S29C51004B V1.0 May 2002 5 SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Waveforms of Read Cycle tRC ADDRESS tAA tCE CE tOE tDF OE tOLZ WE tCLZ HIGH-Z I/O tOH VALID DATA OUT HIGH-Z VALID DATA OUT 51004-09 tAA Waveforms of WE Controlled-Program Cycle 3rd bus cycle tWC tAS 5555H ADDRESS PA(2) PA tCH tRC tAH CE OE tWHWH1 tWP tOES WE tDF tWPH tCS tDS tOE tDH I/O A0H PD(3) I/O7(1) DOUT tOH 51004-10 NOTES: 1. I/O7: The output is the complement of the data written to the device. 2. PA: The address of the memory location to be programmed. 3. PD: The data at the byte address to be programmed. S29C51004T/S29C51004B V1.0 May 2002 6 SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Waveforms of CE Controlled-Program Cycle tWC ADDRESS 5555H PA(1) PA tAS tRC tAH WE OE tWP tWHWH1 CE tDF tWPH tOES tDS tOE tDH I/O PD(2) A0H I/O7 DOUT tOH 51004-11 Waveforms of Erase Cycle(1) tWC ADDRESS (5555H for Chip Erase) tAS 5555H 2AAAH 5555H 5555H 2AAAH SA tAH CE OE tWP WE tWHWH 2 tWPH tCS 3 tDS (10H for Chip Erase) tDH I/O AAH 55H 80H AAH 55H 30H 51004-12 NOTES: 1. PA: The address of the memory location to be programmed. 2. PD: The data at the byte address to be programmed. 3. SA: The sector address for Sector Erase. S29C51004T/S29C51004B V1.0 May 2002 7 SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Waveforms of DATA Polling Cycle tCH CE tDF tOE OE tOEH tCE WE tWHWH1 (2 or 3) I/O7 I/O0-I/O6 I/O7 I/O7 INVALID I/O0-I/O6 tOH VALID DATA OUT VALID DATA OUT HIGH-Z HIGH-Z 51004-13 Waveforms of Toggle Bit Cycle CE tOEH WE OE I/O6 stop toggling tWHWH1 (2 or 3) 51004-14 S29C51004T/S29C51004B V1.0 May 2002 8 SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Functional Description S29C51004T The S29C51004T/S29C51004B consists of 512 equally-sized sectors of 1K bytes each. The 16 KB lockable Boot Block is intended for storage of the system BIOS boot code. The boot code is the first piece of code executed each time the system is powered on or rebooted. The S29C51004 is available in two versions: the S29C51004T with the Boot Block address starting from 7C000H to 7FFFFH, and the S29C51004B with the Boot Block address starting from 00000H to 3FFFFH. 16KB Boot Block S29C51004B 7FFFFH 1 KB 7C000H 1 KB 1 KB 1 KB 1 KB Read Cycle 00000H 03FFFH 1 KB 00000H 16KB Boot Block 51004-15 A read cycle is performed by holding both CE and OE signals LOW. Data Out becomes valid only when these conditions are met. During a read cycle WE must be HIGH prior to CE and OE going LOW. WE must remain HIGH during the read operation for the read to complete (see Table 1). 16KB Boot Block = 32 Sectors During the byte write cycle, addresses are latched on the falling edge of either CE or WE, whichever is last. Data is latched on the rising edge of CE or WE, whichever is first. The byte write cycle can be CE controlled or WE controlled. Output Disable Sector Erase Cycle Returning OE or CE HIGH, whichever occurs first will terminate the read operation and place the l/O pins in the HIGH-Z state. The S29C51004T/S29C51004B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. Sector erase operation is initiated by using a specific six-bus-cycle sequence: Two unlock program cycles, a setup command, two additional unlock program cycles, and the sector erase command (see Table 2). A sector must be first erased before it can be rewritten. While in the internal erase mode, the device ignores any program attempt into the device. The internal erase completion can be determined via DATA polling or toggle bit status. The S29C51004T/S29C51004B is shipped fully erased (all bits = 1). Standby The device will enter standby mode when the CE signal is HIGH. The l/O pins are placed in the HIGH-Z, independent of the OE input state. Byte Write Cycle The S29C51004T/S29C51004B is programmed on a byte-by-byte basis. The byte write operation is initiated by using a specific four-bus-cycle sequence: two unlock program cycles, a program setup command and program data program cycles (see Table 2). Table 1. Operation Modes Decoding Decoding Mode CE OE WE A0 A1 A9 I/O Read Byte Write Standby Autoselect Device ID Autoselect Manufacture ID Enabling Boot Block Protection Lock Disabling Boot Block Protection Lock Output Disable VIL VIL VIH VIL VIL VIL VH VIL VIL VIH X VIL VIL VH VH VIH VIH VIL X VIH VIH VIL VIL VIH A0 A0 X VIH VIL X X X A1 A1 X VIL VIL X X X A9 A9 X VH VH VH VH X READ PD HIGH-Z CODE CODE X X HIGH-Z NOTES: 1. X = Don’t Care, VIH = HIGH, VIL = LOW, VH = 12.5V Max. 2. PD: The data at the byte address to be programmed. S29C51004T/S29C51004B V1.0 May 2002 9 SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Table 2. Command Codes First Bus Program Cycle Second Bus Program Cycle Third Bus Program Cycle Fourth Bus Program Cycle Fifth Bus Program Cycle Six Bus Program Cycle Command Sequence Address Data Address Data Address Data Address Data Address Data Address Data Read XXXXH F0H Read 5555H AAH 2AAAH 55H 5555H F0H RA(1) RD(2) Autoselect Mode 5555H AAH 2AAAH 55H 5555H 90H See table 3 for detail. Byte Program 5555H AAH 2AAAH 55H 5555H A0H PA PD(4) Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Sector Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA(5) 30H NOTES: 1. RA: Read Address 2. RD: Read Data 3. PA: The address of the memory location to be programmed. 4. PD: The data at the byte address to be programmed. 5. SA(5): Sector Address Chip Erase Cycle Toggle Bit (I/O6) The S29C51004T/S29C51004B features a chiperase operation. The chip erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup command, two additional unlock program cycles, and the chip erase command (see Table 2). The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and terminates when the data on DQ7 is “1”. The S29C51004T/S29C51004B also features another method for determining the end of a program cycle. When the device is in the program cycle, any attempt to read the device will result in l/O6 toggling between 1 and 0. Once the program is completed, the toggling will stop. The device is then ready for the next operation. Examining the toggle bit may begin at any time during a program cycle. Program Cycle Status Detection The S29C51004T/S29C51004B features hardware Boot Block Protection. The boot block sector protection is enabled when high voltage (12.5V) is applied to OE and A9 pins with CE pin LOW and WE pin LOW. The sector protection is disabled when high voltage is applied to OE, CE and A9 pins with WE pin LOW. Other pins can be HIGH or LOW. This is shown in table 1. Boot Block Protection Enabling/Disabling There are two methods for determining the state of the S29C51004T/S29C51004B during a program (erase/write) cycle: DATA Polling (I/O7) and Toggle Bit (I/O6). DATA Polling (I/O7) The S29C51004T/S29C51004B features DATA polling to indicate the end of a program cycle. When the device is in the program cycle, any attempt to read the device will received the complement of the loaded data on I/O7. Once the program cycle is completed, I/O7 will show true data, and the device is then ready for the next cycle. S29C51004T/S29C51004B V1.0 May 2002 Autoselect Mode The S29C51004T/S29C51004B features an Autoselect mode to identify boot block locking status, device ID and manufacturer ID. Entering Autoselect mode is accomplished by applying a high voltage (VH) to the A9 Pin, or through a sequence of commands (as shown in table 2). Device will exit this mode once high voltage on A9 is removed or another command is loaded into the device. 10 SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Boot Block Protection Status Manufacturer ID In Autoselect mode, performing a read at address location 3CXX2H (S29C51004T) or 0CXX2H (S29C51004B) will indicate boot bloc protection status. If the data is 01H, the boot block is protected. If the data is 00H, the boot block is unprotected. This is also shown is table 3. In Autoselect mode, performing a read at address XXXX0H will determine the manufacturer ID.40H is the manufacturer code for SyncMOS Flash. Hardware Data Protection VCC Detection: the program operation is inhibited when VCC is less than 3.5V. Noise Protection: a CE or WE pulse of less than 5ns will not initiate a program cycle. Program Inhibit: holding any one of OE LOW, CE HIGH or WE HIGH inhibits a program cycle. Device ID In Autoselect mode, performing a read at address XXX1H will determine whether the device is a Top Boot Block device or a Bottom Boot Block device. If the data is 03H, the device is a Top Boot Block. If the data is A3H, the device is a Bottom Boot Block device (see Table 3). Table 3. Autoselect Decoding Address Decoding Mode Boot Block A0 A1 A2–A13 A14–A17 Boot Block Protection Top VIL VIH X VIH 01H: protected Bottom VIL VIH X VIL 00H: unprotected Top VIH VIL X X Device ID Bottom Manufacture ID VIL V1.0 May 2002 03H A3H VIL NOTE: 1. X = Don’t Care, VIH = HIGH, VIL = LOW. S29C51004T/S29C51004B Data I/O0–I/O7 11 X X 40H SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Byte Program Algorithm Chip/Sector Erase Algorithm Write Byte-Write Command Sequence Write Erase Command Sequence Add/Data 5555H/AAH Add/Data 5555H/AAH 2AAAH/55H 2AAAH/55H Four Bus Cycle Sequence 5555H/A0H 5555H/80H Six Bus Cycle Sequence PA/PD 5555H/AAH Data Polling or Toggle bit successfully completed or tWTWH (2 or 3) timeout 2AAAH/55H 5555H/10H (Chip Erase) SA/30H (Sector Erase) Writing Completed Data Polling or Toggle bit successfully completed or tWTWH (2 or 3) timeout Erase Completed 51004-16 S29C51004T/S29C51004B V1.0 May 2002 12 SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY DATA Polling Algorithm No Toggle Bit Algorithm Read I/O7 Address = PBA(1) Read I/O6 I/O7 = Data Read I/O6 Yes Yes I/O6 Toggle Program Done No Program Done 51004-17 NOTE: 1. PBA: The byte address to be programmed. S29C51004T/S29C51004B V1.0 May 2002 13 SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Package Diagrams 32-pin Plastic DIP 1.660 MAX. 15° MAX INDEX-1 EJECTOR MARK .600 TYP 0.545/0.555 INDEX-2 +.004 .010 – .0004 .050 MAX 0.210 MAX 0.120 MIN .100 TYP +.006 .018 – .002 +.012 .047 – 0 0.010 MIN .032 +.012 –0 32-pin PLCC 20 19 18 17 16 15 14 21 13 22 12 23 11 24 10 25 9 26 8 27 7 28 .590 ± .005 .550 ± .003 6 29 30 31 32 1 2 3 4 5 .045X45° .450 ± .003 .110 .490 ± .005 .136 ± .003 .046 ± .003 .025 .050 TYP 30° .017 .420 ± .003 S29C51004T/S29C51004B V1.0 May 2002 3° - 6° 3° - 6° 14 3° - 6° SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY 32-pin TSOP-I Units in inches Detail “A” 0.787 ± 0.008 0.010 0.315 TYP. (0.319 MAX.) 0.024 ± 0.004 0.724 TYP. (0.728 MAX.) 0.035 ± 0.002 SEATING PLANE See Detail “A” 0.032 TYP. 0.020 SBC 0.005 MIN. 0.007 MAX. S29C51004T/S29C51004B V1.0 May 2002 0.047 MAX. 0.020 MAX. 0.003 MAX 15 0.009 ± 0.002 SyncMOS Technologies Inc. S29C51004T/S29C51004B 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Sales Office : 4th Floor, No. 1, Creation Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan 30077 Tel : 886-3-5792988 Fax : 886-3-5792960 Note : 1. Publication date : November 1998 Rev. A , May 2002 Rev. B 2. All data and specification are subject changed with Program (Erase/Program) Cycle as below description : a. Chip erase time : 2.0 sec → 3.0 sec maximum. b. Byte program time : 20 usec → 35 usec maximum S29C51004T/S29C51004B V1.0 May 2002 16