Preliminary Data Sheet September 2000 W7020 Bluetooth* Radio Module Features + Complete Bluetooth RF solution + Compliant with Bluetooth specification version 1.0 + Highly integrated module including an RF transceiver IC, antenna filter, and transmit/receive baluns n Digital receive signal strength indicator (RSSI) n Small-outline module ceramic land grid array (MCLGA) package (9.7 x 14.0 x 1.6 mm) Applications n Cellular phones + 0 dBm output power at 50 Ω n PCs and peripherals + 2.7 V operation enabling long battery life n PDAs + 3.2 kHz low-power idle-mode clock n Consumer appliances RX BALUN 135° LNA 90° 2402 MHz to 2495 MHz 0 dBm/–70 dBm ANTENNA FILTER φ LIMITER 45° Radio ASIC TX AMPLIFIER ANTENNA SWITCH RECEIVER DATA OUT S VCO BUFFER DISCRIMINATOR 13 MHz CLOCK GENERATION 1 MHz 3.2 kHz INTEGER N PLL TX BALUN GLPF W7020 RADIO MODULE NOTE: SHADED AREA IS EXTERNAL TO MODULE TANK TRANSMITTER DATA IN Figure 1. Circuit Block Diagram *Bluetooth is a trademark of Telefonaktiebolaget LM Ericsson. LPF UNLOCK PLL 13 MHz XTAL Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Table of Contents Features...............................................................................................................................................................1 Applications .........................................................................................................................................................1 Description...........................................................................................................................................................3 Pin Information.....................................................................................................................................................5 Absolute Maximum Ratings..................................................................................................................................6 Handling Precautions ...........................................................................................................................................6 Operating Range..................................................................................................................................................7 Operating Conditions............................................................................................................................................7 Digital Inputs/Outputs...........................................................................................................................................7 Electrical Characteristics ......................................................................................................................................8 Supply Currents................................................................................................................................................8 Power Consumption..........................................................................................................................................8 Transmit Performance ......................................................................................................................................9 Receiver Performance....................................................................................................................................10 Synthesizer Performance................................................................................................................................10 Interface Signal Description ...............................................................................................................................11 Serial Interface...................................................................................................................................................12 CAP State Diagram ........................................................................................................................................13 Reserved Instructions .....................................................................................................................................15 W7020 Registers ............................................................................................................................................15 Channel Register Programming Example .......................................................................................................21 Transmit and Receiver Application.....................................................................................................................22 Application Circuit Diagram ............................................................................................................................22 Timing Information .........................................................................................................................................23 Power-On Reset and XO Start-Up ..................................................................................................................24 Powerup Initialization ..................................................................................................................................25 Wake-Up for Connection .............................................................................................................................26 RSSI...............................................................................................................................................................27 Characteristic Curves.........................................................................................................................................28 Soldering Profile ................................................................................................................................................34 Outline Diagram.................................................................................................................................................35 34-pin MCLGA................................................................................................................................................35 Manufacturing Information .................................................................................................................................36 Ordering Information ..........................................................................................................................................36 2 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Description The W7020 Bluetooth radio module is a short-range microwave-frequency radio transceiver for Bluetooth links. It operates in the globally available 2.4 GHz to 2.5 GHz ISM free band. The radio is based on a bipolar complementary metal-oxide semiconductor (BiCMOS) RFIC. The antenna filter and the RX and TX baluns are all integrated into the radio module. As illustrated in Figure 2, the radio module requires only a baseband controller, an external antenna connected through a 50 Ω characteristic impedance line, and a 13 MHz crystal or reference clock signal. It is controlled by the digital baseband circuit through the serial interface bus and separate strobe signals. The TX and RX data pins also connect to the baseband with a maximum bit rate of 1 Mbit/s. The power supply is partitioned into two paths, one for the VCO circuit and one for all other module supply connections. Each of the supplies should be externally low-frequency decoupled. Fast-frequency hopping (FFH) of 1600 hops/s is used with a channel spacing of 1 MHz so that the radio link is less sensitive to signal fading due to multipath; therefore, antenna diversity is not required. The modulation is Gaussian frequency shift keying (GFSK) with a BT product of 0.5. The channel bandwidth is 1 MHz and the modulation index is between 0.28 and 0.35. A binary one is indicated by a positive frequency deviation, and a binary zero is indicated by a negative frequency deviation. ANTENNA BASEBAND INTERFACE 17 CLOCK CONTROL OUTPUTS 34 POWER SUPPLIES 2 VCC 11 SUPPLY REGULATOR VCC-VCO 31 20 13 MHz REFERENCE CLOCK XO_N 27 26 100 pF 7 XO_P TX_CLK (1 MHz) LPO_CLK (3.2 kHz) SERIAL INTERFACE 25 8 SYS_CLK (13 MHz) 29 W7020 RADIO SUBSYSTEM 33 24 21 3 5 32 SI_CLK (4 MHz) SI_CDI (DATA) SI_CMS (MODE SELECT) SI_CDO (DATA OUTPUT) STROBE INPUTS BASEBAND IC SYS_CLK_REQ SYNT_ON PHD_OFF TX_ON RX_ON PX_ON DATA INTERFACE 22 4 TX_DATA RX_DATA RESET SIGNALS GND 1, 6, 10, 13, 14, 15, 16, 18, 19, 23, 28 30 9 POR (DELAYED RESET) POR_EXT HOST CONTROLLER Figure 2. System Connections Lucent Technologies Inc. 3 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Description (continued) As shown in Figure 3, the antenna filter bandpass filters the radio signal to the antenna switch. The switch directs the signal to the RX balun or from the TX balun. The RX balun performs the transformation from unbalanced to balanced for the RX signal and connects to the low-noise amplifier (LNA). The LNA is followed by an image rejection mixer, so no additional image filter is needed before the mixer. The IF signal out of the mixer is filtered by a bandpass filter and followed by a limiting amplifier and frequency discriminator, giving the RX data output. This discriminator output is offset-corrected. The receiver IF and detection circuits are all integrated, requiring no external components. The RSSI level is available digitally through the serial interface. The transmitter path utilizes direct modulation of the TX data-bit stream onto the VCO. The TX data is shaped by the Gaussian filter and then is applied to the VCO tank. The VCO is buffered internally and driven to the TX balanced output through another amplifier stage. The TX balun performs the transformation of the balanced to unbalanced signal and connects to the antenna switch. NC VCC GND POR_EXT XO_N XO_P GND RX_ON RX_DATA TX_ON TX_CLK GND The VCO frequency operating in the 2.4 GHz ISM band is controlled by the phase-locked loop (PLL) synthesizer through the loop filter. The reference clock oscillator is provided so that only a crystal resonator needs to be added externally to the module, or the reference clock input can be overdriven with an external signal such as from a TCXO or VCXO. The frequency accuracy requirement is ±20 ppm. 11 10 9 8 7 6 5 4 3 2 1 12 34 SYS_CLK 33 SYS_CLK_REQ 32 PX_ON 31 LPO_CLK 30 POR 29 SI_CDO XO GND 13 GND 14 LNA RX BALUN SWITCH ∑ TX AMP VCO TANK LO PLL 17 ANTENNA FILTER 18 19 20 21 22 23 24 25 26 27 28 TX_DATA GND SYNT_ON SI_CLK SI_CMS SI_CDI GND GLPF PHD_OFF ANT LOOP FILTER VCC_VCO 16 GND GND GND 15 DISC Φ TX BALUN GND BPF Figure 3. Module Block Diagram with Pinout 4 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Pin Information Table 1. Pin Descriptions Pin # Symbol Type* Description 1 GND Ground 2 TX_CLK D Output 3 TX_ON D Input 4 RX_DATA D Output Received data input 5 RX_ON D Input Receiver power on 6 GND Ground Common ground 7 XO_P A Input Crystal positive input 8 XO_N A Input Crystal negative input or external clock input 9 POR_EXT D Input External power-on reset 10 GND Ground Common ground 11 VCC Power Common power supply 12 NC — 13 GND Ground Common ground 14 GND Ground Common ground 15 GND Ground Common ground 16 GND Ground Common ground 17 ANT RF 50 Ω Antenna input/output 18 GND Ground Common ground 19 GND Ground Common ground 20 VCC_VCO Power VCO power supply 21 PHD_OFF D Input Open PLL 22 TX_DATA D Input Transmit data input 23 GND Ground Common ground 24 SYNT_ON D Input Synthesizer (PLL) powerup 25 SI_CLK D Input Serial interface clock 26 SI_CMS D Input Serial interface mode select 27 SI_CDI D Input Serial interface data input 28 GND Ground Common ground 29 SI_CDO D Output Serial interface data output 30 POR D Output Power-on reset 31 LPO_CLK D Output 3.2 kHz low-power clock 32 PX_ON D Input Packet on 33 SYS_CLK_REQ D Input System clock request 34 SYS_CLK D Output Common ground 1 MHz clock Transmit power on Not connected System clock *A = analog; D = digital. Lucent Technologies Inc. 5 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Symbol Min Typ Max Unit Ambient Operating Temperature TA –40 25 100 °C Storage Temperature Tstg –65 — 150 °C — — — 230 °C Positive Supply Voltage VCC 0 — 4.5 V Power Dissipation PD — — 350 mW Vp-p 0 — VCC V — –0.3 — VCC + 0.3 V Lead Temperature (soldering, 10 s) ac peak-to-peak Input Voltage Digital Voltages Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: Parameter Method Rating Unit ESD Threshold Voltage HBM 2000 V ESD Threshold Voltage (corner pins) CDM 500 V 6 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Operating Range Performance is not guaranteed over the full range of all conditions possible within this table. However, it lists the ranges of external conditions in which the W7020 provides general functionality, which may be useful in specific applications, without risk of permanent damage. The conditions for guaranteed performance are described in the Electrical Characteristics section. Parameter Min Typ Max Unit Operating Temperature –35 25 85 °C External Reference Clock Input Level 0.4 — 2.0 Vp-p Nominal Operating Voltage 2.7 — 3.6 V Min Typ Max Unit 2.402 — 2.495 GHz 12.999740 13.000000 13.000260 MHz External Reference Clock Level* 0.4 — 1.0 Vp-p Supply Voltage 2.7 2.8 3.0 V Antenna Load (VSWR ≤ 2.0) 25 50 100 Ω Operating Temperature –30 25 75 ºC Operating Conditions Parameter Frequency Range Reference Clock Frequency * Optional overdrive on XO_N pin, ac-coupled. Digital Inputs/Outputs Parameter Min Typ Max Unit Logical Input Low (0) –0.3 0 0.2 * VCC V Logical Input High (1) 0.8 * VCC VCC VCC + 0.3 V Input Leakage Current — — 5 µA Input Capacitance — — 15 pF Crystal Input Capacitance (XO_IN) — 2.5 — pF Rise/Fall Time of Digital Inputs — — 20 ns Logical Output Low (0) — 0 0.4 V VCC – 0.4 VCC — V — 3.2 — kHz — — ±250 ppm Logical Output High (1) LPO Clock Frequency, Trimmed † LPO Clock Frequency Tolerance † Adjusted to 3.2 kHz by the baseband circuit. Lucent Technologies Inc. 7 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Electrical Characteristics Specifications are guaranteed for VCC = 2.8 Vdc, TA = 25 °C ± 10 °C. Supply Currents Parameter Supply Current*: Standby Synthesizer On Receive Mode Transmit Mode Min Typ Max Unit — — — — 50 22 40 33 100 — 52 44 µA mA mA mA *Currents reflect continuous operation, not TDD mode of operation. Power Consumption Mode TX/RX Data Rate Typ Max Unit (kbits/s) TX — 33 44 mA RX — 40 52 mA SYNTH ON — 22 — mA Standby — 50 100 µA DM1 14.4/14.4 18 — mA DM5 286.7/286.7 32 — mA DH1 172.8/172.8 18 — mA DH5 723.2/57.6 32 — mA HV1 64/64 30 — mA HV3 64/64 10 — mA Page Scan — 511 — µA Park Mode (1 s interval) — 108 — µA 8 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Electrical Characteristics (continued) Specifications are guaranteed for VCC = 2.8 Vdc ± 100 mV, TA = 25 °C ± 10 °C. Transmit Performance Transmitter power and spectrum characteristics are measured in 100 kHz RBW, unless otherwise specified. Parameter Min Typ Max Unit 2402 — 2495 MHz Frequency Accuracy* — — ±75 kHz Frequency Drift: 1-slot Packet 3- and 5-slot Packets — — 5 15 ±25 ±40 kHz kHz ±140 ±115 ±150 — ±175 — KHz kHz Transmit Power –2 0 4 dBm 20 dB Signal BW (PN9 PRBS data, in 10 kHz RBW) — — 1 MHz GFSK Modulation Spectrum: ±>550 kHz ±1.550 MHz—2.450 MHz (alternate channel) ±>2.550 MHz (second alternate channel) ±13 MHz — — — — –21 –57 –63 –70 –20 –30 –50 –50 dBc dBm dBm dBm Spurious Emissions: 30 MHz—1 GHz (other than ranges listed below) 810 MHz—960 MHz 1 GHz—12.75 GHz (other than ranges listed below) 1.8 GHz—1.99 GHz 5.1 GHz—5.3 GHz — — — — — <–70 <–110 <–65 <–110 <–70 –36 –100 –30 –100 –47 dBm dBm dBm dBm dBm Frequency Band Frequency Deviation: 00001111 Pattern 01010101 Pattern * This parameter is determined by the accuracy of the reference crystal or external reference clock, specified as <±20 ppm. Lucent Technologies Inc. 9 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Electrical Characteristics (continued) Specifications are guaranteed for VCC = 2.8 Vdc ± 100 mV, TA = 25 °C ± 10 °C. Receiver Performance Receiver data BER ≤ 0.1%. Parameter Min Typ Max Unit — –78 –72 dBm Maximum Signal Sensitivity (BER = 1E-3) –20 –2 — dBm Spurious Free Input Dynamic Range Input 1 dB Compression 50 70 — dB –27 –22 — dBm Input IP3 — –14 — dBm C/I Co-channel — 8 11 dB C/I, ±1 MHz Interference — –3 0 dB C/I, ±2 MHz Interference — –32 –30 dB C/I, ≥3 MHz Interference — –42 –40 dB C/I Image Interference (–6 MHz) — –17 –9 dB C/I Adjacent 1 MHz to Image — –30 –20 dB IM 2 Tone Blocking –39 –34 — dBm Out-of-Band Blocking (CW interferer): 30 MHz—2000 MHz (other than ranges listed below) 824 MHz—960 MHz 1710 MHz—1910 MHz 2000 MHz—2400 MHz 2500 MHz—3000 MHz 3000 MHz—12.75 GHz –10 4 4 –27 –27 –10 10 10 10 –12 –9 –4 — — — — — — dBm dBm dBm dBm dBm dBm Conducted Spurious: @100 kHz RBW: 30 MHz—1 GHz (other than ranges listed below) 810 MHz —960 MHz 2.402 GHz—2.495 GHz 1 GHz—12.75 GHz (other than ranges listed below) 1805 MHz —1990 MHz — — — — — <–60 <–90 –60 <–60 <–90 –57 –100 –47 –47 –100 dBm dBm dBm dBm dBm RSSI Sensitivity — –70 –60 dBm Maximum RSSI Response Level –40 –30 — dBm RSSI Absolute Accuracy –4 — 4 dB Min — Typ 160 Max — Unit µs — — — –107 –122 –126 –88 –114 –124 dBc/Hz dBc/Hz dBc/Hz Sensitivity (BER = 1E-3) Synthesizer Performance Parameter Channel Switching Time SSB Phase Noise: ∆f = 500 kHz ∆f = 2 MHz ∆f = 3 MHz 10 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Interface Signal Description Table 2. Data Interface: CMOS I/O Up to 1 Mbit/s Pin No. Pin Name Function 4 RX_DATA Connects to baseband and is synchronized to the SYS_CLK signal. 22 TX_DATA TX data from baseband must be synchronized with TX_CLK signal. Table 3. Digital Control Inputs: Strobe Signals to Control Various W7020 Features Pin No. Pin Name Function 9 POR_EXT 5 RX_ON Logic high enables receiving of RX_DATA; low disables RX_DATA. 3 TX_ON Logic high enables transmission of TX_DATA; low disables TX_DATA. 33 SYS_CLK_REQ 32 PX_ON 24 SYNT_ON Logic high enables the VCO/PLL. 21 PHD_OFF Logic high opens the VCO/PLL control loop. Reset will occur on the positive edge of an external power-on-reset signal. Logic high starts up SYS_CLK and TX_CLK outputs (if control register bit 2 set). Logic high during synchronization at first data packet from master. Table 4. Digital Control Outputs: Output Clocking and Reset Control for the Baseband Pin No. Pin Name Function 2 TX_CLK 34 SYS_CLK 13 MHz reference clock output, available if POR_EXT & SYS_CLK_REQ are high. 31 LPO_CLK 3.2 kHz adjustable low-power oscillator clock, available after VCC applied. 30 POR 1 MHz transmit clock output, available if POR_EXT & SYS_CLK_REQ are high. Delayed reset signal (<30 ms) (refer to Power-On Reset and XO Start-Up section). Table 5. Analog Inputs: Connect XTAL Off-Module or External Oscillator Signal (0.4 Vp-p to 1.0 Vp-p) Pin No. Pin Name Function 7 XO_P Connect XTAL. Leave unconnected when using external clock. 8 XO_N Connect XTAL or external signal, ac-coupled. Table 6. Serial Interface: Based on the Boundary-Scan Architecture, IEEE* 1149.1 Pin No. Pin Name Function 27 SI_CDI Control data input; transports serial data to the W7020. 26 SI_CMS Control mode select; determine transitions from one state to another with the CLK positive edge. 25 SI_CLK Control clock; control timing of the serial interface. 29 SI_CDO Control data out; transports serial data from the W7020 to baseband. * IEEE is a registered trademark of the Institute of Electrical and Electronic Engineers, Inc. Lucent Technologies Inc. 11 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Serial Interface The serial interface implementation is based on the boundary-scan architecture, IEEE Std. 1149.1. Figure 4 shows a block diagram of the serial interface. It is identical to the boundary-scan architecture if the extra control signals from the controller access port (CAP) block are removed. The interconnection between the serial interface and the external controller (baseband chip) consists of four 1-bit signals: control data input (CDI), control mode select (CMS), control clock (CLK), and control data output (CDO). The CDI signal transports serial data to the W7020, while the CDO signal transports serial data out of the W7020. DATA BUS (D[7:0]) CDI UPDATE_DR DATA REGISTER SHIFT_DR BYPASS REGISTER CMS BUS ENABLE CONTROL CONTROL CAP CLK CLOCK_DR DECODE ADDRESS ENABLE UPDATE_IR SHIFT_IR CLOCK_IR INSTRUCTION REGISTER STATUS SELECT CDO Figure 4. Slave Serial Interface (IEEE Std. 1149.1) The CAP is a controller-state machine and is controlled by the CLK and CMS signals. The CAP, which consists of 16 states, determines whether an instruction register scan or a data register scan will be performed. In these two register scan cycles, data are exchanged between the interconnected units. The interface architecture contains three types of registers: instruction register (IR), bypass register (BYP), and data register (DR). The structure of the instruction register is shown in Figure 5. The register has a serial data input (CDI) and serial data output (CDO), as well as parallel status inputs and outputs. During a scan period, serial data are shifted through the register. Shadow latches are needed to hold the parallel output at a steady value when shifting occurs. The width of the instruction register is 6 bits. 12 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Serial Interface (continued) STATUS CDI CLOCKIR SHIFTIR UPDATEIR INSTRUCTION SHIFT REGISTER CDO SHADOW LATCHES INSTRUCTION REGISTER OUTPUT Figure 5. Instruction Register The data register has a structure similar to the IR. The data width is 8 bits. The bypass register consists of a single register bit and forms a scan path between CDI and CDO. CAP State Diagram The CAP state diagram is shown in Figure 6. Transitions from one state to another depend on the CMS input and occur at the rising edge of the CLK. The CMS and CDI inputs should change value on the falling edge of CLK. The CDO output changes on the negative edge of CLK. An instruction register scan (IR-scan) period starts with a status information download (capture-IR). The status inputs to the instruction register are user-defined observability inputs. However, the two least significant status information bits are fixed to 01 during the capture-IR according to the standard. Afterward, the data can be shifted out (shift-IR) at the same time serial data is shifted in, or directly updated to the parallel output (exit1-IR, update-IR). It also is possible for the IR-scan period to be paused (pause-IR) before a new data shift. A data register scan period is identical, but there are no restrictions on the data during capture-DR. The control-logic-reset state can always be reached from any other state by allowing the CMS input to be high for five clock cycles. Lucent Technologies Inc. 13 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Serial Interface (continued) CAP State Diagram (continued) 1 CONTROLLER_LOGIC RESET 0 0 RUN_TEST/IDLE SELECT_DR SCAN 1 SELECT_IR SCAN 1 0 1 0 1 CAPTURE_DR CAPTURE_IR 0 0 0 SHIFT_DR EXIT1_DR 1 1 EXIT1_IR 0 PAUSE_DR 1 0 0 PAUSE_IR 1 EXIT2_DR UPDATE_DR 0 0 1 0 EXIT2_IR 1 1 0 SHIFT_IR 1 0 1 1 1 UPDATE_IR 0 Figure 6. CAP State Diagram 14 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Serial Interface (continued) Reserved Instructions Two reserved instructions are implemented. The first is the bypass instruction. Its bit code is defined to be all ones. This instruction allows serial data to be transferred through the circuit from CDI to CDO with the bypass register connected between, one clock signal delayed. The second is the normal read/write instruction. This instruction selects a specific register to write to or read from. The bit code of this instruction is defined to be 01XXXX, where XXXX is the register address (see Table 7). W7020 Registers W7020 registers are accessed by the instruction register output. Every register has a unique address. Table 7 lists the various registers, their read or write status, and their addresses. Table 7. W7020 Registers Register Name # of Bits R/W Address VCO/DAFC Control Channel RSSI XO-Trim ID LPO-hi 8 8 5 6 8 1 W W R W R W 010001 = 17 010010 = 18 LPO-lo 8 W 010101 = 21 Control 7 W 010110 = 22 CHP and TX Control 8 W 010111 = 23 Current Control 3 W 011000 = 24 Enable 8 W 011001 = 25 010011 = 19 010100 = 20 The W7020 registers are explained in Table 8 through Table 18. Lucent Technologies Inc. 15 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Serial Interface (continued) W7020 Registers (continued) Table 8. VCO/DAFC/Delay Control (Address = 17)* Bit No. Bit Name Reset Value Baseband Standard Setting Function 7 DelP 0 1 Delays PHD_OFF negative edge by 6 µs—7 µs if DelP = 1. 6 DelS 0 1 Delays SYNT_ON negative edge by 6 µs—7 µs if DelS = 1. 5 Dtrim 0 1 Enables DAFC diode voltage trim: 1 = enable. 0 = default diode voltage. 4 DAFC1 0 1 Sets the diode voltage in 50 mV steps if Dtrim = 1. 3 DAFC0 0 1 2 — — 0 — 1 VCO1 0 1 Sets the VCO core current. 0 VCO0 0 1 * — = not applicable. Table 9. Channel Register (Address = 18) Bit No. Bit Name Reset Value 7 RX/TX 0 Receive or transmit channel: 1 = RX; 0 = TX. 6 C6 0 Channel value (0 dec—127 dec). 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 1 0 C0 0 16 Function Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Serial Interface (continued) W7020 Registers (continued) Table 10. RSSI Register (Address = 18)* Bit No. Bit Name Reset Value Function 7 — — — 6 — — — 5 — — — 4 RS4 U 3 RS3 U 2 RS2 U 1 RS1 U 0 RS0 U Received signal strength indicator. Lower input power gives lower RSSI value. * — = not applicable; U = undefined. Table 11. XO-Trim Register (Address = 19)* Bit No. Bit Name Reset Value Function 7 — — — 6 — — — 5 XO5 0 4 XO4 0 Trim value for the internal capacitor load of the crystal (0 —> max fXO; 63 —> min fXO). 3 XO3 0 2 XO2 0 1 XO1 0 0 XO0 0 * — = not applicable. Lucent Technologies Inc. 17 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Serial Interface (continued) W7020 Registers (continued) Table 12. ID Register (Address = 19)* Bit No. Bit Name Reset Value Function 7 C13 0 — 6 C12 0 5 C11 0 4 C10 1 3 V13 U 2 V12 U 1 V11 U 0 V10 U Version number (P4B = 0111, P5B = 1000). * U = undefined. Table 13. LPO-Hi Register (Address = 20)* Bit No. Bit Name Reset Value Function 7 — — — 6 — — — 5 — — — 4 — — — 3 — — — 2 — — — 1 — — — 0 L8 0 Most significant bit of the LPO adjust value: L8—L0 = 00 . . . 0 gives max fLPO. L8—L0 = 11 . . . 1 —> min fLPO. * — = not applicable. Table 14. LPO-Lo Register (Address = 21) Bit No. Bit Name Reset Value 7 L7 0 6 L6 0 5 L5 0 4 L4 0 3 L3 0 2 L2 0 1 L1 0 0 L0 0 18 Function Eight least-significant bits of the LPO adjust value: L8—L0 = 000 . . . 0 gives maximum fLPO. L8—L0 = 111 . . . 1 gives minimum fLPO. Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Serial Interface (continued) W7020 Registers (continued) Table 15. Control Register (Address = 22)* Bit No. Bit Name Reset Value Function 7 — — — 6 Ltr3 1 5 Ltr2 0 4 Ltr1 0 3 Ltr0 0 2 XOctr 0 XOctr crystal oscillator start-up control. After power-on reset, a 0 to 1 transition enables the XO to be controlled by SYS_CLK_REQ. 1 — — — 0 — — — LPO course trimming. Lower value gives higher fLPO. * — = not applicable. Table 16. CHP and TX Control Register (Address = 23) Bit No. Bit Name Reset Value Baseband Standard Setting 7 ChpTst 0 0 Must be programmed to 0. 6 TX2 0 1 5 TX1 0 0 Sets the frequency deviation amplitude 000 —> maximum deviation. 111 —> minimum deviation. 4 TX0 0 0 3 EnLo1 0 0 Must be programmed to 0. 2 CHP2 0 0 Must be programmed to 0. 1 CHP1 0 0 0 CHP0 0 0 Lucent Technologies Inc. Function 19 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Serial Interface (continued) W7020 Registers (continued) Table 17. Current Control Register (Address = 24)* Bit No. Bit Name Reset Value Function 7 RINT2 0 6 RINT1 0 5 RINT0 0 4 — — — 3 — — — 2 — — — 1 — — — 0 — — — Default reset value is used for normal operation. Does not require programming by baseband. * — = not applicable. Table 18. Enable Register (Address = 25)* Bit No. Bit Name Reset Value Baseband Standard Setting Function 7 PXen 0 1 Must be programmed to 1. 6 — 0 0 Must be programmed to 0. 5 — 0 1 Must be programmed to 1. 4 — 0 1 Must be programmed to 1. 3 — 0 1 Must be programmed to 1. 2 — 0 1 Must be programmed to 1. 1 DEn 0 1 Must be programmed to 1. 0 TXinv 0 1 Must be programmed to 1. *— = not applicable. 20 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Serial Interface (continued) Channel Register Programming Example The following example demonstrates how to program the W7020 for transmit channel 50. The first step is to point to the channel register by doing an IR-scan. The CMS signal is used to put the CAP (see Figure 7) in the SHIFT_IR state. After the CAP is in the SHIFT_IR state, the channel address value 010010 (18) should be shifted into the CDI input (LSB first). When the CAP returns to the RUN_TEST/IDLE state, the instruction register is updated. The new channel value is entered by performing a DR-scan. The CMS signal is used to put the CAP in the SHIFT_DR state. The channel value of 50 is shifted in the CDI = 00110010 (50 decimal) LSB first. When the CAP is returned to RUN_TEST/IDLE, the channel register is updated. If no other W7020 register has been addressed when a new channel value is required, only a new DR-scan needs to be done, because the IR already points to the channel register. When data is shifted in, previous data contained in the selected register will simultaneously be shifted out on the CDO. In the case of the channel register, the value of the RSSI will be shifted out on the CDO. An example of programming the channel register is shown below. All input signals (CDI, CMS) to the serial interface should change on the negative edge of the serial interface clock (CLK) to eliminate setup and hold violations. The serial interface samples the CDI and CMS signals on the positive edge of CCK. The output signal (CDO) changes on the negative edge. In the final application, CDO is sampled on the positive CLK edge. CMS 1 1 1 1 1 0 1 1 0 0 0 CAP STATE SHIFT_IR CDI X X X X CDO — — — — X X X X — — HIGH IMPEDANCE 0 0 0 1 SHIFT_IR AND EXIT X X DON’T CARE — 0 0 1 0 0 1 1 1 0 0 0 UPDATE IR, SELECT _DR 0 X X X 1 0 0 1 1 0 0 0 0 0 0 1 SHIFT_DR AND EXIT X 0 1 — — — — ? ? CHANNEL REGISTER 18 — — — 0 0 0 1 1 0 1 0 0 RUN_TEST IDLE 0 X X X ? — — — CHANNEL VALUE 50 ? ? ? ? ? RSSI VALUE Figure 7. Serial Interface Channel Register Programming Example Timing Information Lucent Technologies Inc. 21 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Transmit and Receiver Application Application Circuit Diagram BASEBAND INTERFACE LINES DATA INTERFACE RX_DATA POR_EXT XO_N XO_P GND RX_ON RX_DATA TX_ON TX_CLK GND 4.7 pF GND 6.8 µF DIGITAL CONTROL INPUTS VCC 2.8 V 11 10 9 8 7 6 5 4 3 2 1 POR_EXT RX_ON TX_ON NC 12 GND 13 XO 34 SYS_CLK 33 SYS_CLK_REQ LNA RX BALUN ∑ PX_ON BPF DISC SWITCH GND 14 GND 15 TX AMP GND DIGITAL CONTROL OUTPUTS Φ TX BALUN LOOP FILTER VCO TANK 32 PX_ON 31 LPO_CLK 30 POR LPO_CLK (3.2 kHz) 29 SI_CDO POR (RESET OUTPUT) LO PLL 16 LPF ANT 17 SYS_CLK_REQ ANTENNA FILTER TX_CLK (1 MHz) SYS_CLK (13 MHz) 19 20 21 22 23 24 25 26 27 28 SI_CDO GND GND VCC_VCO PHD_OFF TX_DATA GND SYNT_ON SI_CLK SI_CMS SI_CDI GND SERIAL INTERFACE 18 SI_CDI SI_CMS 2.8 V SI_CLK 6.8 µF 4.7 pF DIGITAL CONTROL INPUTS SYNT_ON PHD_OFF DATA INTERFACE TX_DATA Figure 8. Application Circuit Diagram 22 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Transmit and Receiver Application (continued) Timing Information Figure 9 shows the test conditions required to produce a transmit and receive slot with the W7020. (In addition, pins POR_EXT and SYS_CLK_REQ must be held HIGH.) The transmit slot begins with taking SYNT_ON HIGH. This turns on the synthesizer and voltage-controlled oscillator (VCO). The synthesizer is programmed to the appropriate channel (see the Channel Register Programming Example section). A delay (tTO) is required for the phase-lock loop (PLL) to settle before TX_ON is pulled HIGH. Modulation is achieved by first opening the PLL by taking PHD_OFF high. The transmit data from the baseband device is input into the W7020 TX_DATA pin. The W7020 Gaussian filter shapes the data, and then directly modulates the VCO. After the transmit slot is completed, the TX_ON, PHD_OFF, and SYNT_ON inputs are returned to a LOW for minimum current consumption. TX SLOT RX SLOT tTD TX_DATA tRD RX_DATA PHD_OFF TX_ON RX_ON PX_ON SYNT_ON SI_CDI CHANNEL NUMBER tTO CHANNEL NUMBER tPHD tTX tRO ts tRX ts Figure 9. Timing Diagram Lucent Technologies Inc. 23 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Transmit and Receiver Information (continued) Timing Information (continued) Table 19. Timing Table Symbol Parameter Min Typ Max Unit TTX Data Sending Period, 1-slot Packet — — 366 µs TTX Data Sending Period, 3-slot Packet — — 1622 µs TTX Data Sending Period, 5-slot Packet — — 2870 µs TRX Data Receiving Period, 1-slot Packet — — 366 µs TRX Data Receiving Period, 3-slot Packet — — 1622 µs TRX Data Receiving Period, 5-slot Packet — — 2870 µs tPHD Phase Detector Off Delay after tTO — 104 — µs tRD Delay Before Receiving Data — 213 — µs tRO Receiver On Delay — 208 — µs tS Slot Time, 1-slot Packet — 625 — µs tS Slot Time, 3-slot Packet — 1875 — µs tS Slot Time, 5-slot Packet — 3125 — µs tTD Delay Before Transmitting Data — 214 — µs tTO Transmitter On Delay — 110 — µs Power-On Reset and XO Start-Up The power-on reset is a block that creates a reset signal to the digital circuitry. The transition from low to high on the POR signal occurs when the LPO and the crystal oscillator, XO, are running and the POR_EXT signal is high. (See Table 20.) Both POR_EXT and POR are active-low signals. Table 20. Reset Truth Table POR_EXT (pin 9) XO LPO POR (pin 30) 0 X X 0 1 X No osc. 0 1 No osc. Osc. 0 1 Osc. Osc. 1 A power supply drop below a certain voltage level that is caused by, for example, a glitch, will automatically cause a reset. A 13 MHz crystal should be connected to the XO_N and XO_P pins, as shown in Figure 3. An internal (0 pF—8 pF) capacitive load of the crystal can be adjusted with the XO-trim register so that the crystal runs at 13 MHz within ±20 ppm. Alternatively, an external 13 MHz sinus signal (200 mV—500 mV peak) can be used instead of the external crystal. The clock should be ac-coupled into the XO_N pin. Figure 10 and Figure 11 show typical powerup initialization and wake-up sequences. 24 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Transmit and Receiver Application (continued) Timing Information (continued) Powerup Initialization VCC LPO OUT (3.2 KHz) SYS_CLK AND TX_CLK OUTPUTS REMAIN ACTIVE IF SYS_CLK_REQ IS HIGH HERE, AFTER CONTROL:XOCTR BIT=1 POR_EXT IN SYS_CLK OUT (13 MHz) TX_CLK OUT (1 MHZ) POR OUT SERIAL BUS INITIALIZATION (XO-TRIM REGISTER; CONTROL REGISTER:XOCTR BIT=1 AND LPO COARSE TRIM BITS AS REQ’D; CHP CONTROL REGISTER=8(DEC); ENABLE REGISTER=191(DEC) SI_CDI (AS REQUIRED) SI_CMS (AS REQUIRED) SI_CLK (AS REQUIRED) SYS_CLK_REQ IN (HIGH) SYS_CLK_REQ IN (LOW) TX_ON IN (LOW) RX_ON IN (LOW) SYNT_ON IN (LOW) XO_N IN (LOW) P PHD_OFF IN (LOW) P 2 ms 3.5 ms 350 ns 20 µs to 200 µs Figure 10. Powerup Initialization Sequence Lucent Technologies Inc. 25 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Transmit and Receiver Application (continued) Timing Information (continued) Wake-Up for Connection VCC (>2.7 VDC) LPO OUT (3.2 kHz) POR_EXT IN (HIGH) POR OUT (HIGH) SYS_CLK_REQ IN SERIAL BUS INITIALIZATION (CHANNEL REGISTER) SI_CDI (AS REQUIRED) SI_CMS (AS REQUIRED) SI_CLK (AS REQUIRED) SYS_CLK OUT (13 MHz) TX_CLK OUT (1 MHz) SYNT_ON IN TX_ON IN TX DATA PHD_OFF IN X_ON R IN RX DATA PX_ON IN 130 µs 18 µs 68 µs—2870 µs (PACKET-DEPENDENT) 80 µs 200 µs 68 µs—2870 µs (PACKET-DEPENDENT) 45 µs—345 µs Figure 11. Typical Wake-up-for-Connection Sequence 26 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Transmit and Receiver Information (continued) RSSI The RSSI value is a measure of the RF input power that is sampled on the low-high transition of the PX_ON signal. The RSSI value is sent out on the SI-CDO line when the channel register is accessed (same address). Select, for example, receive channel 50 (channel register = 10110010) and input a GFSK modulated carrier (–60 dBm). Toggle PX_ON low-high-low and read out the RSSI value by accessing the channel register once again. The RSSI value will be in the 6 to 14 range. Input a higher power (–40 dBm). Toggle PX_ON and read out the RSSI value again. The RSSI value will be in the 20 to 28 range. Lucent Technologies Inc. 27 W7020 Bluetooth Radio Module Preliminary Data Sheet September 2000 Characteristic Curves Figure 12. VCO Settling Time and Transmit Slot (16 Alternating 1s and 0s) 28 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Characteristic Curves (continued) REF LVL 0 dBm Marker 1 (T1) –0.38 dBm 2.44101002 GHz 1 RBW VBW SWT 100 kHz 300 kHz 10 ms RF ATT UNIT 10 dB dBm 0 1 –10 1 –20 –30 [T1] –0.38 dBm 2.44101002 GHz CH PWR 5.86 dBm ACP UP –19.97 dBm ACP LOW –19.81 dBm ALT1 UP –49.92 dBm ALT1 LOW –48.13 dBm ALT2 UP –55.66 dBm ALT2 LOW –54.00 dBm –21.47 dB 1 [T1] 550.00000000 kHz –40 –50 BTMODMASK –60 –70 –80 –90 –100 CENTER 2.441 GHz 1 MHz/ SPAN 10 MHz Figure 13. GFSK Transmit Modulation Mask Lucent Technologies Inc. 29 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Characteristic Curves (continued) REF LVL 0 dBm 0 Marker 1 (T1) –1.81 dBm 2.44100501 GHz 1 RBW VBW SWT 10 kHz RF ATT 30 kHz 1s UNIT 1 [T1] 10 dB dBm –1.81 dBm 2.44100501 GHz –10 –20.75 dB 1 [T1] –340.68136273 kHz 1 –20 2 –20.72 dB 2 [T1] 380.60120241 kHz –30 –40 –50 –60 –70 –80 –90 –100 CENTER 2.441 GHz 500 kHz/ SPAN 5 MHz Figure 14. Transmit Modulation Spectrum (–20 dB Bandwidth) Note: The displayed 20 dB bandwidth = 721 kHz. 30 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Characteristic Curves (continued) BLOCKER POWER (dBm) 0.3 5 0.25 0 0.2 –5 0.15 –10 0.1 –15 0.05 –20 0 BER (%) BLOCKER LEVEL (dBm) BER 10 –25 –30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 BLOCKER FREQUENCY (GHz) Figure 15. Receiver Out-of-Band Blocking Note: Bit error rate (BER) less than 0.1% indicates limitations of blocker-signal power level. Lucent Technologies Inc. 31 W7020 Bluetooth Radio Module Preliminary Data Sheet September 2000 Characteristic Curves (continued) Figure 16. VCO/PLL Synthesizer 32 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Characteristic Curves (continued) Figure 17. VCO/PLL Synthesizer SSB Phase Noise Lucent Technologies Inc. 33 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Soldering Profile To prevent damage to the components from crack, etc., the following soldering steps should be followed: 1. Carefully perform preheating so that the temperature difference ∆T between the solder and the component surface is in the range shown in Figure 18. 2. When the components are immersed in solvent after mounting, maintain the temperature difference within 100 ºC. 3. Use rosin type flux or weakly active flux with chlorine content of 0.2% weight or less. 4. Use eutectic crystal solder. Soldering Method Temperature Reflow ∆T ≤ 130 ºC 220 °C ~ 230 °C WITHIN 10 s 200 °C ∆T TEMPERATURE (°C) ~230 °C 220 °C PREHEATING 60 s MIN. WITHIN 20 s WITHIN 120 s Figure 18. Solder Timing Diagram 34 Lucent Technologies Inc. Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Outline Diagram 34-pin MCLGA Dimensions are in millimeters. 0794 Note: Positions and dimensions of holes in the shield may vary. Lucent Technologies Inc. 35 Preliminary Data Sheet September 2000 W7020 Bluetooth Radio Module Manufacturing Information This device may be assembled in any of the following locations: J, S, and TW. Ordering Information The following devices are available: + Bluetooth Radio Module + Bluetooth Radio Module, Tape and Reel + Bluetooth Radio Module, Bakeable Tray + Bluetooth Radio Module, Dry Pack Tape and Reel + W7020 Evaluation Board, including Solder-Attached W7020 Bluetooth Radio Module (LUCW7020) + W7020 Bluetooth Radio Module Evaluation Kit, including EVB7020, USB Transceiver Interface Board, and PC Control Software Contact your Lucent Technologies Microelectronics Group Account Manager for comcode information and minimum order requirements. For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: [email protected] N.AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P.R. China Tel. (86) 21 6440 0468, ext. 325, FAX (81) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 2000 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. September 2000 DS00-208WBLU (replaces DS99-254WBLU) Printed On Recycled Paper