YMU762 MA-3 Mobile Audio 3 Outline MA-3 is a synthesizer LSI for mobile phones that realize advanced game sounds. This LSI has a built-in speaker amplifier, and thus, is an ideal device for outputting sounds that are used by mobile phones in addition to game sounds and ringing melodies that are replayed by a synthesizer. The synthesizer section adopts “stereophonic hybrid synthesizer system” that are given advantages of both FM synthesizers and Wave Table synthesizers to allow simultaneous generation of up to thirty two FM voices and eight Wave Table voices. Since FM synthesizer is able to present countless voices by specifying parameters with only several tens of bytes, memory capacity and communication band can be saved, and thus, the device exhibits the features in operating environment of mobile phones such as allowing distribution of arbitrary melodies with voices. On the other hand, Wave Table synthesizer can pronounce the voice built in ROM and arbitrary ADPCM/PCM voices from sequencer by the download of the melody with voices etc.. MA-3 has a built-in hardware sequencer that helps to realize complex play without heavily loading the host CPU. The device also has a built-in circuit for controlling vibrators and LEDs synchronizing with play of music. Features MA-3 has features as described below. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Simultaneous generation of up to 40 tones: FM + Wave Table stereophonic hybrid synthesizer. Polyphonic synthesizer specification. Has built-in default voices for FM and Wave Table synthesizers in the ROM, and the voices can be downloaded to RAM. Fundamental waveforms for FM and algorithm are improved compared with YMU759 (MA-2), and voice parameters of detune etc. are added. Stream replay with ADPCM / PCM (shared use of Wave Table section). Software interrupt mechanism for external synchronization. Equipped with 8 bit parallel I/F for control from CPU. Equipped with speaker amplifier and equalizer circuit. Equipped with vibration control circuit, and LED lighting control circuit. Has built-in PLL to support inputting of master clock up to 20 MHz. Contains a 16-bit stereophonic D/A converter. Equipped with a stereophonic output terminal for headphone. Supports power down mode. Digital power supply: 2.7V to 3.3V (Typ 3.0V) Analog power supply: 2.7V to 4.5V (Typ 3.6V) 32-pin QFN plastic package The contents of this booklet are target specifications and they are subject to change without a prior notice. Please check the finalized specifications before actually using this LSI. YAMAHA CORPORATION YMU762 CATALOG CATALOG No.:LSI-4MU762A3 2002.9 YMU762 D2 D3 D4 D5 D6 D7 MTR SPOUT2 SPOUT1 Pin configuration 25 24 23 22 21 20 19 18 17 28 14 EQ3 /CS 29 13 EQ2 A0 30 12 EQ1 /RD 31 11 HPO UT-R IOVDD 32 10 HPO UT-L/M ONO 1 2 3 4 5 6 7 8 9 VREF /W R VSS SPV DD VDD 15 PLLC 27 N.C D0 /RST SPV SS /IRQ 16 LED 26 CLKI D1 <32pin QFN Top View> 2 YMU762 Functions of pins No. Pin name I/O Power supply Function 1 CLKI Ish IOVDD Clock input ( 2 MHz to 20 MHz) 2 LED O IOVDD External LED control (Drive Capability = 4 mA) 3 /IRQ O IOVDD Interrupt output (Drive Capability = 1 mA) 4 /RST Ish IOVDD Hardware reset input 5 N.C ─ ─ 6 PLLC A VDD 7 VDD ─ ─ 8 VSS ─ ─ No Connection (during regular operations) Connection of capacitor for built-in PLL Connect a series connection of 1000 pF capacitor and 3.3 kΩ resistor between this pin and VSS(*). (*)Directly connect VSS used here and VSS of 8th pin. Power supply (Typ +3.0V) Connect 0.1 µF and 4.7 µF capacitors between this pin and VSS. Ground 9 VREF A VDD Analog reference voltage Connect 0.1 µF capacitor between this pin and VSS. 10 HPOUT-L / MONO A VDD Headphone output Lch (Can be used as MONO output) 11 HPOUT-R A VDD Headphone output Rch 12 EQ1 A VDD Equalizer pin 1 13 EQ2 A VDD Equalizer pin 2 14 EQ3 A VDD Equalizer pin 3 15 SPVDD ─ ─ 16 SPVSS ─ ─ 17 SPOUT1 A SPVDD Speaker connection pin 1 18 SPOUT2 A SPVDD Speaker connection pin 2 19 MTR O IOVDD External motor control pin (Drive Capability = 4 mA) 20 D7 I/O IOVDD CPU I/F data bus 7 21 D6 I/O IOVDD CPU I/F data bus 6 (Drive Capability = 1 mA) 22 D5 I/O IOVDD CPU I/F data bus 5 (Drive Capability = 1 mA) 23 D4 I/O IOVDD CPU I/F data bus 4 (Drive Capability = 1 mA) 24 D3 I/O IOVDD CPU I/F data bus 3 (Drive Capability = 1 mA) 25 D2 I/O IOVDD CPU I/F data bus 2 (Drive Capability = 1 mA) 26 D1 I/O IOVDD CPU I/F data bus 1 (Drive Capability = 1 mA) 27 D0 I/O IOVDD CPU I/F data bus 0 (Drive Capability = 1 mA) 28 /WR I IOVDD CPU I/F write enable 29 /CS I IOVDD CPU I/F chip select Speaker amplifier analog power supply (Typ +3.6V) Connect 0.1 µF and 4.7 µF capacitors between this pin and SPVSS. Speaker amplifier analog ground 30 A0 I IOVDD CPU I/F address signal 31 /RD I IOVDD CPU I/F read enable 32 IOVDD ─ ─ A : Analog pin (Drive Capability = 1 mA) Pin power supply (Typ +3.0V) Be sure to apply potential equivalent to 7th pin (directly connect on the board). Ish : Schmitt input 3 4 Vibrator control MTR Instantaneous read path Delayed write path Software Irq TIMER Buffer SEQ FIFO 512byte LED control VSS LED CPU I/F Sequencer /IRQ D0 - D7 /RD /WR Instantaneous write path SRAM 8k-byte PCM /ADPCM Play back FM+Wavetable Synthesizer (Fs=48kHz) Voice ROM Lch Rch Lch Rch Select VREF VREF 16-bit DAC HP VolR SP Vol +－ EQ Vol Mono VREF HP VolL HPOUT-R A0 IOVDD Instantaneous path FIFO 64byte CLKI Register Timing Generator HPOUT-L /MONO /CS VDD Power Down Control PLL PLLC /RST SPOUT2 SPOUT1 EQ3 EQ2 EQ1 YMU762 Block diagram SPVSS SPVDD ↑ Analog power Supply dedicated To speaker amp YMU762 Outline of blocks This section outlines functions of blocks contained in this device and flow of signals. Register Voice ROM Headphone Output FIFO FIFO Sequencer FM +W aveTable Synthesizer SEL CPU interface Instantaneous w rite path DAC EQ am p. D elayed w rite path SR AM Buffer Speaker am p. Instantaneous read path CPU interface CPU interface is an 8-bit parallel type. - ”Instantaneous write path” that enables Write command immediately (equipped with 64byte FIFO), - ”Delayed write path” that enables Write command after elapse of specified time, and - Instantaneous read path are available. Hardware sequencer and FIFO The sequencer is a block that controls time and register access. The structure of sequence data includes “time information data + MA-3 register control data”, for which 512 byte FIFO is provided. The sequence data is written into delayed write path. FM+Wave Table synthesizer This device contains a Polyphonic synthesizer that adopts FM +Wave Table stereophonic hybrid system that generates up to 40 tones. The FM synthesizer has two operation modes; “16-Voice 4 operation mode” and “32-Voice 2 operation mode” which can be changed to each other freely (except during tone generation). Since waveform for FM operation can be set arbitrarily, the device is able to create voices that are more complex than by conventional devices. Wave Table synthesizers is able to generate eight voices simultaneously, and supports 8 bit PCM and 4 bit ADPCM data format. The sampling frequency is 48 kHz. Stream replaying is also available, realizing interchangeability with ADPCM replay capability of MA-2. Voice ROM and SRAM This device stores voice parameters (GM 128 voices + DRUM 40 voices) for FM and waveform data for Wave Table in the ROM. SRAM is used when downloading arbitrary FM voice parameter and waveform data for Wave Table. It is also used as waveform data buffer at stream replay with PCM/ADPCM. DAC Converts digital signal from a synthesizer into analog signal. The data length is 16 bit. IRQ and TIMER This device supports FIFO, two hardware TIMERs, and interrupt output with software interrupt. 5 YMU762 Headphone output This device supports stereophonic analog output for the headphone. Monaural output is available. EQ amplifier The filter response and gain of the amplifier can be changed by adjusting external parts such as resistors and/or capacitors. Speaker amplifier A speaker amplifier of which maximum out is 580 mW at SPVDD=3.6V is built in this device. A control that adjusts the output level of the amplifier is provided in the previous stage of the amplifier. LED and vibrator control block LEDs and vibrator can be controlled synchronizing with a play. Control asynchronous with play is also possible. Clock generating block This devices supports clock input ranging from 2 MHz to 20 MHz. (Stop = 0 Hz is possible at power down.) This block increases the frequency of inputted clock with various frequency by using PLL to create clocks with fixed frequency that are needed in the device. 6 YMU762 Electrical Characteristics Absolute maximum rating Item SPVDD pin, power supply voltage (Speaker amplifier section) VDD pin, power supply voltage IOVDD pin, power supply voltage SPOUT1, SPOUT2 pin, applied voltage Analog input voltage Digital input voltage Permissible loss (*) Storage temperature Symbol Min. Max. Unit SPVDD -0.3 6.0 V VDD IOVDD VINSP VINA VIND Pd TSTG -0.3 -0.3 -0.3 -0.3 -0.3 4.2 4.2 SPVDD+0.3 VDD+0.3 IOVDD+0.3 1197 125 V V V V V mW °C -50 Note: VSS = SPVSS = 0V (*) : Top= 25 °C, and glass epoxy PCB (30mm × 100mm × 1.0mm) is installed. Operation with Top= 25 °C or higher degrees the permissible loss at the rate of 12mW per 1 °C. Recommended operating conditions Item SPVDD operating voltage (Speaker amplifier section) VDD operating voltage IOVDD operating voltage Operating ambient temperature Symbol Min. Typ. Max. Unit SPVDD 2.7 3.6 4.5 V VDD IOVDD TOP 2.7 2.7 -20 3.0 3.0 25 3.3 3.3 85 V V °C Note: VSS = SPVSS = 0V Make VDD and IOVDD into same electric potential (Connect them directly on the circuit board). DC characteristics Item Input voltage “H” level Input voltage “L” level Output voltage “H” level Output voltage “L” level Schmitt width Input leakage current Input capacity Symbol VIH VIL VOH VOL Vsh IL CI Condition Min. 0.2 × IOVDD IOH = (*) IOL = (*) 0.8 × IOVDD 0.4 0.5 -10 /IRQ, D0 ~ D7 are IOH= –1 mA, IOL= +1 mA LED, MTR Max. 0.7 × IOVDD Note: TOP=-20 to 85°C, VDD, IOVDD=3.0±0.3V, Capacitor load=50 pF (*) : Typ. are IOH = –4 mA, IOL= +4 mA 7 10 10 Unit V V V V V µA pF YMU762 AC characteristics /RST, CLKI Item /RST “L” pulse width /RST (indefinite → L) setup time CLKI frequency CLKI rise / fall time CLKI duty factor Symbol Min. TRSTW TRSTS 1 / Tfreq Tr / Tf Th / Tfreq 100 0 0 30 Typ. Max. Unit 20 30 70 µs µs MHz ns % 50 Note: TOP=-20 to 85°C, VDD, IOVDD=3.0±0.3V, Capacitor load=50 pF The input to Clock can be stopped (=0Hz) during reset period and power down state (DP0=1). However, the input level is to be H or L, and input of intermediate level is prohibited. 90% VDD, IOVDD 30% TRSTW /RST VIL= 0.2*IOVDD VIL= 0.2*IOVDD TRSTS The reset width is defined as the time from the moment VDD or IOVDD has risen to 90%. /RST has to be settled at “L” level at the time VDD or IOVDD has risen to 30%. Tr Tf Th VIH= 0.7*IOVDD 0.5*IOVDD VIL= 0.2*IOVDD CLKI Tfreq Measurement point VIH = 0.7*IOVDD VIL = 0.2*IOVDD VOH = 0.8*IOVDD VOL = 0.2*IOVDD 8 YMU762 CPU interface (Write cycle) Item Symbol Min TADS TADH TCSS TCSH TWW TWDS TWDH 50 0 50 0 50 30 0 Address setup time Address hold time Chip select setup time Chip select hold time Write pulse width Data setup time Data hold time Max. Unit ns ns ns ns ns ns ns TOP=-20 to 85°C, VDD,IOVDD=3.0±0.3V, Capacitor load=50 pF (Read cycle) Item Symbol Min TADS TADH TCSS TCSH TRW TACC TRDH 80 0 80 0 80 Address setup time Address hold time Chip select setup time Chip select hold time Read pulse width Read data access time Data hold time Max. Unit 70 30 ns ns ns ns ns ns ns 0 TOP=-20 to 85°C, VDD,IOVDD=3.0±0.3V, Capacitor load=50 pF Write cycle A0 T AD S T AD H T C SS T C SH /CS TWW /W R TWDS D0 -D7 Invalid V alid TWDH Invalid Note : Under the conditions of TCSH ≥ 0ns, TADH, TWDH : Defined with respect to the point where the rise of /WR has reached 0.7*IOVDD. TADS, TWDS : Defined with respect to the point where the rise of /WR has reached 0.2*IOVDD. 9 YMU762 Read cycle A0 T AD S T AD H T C SS T C SH /CS TRW /RD T AC C TRDH D0 -D7 Valid Note : Under the conditions of TCSH ≥ 0ns, TADH, TRDH : Defined with respect to the point where the rise of /RD has reached 0.7*IOVDD. TADS, TCSS : Defined with respect to the point where the rise of /RD has reached 0.2*IOVDD. TACC : Defined with respect to the point where any of /CS , /RD and A0 has changed later. TRDH : Time to the point where D0-D7 pins become high impedance. Power consumption Item Min. Load current of VDD+ IOVDD (at regular operation) At SPVDD side no tone At SPVDD side 8ohm load 400mW output Power down mode (VDD + IOVDD+SPVDD) (*) Note: TOP=-20 to 85°C, VDD, IOVDD=3.0±0.3V, SPVDD=3.6V (*) : Measurement condition : /CS input pin is fixed to VIH=VDD. 10 Typical 25 4 210 1 Max. Unit 10 mA mA mA µA YMU762 Analog characteristics Conditions of TOP=25°C, VDD, IOVDD=3.0V and SPVDD=3.6V apply to all items. SP amplifier Item Min. Gain setting (fixed) Min. load resistance (RL) Max. output voltage amplitude (RL=8Ω) Max. output power (RL=8Ω, THD+N≤1.0%) THD + N (RL=8Ω, f=1 kHz, output = 400mW) Noise at no signal (A-filter: weighting filter) PSRR (f=1 kHz) Amplitude center potential (VSEL2, VSEL1 =0, 0) (VSEL2, VSEL1 =0, 1) (VSEL2, VSEL1 =1, 0) Differential Output Voltage Typical Max. Unit ±2 8 6.0 580 0.025 -90 90 0.6×VDD 0.5×VDD 0.67×VDD 10 50 times Ω Vp-p mW % dBV dB V V V mV Typical Max. Unit 30 dB Vp-p % dBV MΩ kΩ EQ amplifier Item Min. Gain settable range Max. output voltage amplitude THD + N (f=1 kHz) Noise at no signal (A-filter) Input impedance Feedback resistance between EQ2 and EQ3 2.7 0.05 -90 10 20 SP Volume Item Min. Volume setting range Volume step width THD + N (f=1 kHz) Typical -30 Max. Unit 0 0.05 dB dB % Max. Unit 0 dB dB dBV µA Vp-p Ω 1 EQ Volume Item Min. Volume setting range Volume step width Noise at no signal (A-filter) Max. output current Max. output voltage amplitude Output impedance Typical -30 1 -90 120 1.5 300 11 600 YMU762 HP Volume Item Min. Volume setting range Volume step width Noise at no signal (A-filter) Max. output current Max. output volt. amplitude Output impedance Typical -30 Max. Unit 0 1.5 300 600 dB dB dBV µA Vp-p Ω Typical Max. Unit 1 -90 120 VREF Item Min. VREF voltage 0.5×VDD V DAC Item Min. Resolution Full scale output volt. THD+N (f= 1 kHz) Noise at no signal (A-filter) Frequency response (f=50Hz to 20 kHz) Typical Max. Unit 0.5 -80 +0.5 Bit Vp-p % dBV dB 16 1.5 -85 -3.0 (*) (*): Reduction of response in high frequency range caused by aperture effect 12 YMU762 External dimensions of package 13 YMU762 IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE. Note) The specifications of this product are subject to change without notice. Address inquiries to: Agency Semiconductor Sales & Marketing Department ■ Head Office 203, Matsunokijima, Toyooka-mura, Iwata-gun, Shizuoka-ken, 438-0192 Tel. +81-539-62-4918 Fax. +81-539-62-5054 ■ Tokyo Office 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. +81-3-5488-5431 Fax. +81-3-5488-5088 ■ Osaka Office 3-12-12, Minami Senba, Chuo-ku, Osaka City, Osaka, 542-0081 Tel. +81-6-6252-6221 Fax. +81-6-6252-6229 14