ETC 78P7200

78P7200
E3/DS3/STS-1
Line Interface Unit
DATA SHEET
JULY 2005
DESCRIPTION
FEATURES
The 78P7200 is a line interface transceiver IC
intended for STS-1 (51.84 Mbit/s), DS3 (44.736
Mbit/s) and E3 (34.368 Mbit/s) applications. The
receiver has a very wide dynamic range and is
designed to accept either HDB3 or B3ZS-encoded
Alternate-Mark Inversion (AMI) inputs; it provides
CMOS logic level clock, positive data, negative data
and low-level signal detector outputs. An on-chip
equalizer improves the intersymbol interference
tolerance on the receive path. The transmitter
converts CMOS logic level clock, positive data and
negative data input signals into AMI pulses of the
appropriate shape for transmission. A line buildout
(LBO) equalizer may be selected to shape the
outgoing pulses for shorter line lengths. The
78P7200 requires a single 5 volt supply and is
available in a surface mount package.
•
Single chip transmit and receive interface for
STS-1 (51.84 Mbit/s), E3 (34.368 Mbit/s) or DS3
(44.736 Mbit/s) applications
•
On-chip Receive Equalizer
•
Unique clock recovery circuit, requires no
crystals, tuned components or external clock
•
Selectable transmit line buildout (LBO) to
accommodate shorter line lengths
•
Compliant with ANSI T1.102-1993, Bellcore TRNWT-000499 and GR-253-CORE, ITU-T G.703
and G.823_1991
•
Low-level input signal indication
•
Available in a 28 PLCC surface mount package
•
-40°C to +85°C operating range
BLOCK DIAGRAM
LOWSIG
RVcc
CPD
RVcc
RLF2
RLF1
CLF1
RVcc
Low-Level Signal
Detection
RFO
Clock Recovery
RCLK
DVcc
LIN+
Signal
Acquisition
Eq.
INPUT
Data
Detection
LIN-
RPOS
RNEG
DGND
TVcc
LOUT+
OUTPUT
LOUT-
Output
Driver,
Line
Buildout
[email protected]
Page: 1 of 11
LBO
Pulse
Shaper
Pulse
Generator
TCLK
TPOS
TNEG
OPT!
© 2005 Teridian Semiconductor Corporation
Rev 3.0
78P7200
E3/DS3/STS-1
Line Interface Unit
FUNCTIONAL DESCRIPTION
The 78P7200 is a single chip line interface IC
designed to work with either a 51.84 Mbit/s STS-1,
44.736 Mbit/s DS3 or 34.368 Mbit/s E3 signal. The
receiver recovers clock, positive data and negative
data from an Alternate Mark Inversion (AMI) signal.
The input signal should be B3ZS or HDB3 coded.
The transmitter accepts CMOS level logical clock,
positive data and negative data and converts them
to the AMI signal to drive a 75Ω coaxial cable.
Programmable internal Line Buildout (LBO) circuitry
eliminates the need for external LBO networks.
When the option pins are properly selected, the
shape of the transmitted signal through any cable
length of 0 to 450 feet complies with the published
templates of ANSI T1.102, ITU-T G.703, Bellcore
TR-NWT-000499 and GR-253-CORE. The 78P7200
is designed to work with a B3ZS or HDB3 coded
signal. The B3ZS or HDB3 encoding and decoding
functions are normally included in the framer ICs or
can easily be implemented in a PAL.
RECEIVER
The receiver input is normally transformer-coupled to
the AMI signal. The inputs to the IC are internally
referenced to RVCC. Since the input impedance of
the 78P7200 is high, the AMI line must be
terminated in 75Ω. The input signal to the 78P7200
must be limited to a maximum of three consecutive
zeros using a coding scheme such as B3ZS or
HDB3.
The AMI signal first enters a fixed equalizer, which is
designed to overcome the intersymbol interference
caused by long cable lengths and crosstalk. This
fixed equalizer is optimized for DS3 application and
its effect should be compensated by an external filter
circuit similar to Figure 1, for all square shaped
signals such as DS3-high or 34 Mbit/s E3. For all
new designs, the addition of the filter for DS3 and
STS-1 as well as E3 rate allows the circuit to work
with sharp pulses such as DS3-high. The signal is
then input to a variable gain differential amplifier
whose output is maintained at a constant voltage
level regardless of the input voltage level. The gain
of this amplifier is adjusted by detecting the peak of
the signal and comparing it to a fixed reference.
Page: 2 of 11
The output of the variable gain amplifier is compared
to a threshold value, which is a fixed percentage of
the signal peak. In this way, even though the input
signal amplitude may fall below the minimum value
that can be regulated by the variable gain circuit, the
proper detection threshold is maintained.
Outputs of the data comparators are connected to
the clock recovery circuits. The clock recovery
system employs a unique phase locked loop, which
has an auxiliary frequency-sensitive acquisition loop,
which becomes active only when cycle-slipping
occurs between the received signal rate and the
internal oscillator.
This system permits the loop to independently lock
to the frequency and phase of the incoming data
stream without the need for high precision and/or
adjustable oscillator or tuned circuits.
The frequency characteristic for the phase locked
loop is established by external filter components,
RLF1, RLF2 and CLF1. The values of these
components are specified such that the bandwidth of
the phase locked loop is greater than 200 kHz.
The jitter tolerance of the 78P7200 exceeds the
requirements of TR-NWT-000499 for Category II
equipment for DS3 rate and exceeds the
requirements of ITU-T G.823 for E3 rate. The jitter
transfer function is maximally flat so the IC doesn't
add any significant jitter to the system.
Figure 2 shows the recovered clock (RCLK), positive
data (RPOS) and negative data (RNEG) signals
timing. The data is valid on the rising edge of the
clock. The minimum setup and hold times allow easy
interface to framer circuits. These signals are
CMOS-level outputs.
Should the input signal fall below a minimum value,
the LOWSIG pin goes active low. A time delay is
provided before this output is active so that transient
interruptions do not cause false indications. This
signal should be used as one of many indications to
the cable disconnect; the framer device should count
the number of zeros to declare the loss of signal.
The RPOS and RNEG signals generate random
data following a silence period. The framer device
should ignore RPOS and RNEG data if the LOWSIG
pin is active low.
© 2005 Teridian Semiconductor Corporation
Rev 3.0
78P7200
E3/DS3/STS-1
Line Interface Unit
TRANSMITTER
The transmitter accepts CMOS logic level clock
(TCLK), positive data (TPOS) and negative data
(TNEG) signals and generates high current drive
pulses on the LOUT+ and LOUT- pins. When
properly connected to a center tapped transformer,
an AMI pulse is generated which can drive a 75Ω
coaxial cable.
Figure 3 shows the timing for the transmitter logic
signals. The output pulse width is internally set and
is not sensitive to input clock (TCLK) pulse width.
When a recommended transformer is used and
option pins are properly set, the transmitted pulse
shape at the end of a 75Ω terminated cable of 0 to
450 feet will fit the template for DSX3 pulse
published in ANSI T1.102-1993, Bellcore
TR-NWT-000499 documents.
For 51.84 Mbit/s STS-1 application the transmitted
pulse for a short cable meets the requirements of
Bellcore GR-253-CORE. For 34 Mbit/s E3
application, the transmitted pulse for a short cable
meets the requirements of ITU-T G.703 when both
LBO and OPT! pins are set LOW.
Page: 3 of 11
The 78P7200 incorporates a selectable Line
Buildout (LBO) pulse shaper in the transmitter path.
For STS-1 and DS3 applications, the LBO pin
should be set HIGH if the cable is shorter than 225
feet and set LOW for longer cable lengths. For E3
application, LBO pin should be set LOW regardless
of cable length.
The OPT! pin is set HIGH for DS3 and STS-1
operation. The OPT! pin should be set LOW for E3
applications.
The [email protected] pin should be set HIGH for normal
operation. By setting the [email protected] pin to LOW it disables
the transmitter drivers and reduces the power
consumption of the circuit by approximately 125 mW.
Recommended settings for OPT! and LBO pins
SPEED
CABLE
OPT!
LBO
DS3/STS1
< 225'
HI
HI
DS3/STS1
> 225'
HI
LOW
E3
ALL
LOW
LOW
© 2005 Teridian Semiconductor Corporation
Rev 3.0
Page: 4 of 11
Note:
© 2005 Teridian Semiconductor Corporation
NC pins should be tied to the ground
pin indicated by the trailing letter.
OUTPUT
DRIVER
PULSE
SHAPER 2
PULSE
SHAPER 1
REFERENCE
CURRENT
GENERATOR
VAR
AMP
GAIN
FIGURE 1: Functional Diagram
PULSE
GEN.
PULSE
GEN.
VR1
AMP
78P7200
E3/DS3/STS-1
Line Interface Unit
Rev 3.0
78P7200
E3/DS3/STS-1
Line Interface Unit
PIN DESCRIPTION
RECEIVER
NAME
TYPE
DESCRIPTION
LIN+, LIN-
I
Differential inputs, transformer-coupled from coax cable.
RPOS
O
Unipolar receiver output, active as result of positive pulse at inputs.
RNEG
O
Unipolar receiver output, active as result of negative pulse at inputs.
RCLK
O
Recovered Clock from line data.
LOWSIG
O
Low signal logic output indicating that input signal is less than threshold value.
TPOS
I
Unipolar transmitter data input, active high.
TNEG
I
Unipolar transmitter data input, active high.
TCLK
I
Transmitter clock input, active high.
LOUT+
O
Output to transformer for positive data pulses.
LOUT-
O
Output to transformer for negative data pulses.
LBO
I
Transmitter line buildout control. Set low for all E3 or for DS3/STS-1 cable of 225'
or longer. Set high for short DS3/ STS-1 cable.
OPT!
I
Transmit option 1. Set high for DS3/STS-1 and set low for E3.
[email protected]
I
Transmit option 2. Disables output driver and reduces output bias current when
low. Set high for normal transmit operation.
TRANSMITTER
EXTERNAL COMPONENT CONNECTION
RFO
I
Resistor connected to RGND adjusts the center frequency of receiver phase
locked loop oscillator and the transmitter pulse width and amplitude.
LF1, LF2
-
Resistor-capacitor loop filter network to establish bandwidth of phase locked loop.
CPD
-
Capacitor to RVcc that is connected to peak detector node to reduce signaldependent ripple on that node.
TVcc
-
5V power supply for transmit circuits.
RVcc
-
5V power supply for receive circuits.
DVcc
-
5V power supply for receive logic circuits.
TGND
-
Ground return for transmit circuits.
RGND
-
Ground return for receive circuits.
DGND
-
Ground return for receive logic circuits.
NCR
-
No connect, Tie to Receiver Ground (RGND).
NCT
-
No connect, Tie to Transmitter Ground (TGND).
NCD
-
No connect, Tie to Digital Ground.
POWER
Page: 5 of 11
© 2005 Teridian Semiconductor Corporation
Rev 3.0
78P7200
E3/DS3/STS-1
Line Interface Unit
ELECTRICAL SPECIFICATIONS
(TA = -40°C to 85°C, Vcc = 5V ±5%, unless otherwise noted.) Currents flowing into the chip are positive. Current
maximums are currents with the largest absolute value. Operation above absolute maximum ratings may
permanently damage the device.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
Positive 5V supply: TVcc, RVcc, DVcc
6V
Storage Temperature
-65 to 150°C
Soldering Temperature (10 sec.)
260 °C
Ambient Operating Temperature, TA
-40 to +85°C
Pin Ratings: LOUT+, LOUT-
Vcc -2 to Vcc +2V
LIN+, LIN-, TPOS, TNEG, TCLK, LBO, RFO, LF2, LF1,
OPT!, [email protected] Pins
-0.3 to Vcc +0.3V
RPOS, RNEG, RCLK, LOWSIG Pins
-0.3 to Vcc +0.3V or +12 mA
SUPPLY CURRENTS AND POWER
PARAMETER
Supply Current
Power Dissipation
CONDITIONS
ICC
P
Outputs unloaded, normal
operation, transmit and receive
all 1's pattern
MIN
NOM
MAX
UNIT
155
190
mA
0.93
W
Outputs unloaded, TA = 85°C
EXTERNAL COMPONENTS (Common to STS-1/DS3/E3, nominal value)
Loop filter resistor
RLF1
1% tolerance
6.04
kΩ
Loop filter resistor
RLF2
1%
100
kΩ
Loop filter capacitor
CLF1
5%
0.22
µF
CPD
10%
0.022
µF
Peak detector capacitor
Input Filter
R1, R2
1%
75
Ω
Input Filter
C1
5%
1000
pF
Input Filter
C2
5%
82
pF
Input Filter
C3
20% (See Note)
Input Filter
L1
5%
0.47
µH
Input Filter
L2
5%
6.8
µH
T1, T2
3%
1:2
Receiver Termination ResistorRTR
1%
422
Transformer Turns Ratio
0.01
µF
Ω
Note: Optional capacitor to reduce common mode noise.
Page: 6 of 11
© 2005 Teridian Semiconductor Corporation
Rev 3.0
78P7200
E3/DS3/STS-1
Line Interface Unit
EXTERNAL COMPONENTS (Dependent on speed, nominal Value)
STS-1
DS3
E3
Loop center frequency resistor RFO
1% tolerance
4.53
5.23
6.81
kΩ
Transmit termination capacitor CTT
5% (Note 2)
10
10
3
pF
Transmit termination resistor
1%
301
301
604
Ω
RTT
Note 1: Optional capacitor to reduce common mode noise.
Note 2: CTT value depends on the PC board design. Nominal values are selected for 78P7200 Demo Board.
DIGITAL INPUTS AND OUTPUTS
(CMOS-compatible pins: LOWSIG, RPOS, RNEG, RCLK, TPOS, TNEG, TCLK, LBO, OPT!.) Currents flowing
into the chip are positive. Current maximums are currents with the largest absolute value.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Input low voltage
VIL
-0.3
1.5
V
Input high voltage
VIH
3.5
Vcc
+0.3
V
Input low current
IIL
VIL = 1.5V
-5
5
µA
Input high current
IIH
VIH = 3.5V
-5
5
µA
0.4
V
Output low voltage
VOL
IOL = 0.1 mA
Output high voltage
VOH
IOH = -0.1 mA
4
V
[email protected] CHARACTERISTICS
Input low voltage
VIL
Input high voltage
VIH
IIL = 0.4 mA
0.5
2
V
V
RECEIVER
All of the measurements for the receiver are made with the following conditions unless otherwise stated:
1. The input signal is transformer coupled as shown in Figure 1.
2. RFO = 5.23 kΩ for DS3, 6.81 kΩ for E3 and 4.53 kΩ for STS-1.
Input signal voltage
Short cable (3’)
Input Resistance
VIN
RIN
Receive data detection
threshold
VDTH
Receive data low signal
threshold
VLOW
Receive data low signal
delay
TLOW
Page: 7 of 11
Input AC-Coupled
CPD = 0.022 µF
±0.045
±1.2
V
CPD not used
±0.090
±1.2
V
30
kΩ
Input at device's common mode
voltage
15
Relative to peak amplitude for
22.37/17.18/25.92 MHz
sinusoidal input
20
50
±20
CPD = 0.022 µF
CPD not used
VIN(max) = ±250 mV
© 2005 Teridian Semiconductor Corporation
%
±50
500
0.5
mV
µs
3
µs
Rev 3.0
78P7200
E3/DS3/STS-1
Line Interface Unit
RECEIVER (continued)
PARAMETER
CONDITIONS
Receive clock period
TRCF
Receive clock pulse width
TRC
MIN
NOM
MAX
UNIT
DS3
22.35
ns
STS-1
19.29
ns
E3
29.1
ns
DS3
12.24
ns
STS-1
9.65
ns
E3
14.55
ns
Receive clock positive
transition time
TRCPT
CL = 15 pF
4.5
6
ns
Receive clock negative
transition time
TRCNT
CL = 15 pF
4.5
6
ns
Positive or negative TRDP/ TRDN
receive data pulse width
Receive data set-up timeTRDPS/ TRDNS
DS3
22.35
ns
STS-1
19.29
ns
E3
29.1
ns
DS3
5
STS-1
Receive data hold timeTRDPH/ TRDNH
DS3
5
11.18
Clock Recovery Phase
Detector Gain
Clock Recovery Phase
Locked Oscillator Gain
KD
13.7
ns
9.65
ns
14.55
ns
60 - 300 kHz
DS3
STS-1
0.3
UIPP
10 - 800 kHz
E3
0.15
UIPP
0.20
UIPP
10 Hz to 2.3 kHz STS-1, DS3
10
UIPP
100 Hz to 10 kHz
E3
10
UIPP
DS3
72
10 - 800 kHz
E3
VIN (min) = ±90 mV, short cable
Receive input jitter tolerance
low frequency (See Note)
ns
14.55
5
ns
ns
5
E3
13.7
9.65
E3
STS-1
Receive input jitter tolerance high
frequency (See Note)
11.18
All 1's data pattern,
KD = 0.418/RFO
80
88
µA/Rad
STS-1
92
µA/Rad
E3
62
µA/Rad
KO
12
14.5
17
Mrad/
sec. -Volt
Note: UI (Unit Interval) defined as 22.35 ns for DS3, 29.1 ns for E3 and 19.29 ns for STS-1.
Page: 8 of 11
© 2005 Teridian Semiconductor Corporation
Rev 3.0
78P7200
E3/DS3/STS-1
Line Interface Unit
TRANSMITTER
All of the measurements for the transmitter are made with the following conditions unless otherwise stated:
1. Transmit pulse characteristics are obtained using a line transformer which has the characteristics, similar
to Pulse Engineering PE-65969, Mini circuit T4-1, Valor PT5045.
2. The circuit is connected as in Figure 1.
PARAMETER
Transmit clock repetition
Transmit clock pulse width
CONDITIONS
TTCF
TTC
MIN
NOM
MAX
UNIT
DS3
22.35
ns
STS-1
19.29
ns
E3
29.1
ns
DS3
11.18
ns
STS-1
9.65
ns
E3
14.55
ns
Transmit clock negative
transition time
TTCNT
4.5
6
ns
Transmit clock positive
transition time
TTCPT
4.5
6
ns
Transmit data set-up time TTPDS
Transmit data hold time
Transmit negative line
pulse width
3.5
11.18
ns
STS-1
3.5
9.65
ns
TTNDS
E3
3.5
14.55
ns
TTPDH
DS3
3.5
11.18
ns
STS-1
3.5
9.65
ns
E3
3.5
14.55
ns
10.62
11.18
TTNDH
Transmit positive line
pulse width
DS3
TTPL
TTNL
Transmit line pulse waveshape
Measured at
transformer,
Measured at
transformer,
LBO = High
DS3
12
ns
LBO = High STS-1
9.65
ns
LBO = Low
E3
14.5
ns
LBO = High
DS3
10.62
11.18
12
ns
LBO = High STS-1
9.65
ns
LBO = Low
14.5
ns
E3
See Note 1 for DS3
See Note 2 for E3
See Note 3 for STS-1
Note 1: Characteristics are in accordance with ANSI T1.102 - 1993 Table 4 and Figure 4.
Note 2: Characteristics are in accordance with ITU-T G.703 - 1991 Figure 17.
Note 3: Characteristics are in accordance with ANSI T1.102 - 1993 Figure A.1.
Page: 9 of 11
© 2005 Teridian Semiconductor Corporation
Rev 3.0
78P7200
E3/DS3/STS-1
Line Interface Unit
RECEIVE LINE
INPUT (REF)
TRCF
TRC
TRCPT
TRCNT
REC CLOCK
RCLK
TRDPS
REC POS OUT
RPOS
TRDPH
TRDP
TRDNS
REC NEG OUT
RNEG
TRDNH
TRDN
FIGURE 2: Receive Waveforms
TTCF
TTC
TTCPT
TTCNT
TRANSMIT
CLOCK IN
TCLK
TTPDS
TTPDH
TRANSMIT
POS IN
TPOS
TTNDS
TRANSMIT
NEG IN
TNEG
TTNDH
TTPL
VP
TRANSMIT
LINE OUTPUT
0.5VP
0.5VN
VN
TTNL
FIGURE 3: Transmit Waveforms
Page: 10 of 11
© 2005 Teridian Semiconductor Corporation
Rev 3.0
78P7200
E3/DS3/STS-1
Line Interface Unit
PACKAGE PIN DESIGNATIONS
LIN-
NCR
LIN+
CPD
LOWSIG
NCR
DVCC
CAUTION: Use handling procedures necessary for
a static sensitive component.
(Top View)
4
3
2
1
28 27 26
RFO
5
25
RPOS
RGND
6
24
RNEG
RVCC
7
23
RCLK
TGND
8
22
DGND
LOUT+
9
21
NCD
NCT
10
20
LF2
LOUT-
11
19
LF1
[email protected]
TVCC
TCLK
TNEG
TPOS
OPT!
LBO
12 13 14 15 16 17 18
78P7200
28-Pin PLCC
ORDERING INFORMATION
PART DESCRIPTION
28-Pin PLCC,
Silicon Revision A04
28-Pin PLCC – Lead-Free,
Silicon Revision A04
ORDER NUMBER
78P7200-IH
78P7200-IH/F
PACKAGE MARK
78P7200-IH
xxxxxxP4
78P7200-IH
xxxxxxP4F
No responsibility is assumed by Teridian Semiconductor Corporation for use of this product nor for any infringements of patents and
trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of
Teridian Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice.
Accordingly, the reader is cautioned to verify that you are referencing the most current data sheet before placing orders. To do so, see our
web site at http://www.teridiansemi.com or contact your local Teridian Semiconductor representative.
Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Irvine, CA 92618-5201
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridiansemi.com
Page: 11 of 11
© 2005 Teridian Semiconductor Corporation
Rev 3.0