September 2001 AS6WA25616 3.0V to 3.6V 256K×16 Intelliwatt™ low-power CMOS SRAM with one chip enable Features • AS6WA25616 • Intelliwatt™ active power circuitry • Industrial and commercial temperature ranges available • Organization: 262,144 words × 16 bits • 3.0V to 3.6V at 55 ns • Low power consumption: ACTIVE - 144 mW at 3.6V and 55 ns • Low power consumption: STANDBY • 1.5V data retention • Equal access and cycle times • Easy memory expansion with CS, OE inputs • Smallest footprint packages - 48-ball FBGA - 400-mil 44-pin TSOP 2 • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Pin arrangement (top view) - 72 µW max at 3.6V 44-pin 400-mil TSOP 2 A4 44 1 A5 A3 A6 43 2 A2 3 A7 42 A1 4 OE 41 A0 5 40 UB CS 6 39 LB I/O16 7 38 I/O1 I/O15 I/O2 8 37 I/O14 I/O3 9 36 I/O13 10 I/O4 35 VCC VSS 11 34 VSS VCC 12 33 13 32 I/O5 I/O12 I/O6 14 31 I/O11 I/O7 15 30 I/O10 I/O8 16 29 I/O9 17 WE 28 NC 18 27 A17 A8 19 26 A16 A9 20 25 A10 A15 A14 24 A11 21 A13 23 A12 22 Logic block diagram VCC Row Decoder A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1–I/O8 I/O9–I/O16 256K × 16 Array (4,194,304) I/O buffer Control circuit VSS Column decoder A5 A9 A10 A11 A14 A15 A16 A17 WE UB OE LB CS 48-CSP Ball-Grid-Array Package A B C D E F G H 1 LB I/O9 I/O10 VSS VCC I/O15 I/O16 NC 2 3 OE A0 UB A3 I/O11 A5 I/O12 A17 I/O13 NC I/O14 A14 NC A12 A8 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CS I/O2 I/O4 I/O5 I/O6 WE A11 6 NC I/O1 I/O3 VCC VSS I/O7 I/O8 NC Selection guide VCC Range Power Dissipation Typ2 (V) Max (V) Speed (ns) Operating (ICC) Standby (ISB1) Product Min (V) Max (mA) Max (µA) AS6WA25616 3.0 3.3 3.6 55 2 20 7/9/02; v.1.3 Alliance Semiconductor P. 1 of 9 Copyright ©Alliance Semiconductor. All rights reserved. AS6WA25616 Functional description The AS6WA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words × 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS) permit easy memory expansion with multiple-bank memory systems. When CS is high, or UB and LB are high, the device enters standby mode: the AS6WA25616 is guaranteed not to exceed 72 µW power consumption at 3.6V and 55 ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption. A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low, and UB and/or LB low. Data on the input pins I/O1–O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/ O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), chip select (CS), UB and LB low, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode. These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16. All chip inputs and outputs are CMOS-compatible, and operation is from a single 3.0 to 3.6V supply. Device is available in the JEDEC standard 400-mm, TSOP 2, and 48-ball FBGA packages. Absolute maximum ratings Parameter Device Symbol Min Max Unit Voltage on VCC relative to VSS VtIN –0.5 VCC + 0.5 V Voltage on any I/O pin relative to GND VtI/O –0.5 Power dissipation PD – 1.0 W Storage temperature (plastic) Tstg –65 +150 °C Temperature with VCC applied Tbias –55 +125 °C DC output current (low) IOUT – 20 mA V Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CS WE OE LB UB H X X X X L X X H H L H H X X L H H L L L L H L L X Supply Current I/O1–I/O8 I/O9–I/O16 Mode ISB High Z High Z Standby (ISB) ICC High Z High Z Output disable (ICC) DOUT High Z High Z DOUT L DOUT DOUT L H DIN High Z H L High Z DIN L L DIN DIN ICC ICC Read (ICC) Write (ICC) Key: X = Don’t care, L = Low, H = High. 7/9/02; v.1.3 Alliance Semiconductor P. 2 of 9 AS6WA25616 Recommended operating condition (over the operating range) Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –2.1mA VCC = 3.0 - 3.6V VOL Output LOW Voltage IOL = 2.1mA VCC = 3.0 - 3.6V VIH Input HIGH Voltage VCC = 3.0 - 3.6V VIL Input LOW Voltage VCC = 3.0 - 3.6V IIX Input Load Current IOZ Output Load Current ICC VCC Operating Supply Current CS = VIL, VIN = VIL or VIH, IOUT = 0mA, f=0 ICC1 @ 1 MHz Average VCC Operating Supply Current at 1 MHz ICC2 Max 2.4 Unit V 0.4 V 2.2 VCC + 0.5 V –0.5 0.8 V GND < VIN < VCC –1 +1 µA GND < VO < VCC; Outputs High Z –1 +1 µA VCC = 3.6V 2 mA CS < 0.2V, VIN < 0.2V or VIN > VCC – 0.2V, f = 1 mS VCC = 3.6V 5 mA Average VCC Operating Supply Current CS ≠ VIL, VIN = VIL or VIH, f = fMax VCC = 3.6V 40 mA ISB CS Power Down Current; TTL Inputs CS > VIH or UB = LB > VIH, other inputs = VIL or VIH, f = 0 VCC = 3.6V 100 µA ISB1 CS > VCC – 0.2V or CS Power Down Current; UB = LB > VCC – 0.2V, CMOS Inputs other inputs = 0V – VCC, f=0 VCC = 3.6V 20 µA Capacitance (f = 1 MHz, Ta = Room temperature, VCC = NOMINAL) Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CS, WE, OE, LB, UB VIN = 0V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF 7/9/02; v.1.3 Alliance Semiconductor P. 3 of 9 AS6WA25616 Read cycle (over the operating range) Parameter Symbol Min Max Unit Notes Read cycle time tRC 55 – ns Address access time tAA – 55 ns 3 Chip select (CS) access time tACS – 55 ns 3 Output enable (OE) access time tOE – 25 ns Output hold from address change tOH 10 – ns 5 CS low to output in low Z tCLZ 10 – ns 4, 5 CS high to output in high Z tCHZ 0 20 ns 4, 5 OE low to output in low Z tOLZ 5 – ns 4, 5 UB/LB access time tBA – 55 ns UB/LB low to low Z tBLZ 10 – ns 4, 5 UB/LB high to high Z tBHZ 0 20 ns 4, 5 OE high to output in high Z tOHZ 0 20 ns 4, 5 Power up time tPU 0 – ns 4, 5 Power down time tPD – 55 ns 4, 5 Shaded areas indicate preliminary information. Key to switching waveforms Rising input Falling input Undefined/don’t care Read waveform 1 (address controlled) tRC Address tOH DOUT tAA tOH Previous data valid Data valid Read waveform 2 (CS, OE, UB, LB controlled) tRC Address tAA OE tOE tOLZ tOH CS tLZ tOHZ tACS tHZ LB, UB tBLZ tBA DOUT 7/9/02; v.1.3 tBHZ Data valid Alliance Semiconductor P. 4 of 9 AS6WA25616 Write cycle (over the operating range). Parameter Symbol Min Max Unit Notes Write cycle time tWC 55 – ns Chip select to write end tCW 40 – ns Address setup to write end tAW 40 – ns Address setup time tAS 0 – ns Write pulse width tWP 35 – ns Write recovery time tWR 0 – ns Address hold from end of write tAH 0 – ns Data valid to write end tDW 25 – ns Data hold time tDH 0 – ns 4, 5 Write enable to output in high Z tWZ 0 20 ns 4, 5 Output active from write end tOW 5 – ns 4, 5 UB/LB low to end of write tBW 35 – ns 12 12 Write waveform 1 (WE controlled) tWC tWR Address tAH tCW CS tBW LB, UB tAW tAS tWP WE tDW DIN Data valid tWZ DOUT tDH tOW Data undefined High Z Write waveform 2 (CS controlled) tWC tWR tCW tAH Address tAS CS tAW tBW LB, UB tWP WE tDW DIN DOUT 7/9/02; v.1.3 tCLZ High Z tWZ Data undefined Alliance Semiconductor tDH Data valid tOW High Z P. 5 of 9 AS6WA25616 Data retention characteristics (over the operating range) Parameter Symbol Test conditions Min Max Unit VCC for data retention VDR 1.5V - V Data retention current ICCDR – 10 µA Chip deselect to data retention time tCDR VCC = 1.5V CS ≥ VCC – 0.1V or UB = LB = > VCC – 0.1V VIN ≥ VCC – 0.1V or VIN ≤ 0.1V 0 – ns tRC – ns Operation recovery time tR Data retention waveform Data retention mode VCC VDR ≥ 1.5V VCC VCC tCDR tR VDR VIH CS VIH AC test loads and waveforms Thevenin equivalent: R1 VCC OUTPUT R1 VCC OUTPUT 30 pF 5 pF (a) R2 INCLUDING JIG AND SCOPE VTH ALL INPUT PULSES R2 INCLUDING JIG AND SCOPE RTH OUTPUT VCC Typ GND 90% 10% (b) 90% < 5 ns 10% (c) Parameters VCC = 3.6V Unit R1 1523 Ohms R2 1142 Ohms RTH 476 Ohms VTH 1.4V Volts Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 During VCC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is HIGH for read cycle. CS and OE are LOW for read cycle. Address valid prior to or coincident with CS transition LOW. All read cycle timings are referenced from the last valid address to the first transitioning address. CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. 1.5V data retention applies to commercial and industrial temperature range operations. C = 30pF, except at high Z and low Z parameters, where C = 5pF. 7/9/02; v.1.3 Alliance Semiconductor P. 6 of 9 AS6WA25616 Typical DC and AC characteristics Normalized supply current vs. supply voltage Normalized access time vs. supply voltage 1.4 1.0 2.5 Normalized TAA VIN = VCC typ TA = 25° C 1.0 3.0 0.8 0.6 0.4 0.75 Normalized ISB2 1.2 Normalized ICC Normalized standby current vs. ambient temperature TA = 25° C 0.5 1.5 1.0 0.5 0.0 0.25 0.2 VCC = VCC typ VIN = VCC typ 2.0 –0.5 0.0 1.7 2.2 2.7 3.2 3.7 0.0 1.7 2.2 Supply voltage (V) 2.7 3.2 3.7 –55 Supply Voltage (V) 25 105 Ambient temperature (°C) Normalized standby current vs. supply voltage Normalized ICC vs. Cycle Time 1.4 1.0 Normalized ICC Normalized ISB 1.5 ISB2 1.2 0.8 0.6 0.4 VCC = 3.6V TA = 25° C 1.0 0.50 VIN = VCC typ TA = 25° C 0.2 0.10 0.0 2.8 1.9 Supply voltage (V) 1 1 3.7 5 10 Supply voltage (V) 15 Package diagrams and dimensions 44-pin TSOP 2 c 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Min (mm) A e He 44-pin TSOP 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A2 A A1 b l 0–5° 0.05 A2 0.95 1.05 b 0.25 0.45 18.28 18.54 e 10.06 10.26 He 11.56 11.96 l 7/9/02; v.1.3 Alliance Semiconductor 0.15 (typical) d E E 1.2 A1 c d Max (mm) 0.80 (typical) 0.40 0.60 P. 7 of 9 AS6WA25616 48-ball FBGA Top View Bottom View 6 5 4 3 2 1 Ball #A1 Index Ball #A1 A B C D SRAM Die C1 C E F A G H Elastomer A B B1 Detail View Side View A E2 D E E2 Y E Die Die E1 7/9/02; v.1.3 0.3/Typ Minimum Typical Maximum A – 0.75 – B 6.90 7.00 7.10 B1 – 3.75 – C 10.90 11 11.10 C1 – 5.25 – D 0.30 0.35 0.40 5. Typ: typical. E – – 1.20 6. Y is coplanarity: 0.08 (max). E1 – 0.68 – E2 0.22 0.25 0.27 Y – – 0.08 Notes 1. Bump counts: 48 (8 row × 6 column). 2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ). 3. Units: millimeters. 4. All tolerance are ±0.050 unless otherwise specified. Alliance Semiconductor P. 8 of 9 AS6WA25616 Ordering codes Speed (ns) 55 55 Ordering Code Package Type AS6WA25616-TC 44-pin TSOP 2 AS6WA25616-BC 48-ball fine pitch BGA AS6WA25616-TI 44-pin TSOP 2 AS6WA25616-BI 48-ball fine pitch BGA Operating Range Commercial Industrial Part numbering system AS6WA 25616 T, B C, I SRAM Intelliwatt™ prefix Device number Package: T: TSOP 2 B: CSP/BGA Temperature range: C: Commercial: 0° C to 70° C I: Industrial: –40° C to 85° C 7/9/02; v.1.3 Alliance Semiconductor P. 9 of 9 © Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. 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