ETC C8051

8-bit Control Unit
8-bit Arithmetic-Logic Unit with
8-bit multiplication and division
Instruction decoder
Legacy-Speed 8-Bit
Processor Core
Two 16-bit Timer/Counters
Four 8-bit Input / Output ports
Serial Peripheral Interface in full
duplex mode
Synchronous mode, fixed baud
The C8051 core implements a single-chip, 8-bit microcontroller that executes all ASM51
instructions and has the same instruction set and timing of the 80C31. On-chip debugging is an option.
The microcode-free design was developed for reuse in ASICs and FPGAs. It is strictly
synchronous, with positive-edge clocking (except for a flip-flop for internal reset and two
flip-flops for gated clocks in the PMU), no internal tri-states and a synchronous reset.
Scan insertion is therefore straightforward.
8-bit & 9-bit UART mode, variable baud rate
9-bit UART mode, fixed baud
Multiprocessor communication
Two Level Priority Interrupt System
5 Interrupt Sources
Internal Clock prescaler and
Phase Generator
The C8051 can be utilized for a variety of applications including:
• Embedded microcontroller systems
• Data computation and transfer
256 bytes of Read/Write Data
Memory Space
64KB External Program Memory
64KB External Data Memory
• Communication systems
Services up to 107 External
Special Function Registers
• Professional audio and video
Power Management Unit supports stop and idle modes
On-Chip-Instrumentation Debugging (optional)
Optional Features
Fast Multiplication-Division Unit
o 16 x 16 bit multiplication
o 32 bit L/R shifting
o 32 / 16 bit division
o 16 / 16 bit division
o 32 bit normalization
Compare/Capture Unit
o Four 16-bit Compare registers
used for Pulse With Modulation
o Four external Capture inputs
used for Pulse With Measuring
o 16-bit Reload register used
for Pulse Generation
Programmable Watchdog Timer
Third 16-bit Timer/Counter
Second Serial Peripheral Interfaces
Real Time Clock
On-Chip-Instrumentation Debugging
May 2004
Functional Description
The C8051 is partitioned into modules described below:
Memory Control Unit
mode. In asynchronous mode, full duplex operation is
available. Receive data is buffered in a holding register.
This allows the serial to receive an incoming word before
software has read the previous value.
• Can address up to 64K bytes of External Program
Memory Space
The port provides four operating modes. These offer different communication protocols and baud rates:
• Can address up to 64K bytes of External Data Memory
• Synchronous mode, fixed baud rate
Core Engine
• 9-bit UART mode, fixed baud rate
The C8051 engine is composed of four components:
• 9-bit UART mode, variable baud rate
• Control unit
Interrupt Service Routine
• Arithmetic-logic unit
The C8051 core improves two-priority interrupt system.
There are 5 interrupt sources. Each source has an independent priority bit, flag, interrupt vector, and enable. In
addition, interrupts can be globally enabled or disabled.
• Memory control unit
• RAM and SFR control unit
The C8051 engine allows fetching instructions from program memory and execution using RAM or SFR.
Control Unit
The Control Unit performs instruction fetch and execution
from the Memory Control Unit and the RAM_SFR Control
• 8-bit UART mode, variable baud rate
The C8051 provides four I/O ports. Port 0 – Port 3 is an 8bit bi-directional I/O ports with separated inputs and outputs.
RAM and SFR Unit
Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data memories.
• Can Address up to 256 bytes of Read/Write Data Memory space
Port 1 also serves the special features like external interrupt inputs, Serial 1 interface, and Timer 2 inputs.
• Serves the interface for off-core Special Function Registers
Port 2 emits the high-order address byte during fetches
from external program memory that use 16-bit addresses
Arithmetic-logic Unit
• 8-bit arithmetic & logic operations
• Boolean manipulations
• 8 x 8-bit multiplication
• 8 / 8-bit division
Timer 0 and 1
Timers 0 and 1 are nearly identical. Timers 0 and 1 both
have four modes. They are:
• 13-bit Timer/counter
Port 3 also serves the special features such as read and
write strobes for external data memory, Serial 0 interface,
Timer 0 and Timer 1 inputs.
Clock Control
The Clock Control unit generates the internal synchronous
reset. It also contains registers for selecting the clock for
Interface for On-Chip Instrumentation
• 8-bit timer/counter with auto reload
The OCI unit serves as an interface for On-Chip Instrumentation. The OCI provides the following functions for
communication with On-Chip Instrumentation:
• two 8-bit timers
• the run/stop control
The later mode is available to Timer 0 only. Each timer can
also serve as a counter of external pulses (1 to 0 transition)
on the corresponding T0 or T1 pin. One other option is to
gate the timer/counter using an external control signal. This
allows the timer to measure the pulse width of external signals.
• single-step mode
• access to ACC register
The C8051 core provides interface for serial communication. The serial port is capable of both synchronous and
asynchronous modes. In synchronous mode, the microcontroller generates the clock and operates in a half-duplex
Power Management Unit
• 16-bit Timer/counter
• software breakpoint
• debugger program
• hardware breakpoint
• program trace
Power Management Unit serves two power management
modes IDLE and STOP.
The core as delivered is warranted against defects for three
years from purchase. Thirty days of phone and email technical support are included, starting with the first interaction.
Additional maintenance and support options are available.
The C8051 core’s functionality was verified by means of a
proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Intel
80C31 chip, and the results compared with the core’s simulation outputs.
The core includes everything required for successful implementation:
• HDL source code for the C8051
• Synthesis & simulation scripts
• Example CHIP_C8051 – 8051 compatible design
This design uses the C8051 and illustrates how to build
and connect memories and port modules
• Extensive HDL testbench that instantiates:
− Example design CHIP_C8051
− External RAM
− External ROM
− Clock generator
− Process that compares your simulation results with
the expected results
• A collection of 8051 assembler programs which are executed directly by the testbench
• A set of expected results
• Documentation
• Design support including consulting
CAST, Inc. 11 Stonewall Court
Woodcliff Lake, NJ 07677 USA
tel 201-391-8300 fax 201-391-8694
Copyright © CAST, Inc. 2004, All Rights Reserved.
Contents subject to change without notice.
Trademarks are the property of their respective owners.
This core developed by the processor
experts at Evatronix SA.