ETC NAT9914BPD

IEEE 488.2 Controller Chip
NAT9914
Pin compatible with TI TMS9914A
Software compatible with
NEC µPD7210 or TI TMS9914A
controller chips
Low power consumption
Meets all IEEE 488.2 requirements
Bus line monitoring
Preferred implementation of
requesting service
Will not send messages when there
are no Listeners
Performs all IEEE 488.1
interface functions
Programmable data transfer rate
(T1 delays of 350 ns, 500 ns,
1.1 µs, and 2 µs)
Automatic EOS and/or NL message
detection
Direct memory access (DMA)
Automatically processes IEEE 488
commands and reads
undefined commands
TTL-compatible CMOS device
Programmable clock rate
20 MHz maximum
Reduces driver overhead
Does not lose a data byte
if ATN is asserted while
transmitting data
ni.com/store
Description
General
The NAT9914 IEEE 488.2 controller chip can perform all the
interface functions defined by the IEEE Standard 488.1-1987, and
also meets the additional requirements and recommendations
of the IEEE Standard 488.2-1987. Connected between the
processor and the IEEE 488 bus, the NAT9914 provides highlevel management of the IEEE 488 bus, significantly increases
the throughput of driver software, and simplifies both the
hardware and software design. The NAT9914 performs
complete IEEE 488 Talker, Listener, and Controller functions. In
addition to its numerous improvements, the NAT9914 is also
completely pin compatible with the TI TMS 9914A and
software compatible with the NEC µPD7210 and TI TMS9914A
controller chips.
The NAT9914 manages the IEEE 488 bus. You program the
IEEE 488 bus by writing control words into the appropriate
registers. CPU-readable status registers supply operational
feedback. The NAT9914 mode determines the function of
these registers. On power up or reset, the NAT9914 registers
resemble those of the TMS9914A set, with additional registers that
supply extra functionality and IEEE 488.2 compatibility. In this
mode, the NAT9914 is completely pin compatible with
the TI TMS9914A. If you enable the 7210 mode, the registers
resemble those of the NEC µPD7210 set, with additional registers
that supply extra functionality and IEEE 488.2 compatibility. This
mode is not pin compatible with the NECµPD7210. Figure 4
shows the key components of the NAT9914.
IEEE 488.2 Overview
The IEEE 488.2 standard removes the ambiguities of IEEE 488.1
by standardizing the way instruments and controllers operate. It
defines data formats, status reporting, error handling, and
common configuration commands to which all IEEE 488.2
instruments must respond in a precise manner. It also defines a
set of controller requirements. With IEEE 488.2, you gain the
benefits of reduced development time and cost because systems
are more compatible and reliable. The NAT9914 brings the full
power of IEEE 488.2 to the design engineer along with
numerous other design and performance benefits, while
retaining the 40-pin and 44-pin hardware configurations of the
TI TMS 9914A.
ACCRQ
ACCGR
CE
WE
DBIN
RS0
RS1
RS2
INT
D7
D6
D5
D4
D3
D2
D1
D0
CLK
RESET
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NAT9914BPD
IEEE 488.2 Controller Chip
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Pin Identification
VDD
TR
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
DIO8
CONT
SRQ
ATN
EOI
DAV
NRFD
NDAC
IFC
REN
TE
PLCC
11, 12, 13,
14, 15, 16,
17, 19
Pin Number
DIP
QFP
10, 11, 12, 16, 17, 18,
13, 14, 15, 19, 20, 21,
16, 17
22, 24
Mnemonic
D(7-0)
Type
I/O
†
4
3
9
CE*
I
6
5
11
DBIN
I
5
4
10
WE*
I
3
2
8
ACCGR*
I
2
1
7
ACCRQ*
O
20
21
18
19
25
26
CLK
RESET*
I
I
10
9
15
INT*
(OC)
O
9, 8, 7
8, 7, 6
14, 13, 12
RS(2-0)
I
25
23
30
IFC*
24
22
29
REN*
31
28
36
ATN*
I/O ,
(OC)
I/O
(OC)
I/O
32
29
37
SRQ*
I/O
34, 35, 36,
37, 38, 39,
41, 42
29
31, 32, 33,
34, 35, 36
37, 38
26
39, 40, 41,
42, 43, 44,
2, 3
34
DIO(8-1)*
I/O
DAV*
I/O
27
25
32
NRFD*
I/O
26
24
31
NDAC*
I/O
30
27
35
EOI*
I/O
23
21
28
TE
O
†
DBIN
WE
CE
ACCGR
ACCRQ
NC
VDD
TR
DIO1
DIO2
NC
Figure 1. NAT9914BPD
Pin Configuration
6 5 4 3 2 1 44 43 42 41 40
7
39
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
18 19 20 21 22 23 24 25 26 27 28
NAT9914BPL
DIO3
DIO4
DIO5
DIO6
DIO7
DIO8
CONT
SRQ
ATN
EOI
DAV
NC
D0
CLK
RESET
VSS
TE
REN
IFC
NDAC
NRFD
NC
RS0
RS1
RS2
INT
D7
D6
D5
D4
D3
D2
D1
NC
NRFD
NDAC
IFC
REN
TE
VSS
RESET
CLK
D0
NC
Figure 2. NAT9914BPL
Pin Configuration
33 32 31 30 29 28 27 26 25 24 23
34
22
21
35
20
36
19
37
18
38
17
39
16
40
15
41
14
42
13
43
12
44
1 2 3 4 5 6 7 8 9 10 11
NAT9914BPQ
NC
DIO2
DIO1
TR
VDD
NC
ACCRQ
ACCGR
CE
WE
DBIN
DAV
EOI
ATN
SRQ
CONT
DIO8
DIO7
DIO6
DIO5
DIO4
DIO3
Figure 3. NAT9914BPQ
Pin Configuration
2
D1
D2
D3
D4
D5
D6
D7
INT
RS2
RS1
RS0
National Instruments
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†
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Description
Bidirectional 3-state data bus transfers
commands, data, and status between the
NAT9914 and the CPU.
D0 is the most significant bit.
Chip Enable gives access to the register
selected by a read or write operation, and the
register selects RS(2-0).
With the Data Bus Input, you can place the
contents of the register selected by RS(2-0)
and CE* onto the data bus D(7-0). The polarity
of DBIN is reversed for DMA operation.
The Write input latches the contents of the
data bus D(7-0) into the register selected by
RS(2-0).
The Access Grant signal selects the DIR or
CDOR for the current read or write cycle.
The Access Request output asserts to request
a DMA Acknowledge cycle.
The CLK input can be up to 20 MHz.
Asserting the RESET* input places the
NAT9914 in an initial, idle state.
The Interrupt output asserts when one of the
unmasked interrupt conditions is true. The
NAT9914 does not drive INT* high. The INT*
pin must be pulled up by an external resistor.
The Register Selects determine which register
to access during a read or write operation.
Bidirectional control line initializes the
IEEE 488 interface functions.
Bidirectional control line selects either remote
or local control of devices.
Bidirectional control line indicates whether
data on the DIO lines is an interface or devicedependent message.
Bidirectional control line requests service from
the controller.
8-bit bidirectional IEEE 488 data bus
Handshake line indicates that the data on the
DIO(8-1)* lines is valid.
Handshake line indicates that the device is
ready for data.
Handshake line indicates the completion of a
message reception.
Bidirectional control line indicates the last byte
of a data message or executes a parallel poll.
Talk Enable controls the direction of the
IEEE 488 data transceiver.
IEEE 488.2 Controller Chip
PLCC
43
33
44
22
1, 18,
28,40
Pin Number
DIP
39
30
40
20
–
QFP
4
38
5
27
1, 6,
23, 33
Mnemonic
TR
CONT*
VDD
VSS
NC
Type
O
O
–
–
–
†
†
Description
Trigger asserts when one of the trigger conditions is satisfied.
Controller asserts when the NAT9914 is Controller-In-Charge.
Power pin – +5 V (±5%)
Ground pin – 0 V
No connect
OC= Open collector.
†
The pin contains an internal pull-up resistor of 25 kΩ to 100 kΩ.
* Active low.
††
In controller applications where the CLK signal frequency is > 8 MHz, IFC* should be pulled up with a 4.7 kΩ resistor.
†††
RS0 and RS1 contain an internal pull-up resistor of 25 kΩ to 100 kΩ. RS2 does not contain an internal pull-up or pull-down resistor.
D(7-0)
Data-In
CE*
RS(2-0)
DBIN
WE*
DIO(8-1)*
Message
Decoder
Command Pass Through
Read/
Write
Control
Command/Data Out
ACCRQ*
ACCGR*
Interface
Functions
Address Status
SH1
Address
Compare
Address Mode
AH1
CONT*
TE
TR
T5/TE5
L3/LE3
Interrupt Mask 0, 1, 2
Compare
End-of-String
SR1
RL1
PP1/PP2
Interrupt Status 0, 1, 2
INT*
CLK
DC1
Internal Count
Internal Count 2
DT1
C1-C5
Serial Poll
RSV Gen
Parallel Poll
EOI Gen
Aux A, B, E, F, G, I
SASR
RESET*
STB Out
SYNC
Auxiliary
Command Decoder
Bus Status
and Control
GPIB
Control
Version
Figure 4. NAT9914 Block Diagram
National Instruments
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3
IEEE 488.2 Controller Chip
9914 Mode Registers
7210 Mode Registers
In 9914 mode, the NAT9914 registers consist of all the
TI TMS9914A registers and two types of additional registers – newly
defined registers and paged-in registers. The NAT9914 maps the newly
defined registers into the unused portion of the 9914 address space.
Each paged-in register appears at Offset 2 immediately after you issue an
auxiliary page-in command, and it remains there until you page another
register into the same space or you issue a reset. The table below lists all
the registers in the 9914 register set. See the NAT9914 Reference Manual
available at ni.com for more information.
The NAT9914 registers include all the NEC µPD7210 registers plus two
types of additional registers – extra auxiliary registers and paged-in
registers. You write the extra auxiliary registers the same as standard
µPD7210 auxiliary registers. On issuing an auxiliary page-in command,
the paged-in registers appear at the same offsets as existing µPD7210
registers. At the end of the next CPU access, the chip pages out the
paged-in registers. The following table lists all the registers in the 7210
mode register set. See the NAT9914 Reference Manual available at
ni.com for more information.
9914 Register Set
7210 Register Set
Register
PAGE-IN
RS(2-0)
WE*
DBIN
CE* ACCGR*
Register
PAGE-IN
WE*
DBIN
CE*
Interrupt Status 0
U
0
0
0
1
1
0
1
Data-In
U
0
0
0
1
1
0
1
Interrupt Mask 0
U
0
0
0
0
0
0
1
Data-In
X
X
X
X
X
0
X
0
Interrupt Status 1
U
0
0
1
1
1
0
1
Command/Data Out
U
0
0
0
0
0
0
1
Interrupt Mask 1
U
0
0
1
0
0
0
1
Command/Data Out
X
X
X
X
0
1
X
0
Address Status
U
0
1
0
1
1
0
1
Interrupt Status 1
U
0
0
1
1
1
0
1
P
0
1
0
0
0
0
1
Interrupt Mask 1
U
0
0
1
0
0
0
1
P
0
1
0
0
0
0
1
Interrupt Status 2
U
0
1
0
1
1
0
1
†
Interrupt Mask 2
†
End-of-String
†
Bus Control
ACCGR*
P
0
1
0
0
0
0
1
Interrupt Mask 2
U
0
1
0
0
0
0
1
Accessory
†
P
0
1
0
0
0
0
1
Serial Poll Status
N
0
1
1
1
1
0
1
Bus Status
U
0
1
1
1
1
0
1
Serial Poll Mode
N
0
1
1
0
0
0
1
Auxiliary Command
U
0
1
1
0
0
0
1
Version
P
0
1
1
1
1
0
1
Interrupt Status 2
P
1
0
0
1
1
0
1
Internal Counter 2
P
0
1
1
0
0
0
1
Address
1
†
U
1
0
0
0
0
0
1
Address Status
U
1
0
0
1
1
0
Serial Poll Status
P
1
0
1
1
1
0
1
Address Mode
U
1
0
0
0
0
0
1
Serial Poll Mode
U
1
0
1
0
0
0
1
Command Pass Through
N
1
0
1
1
1
0
1
†
Command Pass Through
U
1
1
0
1
1
0
1
Auxiliary Mode
U
1
0
1
0
0
0
1
Parallel Poll
U
1
1
0
0
0
0
1
Source/Acceptor Status
P
1
0
1
1
1
0
1
Data-In
U
1
1
1
1
1
0
1
Address 0
N
1
1
0
1
1
0
1
Data-In
U
X
X
X
X
0
X
0
Address
N
1
1
0
0
0
0
1
Command/Data Out
U
1
1
1
0
0
0
1
Interrupt Status 0
P
1
1
0
1
1
0
1
Command/Data Out
U
X
X
X
0
1
X
0
Interrupt Mask 0
P
1
1
0
0
0
0
1
Address 1
N
1
1
1
1
1
0
1
End-of-String
N
1
1
1
0
0
0
1
Bus Status
P
1
1
1
1
1
0
1
P
1
1
1
0
0
0
1
The ' ' symbol denotes features (such as registers and auxiliary commands) that are not available in the TMS9914A.
†
Notes for the PAGE-IN column:
U = Page-in auxiliary commands do not affect
the register offset.
P = The register offset is valid only after a page-in
auxiliary command.
4
A(2-0)
National Instruments
Tel: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • ni.com/gpib
†
†
†
†
†
Bus Control
The ' ' symbol denotes features (such as registers and auxiliary commands) that are not available in the NEC7210.
†
Notes for the PAGE-IN column:
U = The page-in auxiliary command does not affect
the register.
N = The register offset is always valid except for immediately
after a page-in auxiliary command.
P = The register is valid only immediately after a page-in
auxiliary command.
IEEE 488.2 Controller Chip
Preliminary DC Characteristics
Absolute Maximum Ratings
TA 0 to 70 °C; VCC = 5 V ±5%
Limits
Parameter
Voltage input low
Voltage input high
Voltage output low
Voltage output high
Input/output
Leakage current
Input/output
Leakage current
Supply current
Output current low
All pins except ACCRQ
ACCRQ
Input current low
Supply voltage
Symbol
VIL
VIH
VOL
VOH
–
Min
-0.5
+2.0
0
+2.4
-10
Max
+0.8
VCC
0.4
VCC
+10
Unit
V
V
V
V
µA
–
-200
+200
µA
–
–
45
mA
Test
Condition
–
–
–
–
without
internal pull-up
with internal
pull-up
–
IOL
IOL
IIL
VDD
2
4
–
4.75
–
–
- 0.5
5.25
mA
mA
mA
V
0.4 V @ IOL
0.4 V @ IOL
–
–
Capacitance
TA 0 to 70 °C; VCC = 5 V ±5%
Parameter
Input
capacitance
Output
capacitance
I/O capacitance
Limits
Min
Max
–
10
Symbol
CIN
Unit
pF
Test
Condition
–
COUT
–
10
pF
–
CI/O
–
10
pF
–
Property
Supply voltage, VDD
Input voltage, VI
Operating temperature, TOPR
Storage temperature, TSTG
Range
-0.5 to +7.0 V
-0.5 to VDD +0.5 V
0 to +70° C
-40 to +125° C
Comment: Exposing the device to stresses above those listed could cause permanent damage. The
device is not meant to be operated under conditions outside the limits described in the operational
section. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
AC Characteristics
TA 0 to 70 °C; VCC = 5 V ±5%
Limits
Parameter
Test
Symbol
Min
Max
Unit
Condition
Address hold from CE, WE,and DBIN
tAH
0
–
ns
–
Address setup to CE , WE, and DBIN
tAS
0
–
ns
–
Data float from CE or DBIN
tDF
–
20
ns
–
Data delay from DBIN↓
tDR
–
75
ns
ACCGR=0
ACCRQ unassertion
tDU
–
20
ns
–
Data delay from CE↓
tRD
–
80
ns
ACCGR=1
CE recovery width
tRR
80
–
ns
–
CE pulse width
tRW
80
–
ns
–
Data hold from WE↑
tWH
0
–
ns
–
Data setup to WE↑
tWS
60
–
ns
–
Notes:
• tAS is the setup time to CE↓ or WE↓ , whichever is later.
• tAH is the hold time from WE↑ or CE↑ , whichever is earlier.
Timing Waveforms
tAS
tAH
RS2-RS0
RS2-0
tAH
tAS
DBIN
CE
tDF
tRD
CE
WE
tWS
D7-0
tWH
D7-0
tRW
tRR
Figure 7. CPU Write
Figure 5. CPU Read
ACCRQ
tDU
ACCRQ
tDU
ACCGR
ACCGR
DBIN
DBIN
tDR
tDF
WE
tWS
D7-0
tWH
D7-0
Figure 6. DMA Read
Figure 8. DMA Write
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5
IEEE 488.2 Controller Chip
Source Handshake
Response to ATN
Parameter
Symbol
Limits (ns)
Min Max
Test
Condition
NDAC↑ to DAV↑
tND
–
40
–
NDAC↑ to INT↓ or ACCRQ↓
tNI
–
40
INT(DOIE Bit=1)
ACCGR (DMAO Bit=1)
WE ↑ to DAV↓
tWD
2000
2180
2 µs T1, 5MHz
WE ↑ to DAV↓
tWD
1200
1380
1.1 µs T1, 5MHz
WE ↑ to DAV↓
tWD
600
780
500 ns T1, 5MHz
WE ↑ to DAV↓
tWD
400
580
350 ns T1, 5MHz
Parameter
ATN↑ to NRFD↓
Symbol
tAF
Limits (ns)
Min
Max
35
ATN↓ to NDAC↓
tAN
35
Test
Condition
Acceptor handshake
holdoff
AIDS → ANRS
ATN↓ to TE↓
tAT
30
TACS → TADS
ATN
tAT
WE
TE
D7-0
NDAC
tAN
tAF
NRFD
tNI
INT/ACCGR
DIO 8-1
Figure 11. ATN Response Timing
tWD
DAV
Parallel Poll
tND
NDAC
Parameter
EOI↓ to DIO↓ valid
EOI↓ to TE↑
EOI↑ to TE↓
Figure 9. Source Handshake Timing
Acceptor Handshake
Parameter
Symbol
DAV↓ to NDAC↑
DAV ↑ to NDAC↓
DAV↓ to INT↓ or ACCRQ↓
Limits (ns)
Min
Max
tDD
tDF
tDI
DAV↓ to NRFD↓
DBIN↑ to NRFD↑
35+3T
25
50+2T
tDR
tNR
20
35
Limits (ns)
Min
Max
Symbol
tED
tET
tTE
Test
Condition
ATN
INT(DIIE Bit=1),
ACCGR (DMAI Bit=1)
EOI
tTE
TE
Read of DIR, not in
Holdoff state
DIO
tET
tED
Figure 12. Parallel Poll Response Timing
tDF
NDAC
tDD
tDR
tNR
NRFD
tDI
INT/ACCRQ
DBIN
Figure 10. Acceptor Handshake Timing
6
PPSS → PPAS
PPSS → PPAS
PPAS → PPSS
90
30
30
Note: T = one clock period
DAV
Test
Condition
National Instruments
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IEEE 488.2 Controller Chip
GPIB
+5 V
CPU(80186)
NAT9914
75160
DRQ
ACCRQ*
RD*
WR*
DBIN
WE*
INT0
INT*
RESET
DIO8
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
RESET*
OSC
AD15-0
D8
D7
D6
D5
D4
D3
D2
D1
CLK
74245
PE
D7-0
DEN
TE
TE
DT/R
Decode
74573
A3
A2
A1
D7-0
CONT*
DC TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
SC
CE*
ACCGR*
+5 V
A2
A1
A0
75162
A15-0
CPU(68000)
GPIB
NAT9914
75160
WE*
LDSN
R/WN
ASN
UDSN
IPL2-0
DBIN
+5 V
Interrupt
Control
DIO8
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
D8
D7
D6
D5
D4
D3
D2
D1
INT*
PE TE
Othe r
DTA CK Sources
DTACKN
TE
D7-0
D15-0
A23-0
Decode
CE*
A3
A2
A1
RESET
A2
A1
A0
RESET*
CONT*
DC TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
SC
+5 V
CLK
OSC
68440
RDYN
DTACKN
UDSN
LDSN
R/WN
ASN
A7-A1
UAS
A23/D15 - A8/D0
75162
ACCRQ*
ACCGR*
GND
74573
74573
OWN
74245
DBEN
DDIR
DRQ
ACK
A23-0
D15-0
Figure 13. Typical CPU Systems with NAT9914
National Instruments
Tel: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • ni.com/gpib
7
IEEE 488.2 Controller Chip
Figure 14. Mechanical Data 40-Pin Plastic DIP
Figure 15. Mechanical Data 44-Pin PLCC
8
National Instruments
Tel: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • ni.com/gpib
IEEE 488.2 Controller Chip
Figure 16. Mechanical 44-pin QFP.
Dimensions
A
A1
A2
D
D1
E
E1
L
e
b
θ
ddd
ccc
Tolerance
max.
–
+ 0.10/-0.05
± 0.25
± 0.10
± 0.25
± 0.10
+ 0.15/- 0.10
basic
± 0.05
–
–
max.
Value (in mm)
2.35
0.25 max.
2.00
17.20
14.00
17.20
14.00
0.88
1.00
0.35
0 to 7°
0.20 nom.
0.10
National Instruments
Tel: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • ni.com/gpib
9
IEEE 488.2 Controller Chip
Ordering Information
NAT9914BPD
NAT9914BPL
NAT9914BPQ
Part Number Legend
a
NAT
b
9914
c
B
d
P
e
D
a. Family name – NAT = 8-bit GPIB
Talker/Listener/Controller interface
b. Device number – 9914 = TI TMS9914A
pin-compatible part
c. Revision
d. Package material – P = plastic
e. Package type – D = Dual Inline Package (DIP)
L = Plastic Leaded Chip Carrier (PLCC)
Q = Quad Flatpack (QFP)
NAT9914 Programmer Reference Manual......visit ni.com
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