NT7702 240 Output LCD Segment/Common Driver Features ! Available in a single mode (240-bits shift register) or in a dual mode(120-bits shift register x 2) 1. Y1 → Y240 Single mode 2. Y240 → Y1 Single mode 3. Y1 → Y120, Y121 → Y240 Dual mode 4. Y240 → Y121, Y120 → Y1 Dual mode The above 4 shift directions are pin-selectable (Segment mode) ! Shift Clock frequency: 20 MHz (Max.) (VDD = 5 V ± 10%) ! Adopts a data bus system ! 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin ! Automatic transfer function with an enable signal ! Automatic counting function when in the chip select mode, causes the internal clock to be stopped by automatically counting 240 bits of input data (Both for segment mode and common mode) ! ! ! ! ! ! ! ! (Common mode) ! Shift clock frequency : 4.0 MHz (Max.) ! Built-in 240-bits bidirectional shift register (divisible into 120-bits x 2) Supply voltage for LCD driver: 15.0 to 30.0 V Number of LCD driver outputs: 240 Low output impedance Low power consumption Supply voltage for the logic system: +2.5 to +5.5 V COMS process Package: 272pin TCP (Tape Carrier Package) Not designed or rated as radiation hardened General Description The NT7702 is a 240-bit output segment/common driver LSI suitable for driving large scale dot matrix LCD panels using as PDA/personal computers/work stations. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The NT7702 is good as both a segment driver and as a common driver, and a low power consuming, high- precision LCD panel display can be assembled using the NT7702. In the segment mode, the data input is selected as 4bit parallel input mode or as 8bit parallel input mode by a mode (MD) pin. In the common mode, the data input/output pins are bi-directional and the four data shift directions are pin-selectable. Pin Configuration D U M M Y Y 2 4 0 Y 2 3 9 Y 2 3 8 Y 2 3 7 Y 2 3 6 272 271 270 269 268 Y 1 2 3 Y 1 2 2 Y 1 2 1 Y 1 2 0 Y 1 1 9 Y 1 1 8 155 154 153 152 151 150 Y 5 Y 4 Y 3 Y 2 Y 1 D U M M Y 37 36 35 34 33 NT7702 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D V V V V V V V S E D D D D D D D D X D L E F L M N V N V V V V V D U 0 0 1 4 5 S D / I 0 1 2 3 4 5 6 7 C I P I R / D C S C 5 4 1 0 0 U M L L 2 3 L S D C O K S O R S R 3 2 R R M M L L 2 P 1 R R M Y O Y F F 1 V1.0 NT7702 Pad Configuration 59 x x x 282 x 58 NT7702 Dummy Pad x x 283 Dummy Pad 1 44 Block Diagram V0R V12R V43R V5R Y1 Y2 Y239 Y240 V5L FR 240 Bits 4 Level Driver Level Shifter V43L V12L DISPOFF /240 V0L 240 Bits Level Shifter EIO1 /240 Active Control 240 Bits Line Latch/Shift Register EIO2 /16 LP /16 /16 /16 /16 8Bits2 Data Latch Control Logic XCK Data Latch Control L/R /8 MD SP Conversion & Data Control (4 to 8 or 8 to 8) S/C D0 D1 D2 D3 D4 D5 D6 D7 2 VDD VSS VSS 45 x x x ALK_R x x x 296 x ALK_L NT7702 Pin Description Pin No. Designation I/O Description 1, 2 V0L P Power supply for LCD driver 3 V12L P Power supply for LCD driver 4 V43L P Power supply for LCD driver 5 V5L P Power supply for LCD driver 6 VSS P Ground (0V), these two pads must be connected to each other 7 VDD P Power supply for the logic system (+2.5 to +5.5V) 8 S/C I Segment mode/common mode selection 9 EIO2 I/O 10 - 16 Input/output for chip select or data of the shift register D0 - D6 I Display data input for segment mode 17 D7 I Display data input for Segment mode/ Dual mode data input 18 XCK I Display data shift clock input for segment mode 19 DISPOFF I Control input for deselect output level 20 LP I Latch pulse input/shift clock input for the shift register 21 EIO1 I/O Input/output for chip select or data of the shift register 22 FR I AC-converting signal input for LCD driver waveform 23 L/R I Display data shift direction selection 24 MD I Mode selection input 25, 27 NC - No connected 26 VSS P Ground (0V), these two pads must be connected to each other 28 V5R P Power supply for LCD driver 29 V43R P Power supply for LCD driver 30 V12R P Power supply for LCD driver 31, 32 V0R P Power supply for LCD driver Y1 - Y240 O LCD driver output 33 - 272 3 NT7702 Pad Description Pad No. Designation I/O Description 1, 2 V5L P Power supply for LCD driver 3, 4 VSS P Ground (0V), these two pads must be connected to each other 5, 6 VDD P Power supply for the logic system (+2.5 to +5.5V) 7, 8 S/C I Segment mode/common mode selection 9, 10 EIO2 I/O 11, 12 - 23, 24 Input/output for chip select or data of the shift register D0 - D6 I Display data input for segment mode 25, 26 D7 I Display data input for Segment mode/ Dual mode data input 27, 28 XCK I Display data shift clock input for segment mode 29, 30 DISPOFF I Control input for deselect output level 31, 32 LP I Latch pulse input/shift clock input for the shift register 33, 34 EIO1 I/O Input/output for chip select or data of the shift register 35, 36 FR I AC-converting signal input for LCD driver waveform 37, 38 L/R I Display data shift direction selection 39, 40 MD I Mode selection input 41, 42 VSS P Ground (0V), these two pads must be connected to each other 43, 44 V5R P Power supply for LCD driver 45, 46 V43R P Power supply for LCD driver 47, 48 V12R P Power supply for LCD driver 49, 50 V0R P Power supply for LCD driver 51 - 290 Y1 - Y240 O LCD driver output 291, 292 V0L P Power supply for LCD driver 293, 294 V12L P Power supply for LCD driver 295, 296 V43L P Power supply for LCD driver 4 NT7702 Input / Output Circuits VDD I Input Signal Applicable Pins L/R, S/C, D0 - D6, DISPOFF , LP, FR, MD VSS Input Circuit (1) VDD I Input Signal Control Signal VSS VSS Input Circuit (2) 5 Applicable Pins D7, XCK NT7702 VDD Input Signal Control Signal VSS VDD VSS Output Signal I/O Control Signal Applicable Pins EIO1, EIO2 VSS Input / Output Circuit V0 V12 Control Signal 1 Control Signal 2 Control Signal 3 Control Signal 4 O Applicable Pins Y1 to Y240 V43 VSS LCD Driver Output circuit 6 V5 NT7702 Pad Description Segment mode Symbol Function VDD Logic system power supply pin connects to +2.5 to +5.5V VSS Ground pin connects to 0V VOR, VOL V12R, V12L V43R, V43L V5R, V5L D0 - D7 XCK Power supply pin for LCD driver voltage bias " Normally, the bias voltage used is set by a resistor divider " Ensure that the voltages are set such that VSS ≤ V5 < V43 < V12 < V0 " To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and Y240, externally connect ViR and ViL (I = 0, 12, 43, 5) Input pin for display data " In 4-bit parallel input mode, input data into the 4 pins D0 - D3. Connect D4 - D7 to VSS or VDD " In 8-bit parallel input mode, input data into the 8 pins D0 - D Clock input pin for taking display data " Data is read on the falling edge of the clock pulse LP Latch pulse input pin for display data " Data is latched on the falling edge of the clock pulse L/R Direction selection pin for reading display data " When set to VSS level "L", data is read sequentially from Y240 to Y1 " When set to VDD level "H", data is read sequentially from Y1 to Y240 Control input pin for output deselect level " The input signal is level-shifted from logic voltage level to LCD driver voltage level, and controls LCD driver circuit. " When set to VSS level “L”, the LCD driver output pins (Y1-Y240) are set to level V5 DISPOFF " While DISPOFF set to “L”, the contents of the line latch are reset, but read the display data in the data latch are read regardless of the condition of DISPOFF . When the DISPOFF function is canceled, the driver outputs deselect level (V12 or V43), then outputs the contents of the date latch onto the next falling edge of the LP. That time, if DISPOFF removal time can not keep regulation what is shown AC characteristics, can not output the reading data correctly FR AC signal input for LCD driving waveform " The input signal is level-shifted from the logic voltage level to the driver voltage level and controls the LCD driver circuit. " Normally inputs a frame inversion signal The LCD driver output pin’s output voltage level can be set to the line latch output signal and the FR signal MD Mode selection pin " When set to VSS level “L”, 8-bit parallel input mode is set " When set to VDD level “H", 4-bit parallel input mode is set 7 NT7702 Segment mode continued Symbol S/C Function Segment mode/common mode selection pin " When set to VDD level "H", segment mode is set " When set to VSS level "L", common mode is set EIO1, EIO2 Input/output pin for chip selection " When L/R input is at VSS level “L”, EIO1 is set for output, and EIO2 is set for input " When L/R input is at VDD level “H”, EIO1 is set for input, and EIO2 is set for output " During output, it is set to “H” while LP* XCK is “H” and after 240-bits of data have been read, it is set to “L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H” " During input, after the LP signal is input, the chip is selected while EI is set to “L”. After 240-bits of data have been read, the chip is deselected Y1 - Y240 LCD driver output pins These correspond directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and output Common mode Symbol Function VDD Logic system power supply pin connects to +2.5 to +5.5V VSS Ground pin connects to 0V V0R, V0L V12R, V12L V43R, V43L V5R, V5L Power supply pin for LCD driver voltage bias. " Normally, the bias voltage used is set by a resistor divider " Ensure the voltages are set such that VSS ≤ V5 <V43 < V12 < V0 To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and Y240, externally connect ViR and ViL (I = 0, 12, 43, 5) EIO1 Bi-directional shift register shift data input/output pin " Is an output pin when L/R is at VSS level “L” and an input pin when L/R is at VDD level “H” " When EIO1 is used as an input pin, it will be pulled-down " When EIO1 is used as an output pin, it won’t be pulled-down EIO2 Bi-directional shift register shift data input/output pin " Is an input pin when L/R is at VSS level “L” and an output pin when L/R is at VDD level “H” " When EIO2 is used as input pin, it will be pulled-down " When EIO2 is used as output pin, it won’t be pulled-down LP Bi-directional shift register shift clock pulse input pin " Data is shifted on the falling edge of the clock pulse L/R Bi-directional shift register shift direction selection pin " Data is shifted from Y240 to Y1 when it is set to VSS level “L”, and data is shifted from Y1 to Y240 when it is set to VDD level “H” 8 NT7702 Common mode continued Symbol Function DISPOFF Control input pin for output deselect level " The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the LCD driver circuit " When set to VSS level “L”, the LCD driver output pins (Y1-Y240) are set to level V5 " While set to “L”, the contents of the shift resister are reset and are not reading data. When the DISPOFF function is canceled, the driver outputs deselect level (V12 or V43), and the shift data is read on the falling edge of the LP. That time, if DISPOFF removal time can not keep regulation what is shown AC characteristics, the shift data is not reading correctly FR AC signal input for LCD driving waveform " The input signal is level-shifted from logic voltage level to the LCD driver voltage level, and it controls the LCD driver circuit " Normally, inputs a frame inversion signal The LCD driver output pin’s output voltage level can be set using the shift register output signal and the FR signal MD Mode selection pin " When set to VSS level “L”, Single Mode operation is selected. When set to VDD level “H”, Dual Mode operation is selected D7 Dual Mode data input pin " According to the data shift direction of the data shift register, data can be input starting from the 121st bit When the chip is used as Dual Mode, D7 will be pulled-down When the chip is used as Single Mode, D7 won’t be pulled-down S/C Segment mode/common mode selection pin " When set to VSS level “L”, common mode is set D0 - D6 Not used " Connect D0-D6 to VSS or VDD. Avoiding floating XCK Y1 - Y240 Not used " XCK is pull-down in common mode, so connect to VSS or open LCD driver output pins " These correspond directly Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or V5) is selected and output 9 NT7702 Functional Description 1. Block description 1.1 Active Control 1.5. Line Latch/Shift Register In the case of the segment mode, it controls the selection or deselection of the chip. Following a LP signal input, and after the select signal is input, a select signal is generated internally until 240 bits of data have been read in. Once data input has been completed, a select signal for cascade connection is output, and the ship is deselected. In the case of the segment mode, all 240 bits which have been read into the data latch, are simultaneously latched on to the falling edge of the LP signal, and output to the level shift block. In the case of the common mode, it shifts data from the data input pin on to the falling edge of the LP signal. In the case of the common mode, it controls the input/output data of the bi-directional pins. 1.6. Level Shifter 1.2. SP Conversion & Data Control The logic voltage signal is level-shifted to the LCD driver voltage level, and output to the driver block. In the case of the segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode into latch circuit, or keep input data which are 1 clock of XCK at 8-bit parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at a time. 1.7. 4-Level Driver It drives the LCD driver output pins from the line latch/shift register data, selecting one of 4 levels (V0, V12, V43, V5) based on the S/C, FR and DISPOFF signals. 1.3. Data Latch Control 1.8. Control Logic In the case of the segment mode, selects the state of the data latch, which reads in the data bus signals. The shift direction is controlled by the control logic and for every 16 bits of data read in, the selection signal shifts one bit, based on the state of the control circuit. Controls the operation of each block. In case of segment mode, when an LP signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission are controlled, 240 bits of data are read in, and the chip is deselected. 1.4. Data Latch In the case of the segment mode, latches the data on the data bus. The latched state of each LCD driver output pin is controlled by the control logic and the data latch control 240 bits of data are read in 20 sets of 8 bits. In the case of the common mode, it controls the direction of data shift. 10 NT7702 2. LCD Driver Output Voltage Level The relationship amongst the data bus signal, AC converted signal FR and LCD driver output voltage is as shown in the table below: 2.1. Segment Mode FR Latch Data DISPOFF Driver Output Voltage Level (Y1 - Y240) L L H V43 L H H V5 H L H V12 H H H V0 X X L V5 Here, VSS ≤ V5 < V43 < V12 < V0, H: VDD (+2.5 to +5.5V), L: VSS (0V), X: Don't care 2.2. Common Mode FR Latch Data DISPOFF Driver Output Voltage Level (Y1 - Y240) L L H V43 L H H V0 H L H V12 H H H V5 X X L V5 Here, VSS ≤ V5 < V43 < V12 < V0, H: VDD (+2.5 to +5.5V), L: VSS (0V), X: Don't care Note: There are two kinds of power supply (logic level voltage, LCD driver voltage) for the LCD driver. Please supply regular voltage which assigned by specification for each power pin. That time "Don't care" should be fixed to "H" or "L", avoiding floating. 11 NT7702 3. Relationship between the Display Data and Driver Output pins 3.1. Segment Mode: (a) 4-bit Parallel Mode MD H H L/R L H EIO1 Output Input EIO2 Input Output Data Input Number of Clock 60clock 59clock 58clcok ~ 3clock 2clock 1clock D0 Y1 Y5 Y9 ~ Y229 Y233 Y237 D1 Y2 Y6 Y10 ~ Y230 Y234 Y238 D2 Y3 Y7 Y11 ~ Y231 Y235 Y239 D3 Y4 Y8 Y12 ~ Y232 Y236 Y240 D0 Y240 Y236 Y232 ~ Y12 Y8 Y4 D1 Y239 Y235 Y231 ~ Y11 Y7 Y3 D2 Y238 Y234 Y230 ~ Y10 Y6 Y2 D3 Y237 Y233 Y229 ~ Y9 Y5 Y1 ~ 3clock 2clock 1clock (b) 8-bit Parallel Mode MD L L L/R L H EIO1 Output Input EIO2 Input Output Data Input Number of Clock 30clock 29clock 28clcok D0 Y1 Y9 Y17 ~ Y217 Y225 Y233 D1 Y2 Y10 Y18 ~ Y218 Y226 Y234 D2 Y3 Y11 Y19 ~ Y219 Y227 Y235 D3 Y4 Y12 Y20 ~ Y220 Y228 Y236 D4 Y5 Y13 Y21 ~ Y221 Y229 Y237 D5 Y6 Y14 Y22 ~ Y222 Y230 Y238 D6 Y7 Y15 Y23 ~ Y223 Y231 Y239 D7 Y8 Y16 Y24 ~ Y224 Y232 Y240 D0 Y240 Y232 Y224 ~ Y24 Y16 Y8 D1 Y239 Y231 Y223 ~ Y23 Y15 Y7 D2 Y238 Y230 Y222 ~ Y22 Y14 Y6 D3 Y237 Y229 Y221 ~ Y21 Y13 Y5 D4 Y236 Y228 Y220 ~ Y20 Y12 Y4 D5 Y235 Y227 Y219 ~ Y19 Y11 Y3 D6 Y234 Y226 Y218 ~ Y18 Y10 Y2 D7 Y233 Y225 Y217 ~ Y17 Y9 Y1 12 NT7702 3.2. Common Mode MD L/R Data Transfer Direction EIO1 EIO2 D7 L (Single) L (shift to left) Y240 to Y1 Output Input X H (shift to right) Y1 to Y240 Input Output X L (shift to left) Y240 to Y121 Y120 to Y1 Output Input Input H (shift to right) Y1 to Y120 Y121 to Y240 Input Output Input H (Dual) Here, L: VSS (0V), H: VDD (+2.5V to +5.5V), X: Don't care Note: "Don't care" should be fixed to "H" or "L", avoiding floating. 13 NT7702 4. Connection Examples of Segment Drivers 4.1. Case of L/R = “L” last data first data (data taking flow) Y240 ----------------------->Y1 Y240 ---------------------->Y1 Y240 ---------------------->Y1 EIO2 EIO2 EIO2 EIO1 EIO1 D0~D7 FR MD L/R LP D0~D7 FR LP MD L/R XCK D0~D7 FR MD LP XCK L/R XCK EIO1 XCK LP MD FR D0~D7 /8 VSS 4.2. Case of L/R = “H” VDD /8 D0~D7 FR MD LP L/R VSS L/R EIO1 EIO2 Y1 ---------------------->Y240 XCK LP MD FR D0~D7 XCK LP MD FR D0~D7 XCK LP MD FR D0~D7 XCK L/R EIO1 EIO2 Y1 ---------------------->Y240 EIO1 EIO2 Y1 ---------------------->Y240 (data taking flow) first data last data 14 NT7702 5. Timing waveform of 4-Device cascade Connection of Segment Drivers FR LP XCK First data D0~D7 n 1 2 Last data n 1 2 device A n 1 2 device B n 1 2 device C EI (device A) n 1 2 device D H L EO (device A) EO (device B) EO (device C) n: 4-bit parallel mode 60 8-bit parallel mode 30 15 NT7702 6. Connection Examples for Common Drivers Last First Y240 CS DISPOFF L/R MD EIO1 D7 EIO2 LP FR CS DISPOFF L/R D7 MD EIO1 Y1 FR Y1 EIO2 FR CS DISPOFF L/R MD EIO1 D7 EIO2 LP D Y240 Y1 LP Y240 LP VSS (VDD) VSS VSS DISPOFF CS FR Single Mode (Shifting towards the left) FR DISPOFF VSS VSS VSS (VDD) D LP D7 MD L/R DISPOFF FR LP D7 MD L/R DISPOFF FR LP D7 MD L/R DISPOFF FR LP EIO1 EIO2 EIO1 EIO2 EIO1 EIO2 Y1 Y240 Y1 Y240 Y1 Y240 Last First Single Mode (Sifting towards the right) 16 NT7702 Last2 DISPOFF D7 FR L/R MD EIO1 MD EIO2 L/R EIO1 D7 Y1 DISPOFF Y240 LP Y1 FR DISPOFF L/R MD Y121 Y120 D7 LP EIO2 FR EIO1 DISPOFF EIO2 L/R Y240 MD Y1 D7 Y240 LP D1 Last1 First2 FR First1 LP D2 VSS (VDD) VDD VSS DISPOFF FR Dual mode (Shifting towards the left) FR DISPOFF VSS VDD VSS (VDD) D2 D1 EIO1 EIO2 EIO1 Y1 Y240 Y1 First1 EIO2 Y120 Y121 Y240 Last1 First2 Dual mode (Shifting towards the right) 17 LP LP D7 MD L/R DISPOFF FR LP D7 MD L/R DISPOFF FR LP EIO1 EIO2 Y1 Y240 Last2 NT7702 7. Precaution Be careful when connecting or disconnecting the power This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occar, if a voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The details are as follows: ! ! When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power. We recommend that you connect a serial resistor (50-100 Ω) or fuse to the LCD driver power V0 of the system as a current limiting device. Also, set a suitable value of the resistor in consideration of LCD display grade. In addition, when connecting the logic power supply, the logic condition of this LSI inside is insecure. Therefore connect the LCD driver power supply after resetting the logic condition of this LSI inside to DISPOFF function. After that, the DISPOFF cancel the function after the LCD driver power supply has become stable. Furthermore, when disconnecting the power, set the LCD driver output pins to level V5 on the DISPOFF function. After that, disconnect the logic system power after disconnecting the LCD driver power. When connecting the power supply, follow the recommended sequence shown. VDD VDD VSS VDD DISPOFF VSS V0 V0 VSS 18 NT7702 Absolute Maximum Rating* *Comments DC Supply Voltage VDD . . . . . . . . . . . . -0.3V to +7.0V Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Supply Voltage V0 . . . . . . . . . . . . . -0.3V to +30V Input Voltage . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Operating Ambient Temperature . . . . -30°C to +85°C Storage Temperature . . . . . . . . . . . . .-45°C to +125°C Electrical Characteristics DC Characteristics Segment Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30 V, and TA = -30 to +85°C, unless otherwise noted) Parameter Symbol Min. Typ. Max. Unit Operating Voltage 1 VDD 2.5 - 5.5 V Operating Voltage 2 V0 15 - 30 V Input high voltage VIH 0.8 VDD - - V Input low voltage VIL - - 0.2 VDD V D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins Output high voltage VOH VDD - 0.4 - - V EIO1, EIO2 pins, IOH = -0.4mA Output low voltage VOL - - +0.4 V EIO1, EIO2 pins, IOL = +0.4mA Input leakage current 1 IIH - - +1 µA D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins, VI = VDD Input leakage current 2 IIL - - -1 µA D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins, VI = VSS - 1.5 2.0 Output resistance RON - 2.0 2.5 Condition V0 = +30.0V kΩ V0 = +20.0V Stand-by current ISB - - 10 µA VSS pin, Note 1 Consumed current (1) (Deselection) IDD1 - - 2 mA VDD pin, Note 2 Consumed current (2) (Selection) IDD2 - - 12 mA VDD pin, Note 3 I0 - - 1.5 mA V0 pin, Note 4 Consumed current Note: 1. VDD = +5.0V, V0 = +30V, VI = VSS 2. VDD = +5.0V, V0 = +30V, fXCK = 20MHz, No-load, EI = VDD The input data is turned over by the data taking clock (4-bit Parallel input mode) 3. VDD = +5.0V, V0 = +30V, fXCK = 20MHz, No-load. EI = VSS The input data is turned over by the data taking clock (4-bit parallel input mode) 4. VDD = +5.0V, V0 = +30V, fXCK = 20MHz, fLP = 41.6kHz. fFR = 80 Hz, No-load The input data is turned over by the data taking clock (4-bit parallel-input mode) 19 Y1 - Y240 pins, ∆V O N = 0.5V NT7702 Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30 V, and TA = -30 to +85°C, unless otherwise noted) Parameter Symbol Min. Typ. Max. Unit Operating Voltage VDD 2.5 - 5.5 V Operating Voltage V0 15 - 30 V Input high voltage VIH 0.8 VDD - - V Input low voltage VIL - - 0.2 VDD V D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins Output high voltage VOH VDD - 0.4 - - V EIO1, EIO2 pins, IOH = -0.4mA Output low voltage VOL - - +0.4 V EIO1, EIO2 pins, IOL = +0.4mA Input leakage current 1 IIH - - +10.0 µA D0 - 6, LP, L/R, FR, MD, S/C and DISPOFF pins, VI = VDD Input leakage current 2 IIL - - -10.0 µA D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins, VI = VSS Input pull down current IPD - - 100 µA XCK, EIO1, EIO2, D7 pins - 1.5 2.0 Output resistance RON - 2.0 2.5 Condition V0 = +30.0V kΩ V0 = +20.0V Stand-by current ISB - - 75 µA VSS pin, Note 1 Consumed current (1) IDD - - 120 µA VDD pin, Note 2 Consumed current (2) I0 - - 240 µA V0 pin, Note 2 Note: 1. VDD = +5.0V, V0 = +30.0V, VI = VSS 2. VDD = +5.0V, V0 = +30.0V, fLP = 41.6KHz, fFR = 80Hz, case of 1/480 duty operation, No-load 20 Y1 - Y240 pins, ∆V O N = 0.5V NT7702 AC Characteristics Segment Mode 1 (VSS = V5 = 0V, VDD = 4.5 - 5.5V, V0 = 15 to 30V, and TA = -30 to +85°C, unless otherwise noted) Parameter Symbol Min. Typ. Shift clock period tWCK 50 - ns Shift clock "H" pulse width tWCKH 15 - ns Shift clock "L" pulse width tWCKL 15 - ns Data setup time tDS 10 - ns Data hole time tDH 12 - ns tWLPH 15 - ns Shift clock rise to Latch pulse rise time tLD 0 - ns Shift clock fall to Latch pulse fall time tSL 30 - ns Latch pulse rise to Shift clock rise time tLS 25 - ns Latch pulse fall to Shift clock rise time tLH 25 - ns Latch pulse "H" pulse width Max. Unit Condition tr, tf 10ns, Note 1 Input signal rise time tr - 50 ns Note 2 Input signal fall time tf - 50 ns Note 2 Enable setup time tS 10 - ns DISPOFF Removal time tSD 100 - ns tWDL 1.2 - µs DISPOFF enable pulse width Output delay time (1) tD - 30 ns CL = 15pF Output delay time (2) tpd1, tpd2 - 1.2 µs CL = 15pF Output delay time (3) tpd3 - 1.2 µs CL = 15pF Note 1. Take the cascade connection into consideration. 2. (tCK-tWCKII-twckl)/2 is the maximum in the case of high speed operation. 21 NT7702 Segment Mode 2 (VSS = V5 = 0V, VDD = 3.0 - 4.5V, V0 = 15 to 30V, and TA = -30 to +85°C, unless otherwise noted) Parameter Symbol Min. Typ. Shift clock period tWCK 66 - ns Shift clock "H" pulse width tWCKH 23 - ns Shift clock "L" pulse width tWCKL 23 - ns Data setup time tDS 15 - ns Data hole time tDH 23 - ns tWLPH 30 - ns Shift clock rise to Latch pulse rise time tLD 0 - ns Shift clock fall to Latch pulse fall time tSL 50 - ns Latch pulse rise to Shift clock rise time tLS 30 - ns Latch pulse fall to Shift clock fall time tLH 30 - ns Latch pulse "H" pulse width Max. Unit Condition tr, tf 10ns, Note 1 Input signal rise time tr - 50 ns Note 2 Input signal fall time tf - 50 ns Note 2 Enable setup time tS 15 - ns DISPOFF Removal time tSD 100 - ns tWDL 1.2 - µs DISPOFF enable pulse width Output delay time (1) tD - 41 ns CL = 15pF Output delay time (2) tpd1, tpd2 - 1.2 µs CL = 15pF Output delay time (3) tpd3 - 1.2 µs CL = 15pF Note 1. Take the cascade connection into consideration. 2. (tCK-tWCKII-tWCKL)/2 is the maximum in the case of high speed operation. 22 NT7702 Segment Mode 3 (VSS = V5 = 0V, VDD = 2.5 - 3.0V, V0 = 15 to 30V, and TA = -30 to +85°C, unless otherwise noted) Parameter Symbol Min. Typ. Shift clock period tWCK 82 - ns Shift clock "H" pulse width tWCKH 28 - ns Shift clock "L" pulse width tWCKL 28 - ns Data setup time tDS 20 - ns Data hole time tDH 23 - ns tWLPH 30 - ns Shift clock rise to Latch pulse rise time tLD 0 - ns Shift clock fall to Latch pulse fall time tSL 65 - ns Latch pulse rise to Shift clock rise time tLS 30 - ns Latch pulse fall to Shift clock fall time tLH 30 - ns Latch pulse "H" pulse width Max. Unit Condition tr, tf 10ns, Note 1 Input signal rise time tr - 50 ns Note 2 Input signal fall time tf - 50 ns Note 2 Enable setup time tS 15 - ns DISPOFF Removal time tSD 100 - ns tWDL 1.2 - µs DISPOFF enable pulse width Output delay time (1) tD - 57 ns CL = 15pF Output delay time (2) tpd1, tpd2 - 1.2 µs CL = 15pF Output delay time (3) tpd3 - 1.2 µs CL = 15pF Note 1. Take the cascade connection into consideration. 2. (tCK-tWCKII-tWCKL)/2 is the maximum in the case of high speed operation. 23 NT7702 Timing waveform of the Segment Mode tWLPH LP tLD tSL tLH tLS tWCKH tWCKL XCK D0 - D7 tr tr tWCK tDS LAST DATA tDH TOP DATA tWDL tSD DISPOFF LP 1 2 n XCK tS EI tD EO n: 4-bit parallel mode 60 8-bit parallel mode 30 FR tpd1 LP tpd2 DISPOFF tpd3 Y1 - Y240 24 NT7702 Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30V and TA = -30 to +85°C, unless otherwise noted) Parameter Symbol Min. Typ. Max. Unit Condition Shift clock period tWLP 250 - - ns tr, tf 20ns 15 - - ns VDD = +5.0V 10% Shift clock "H" pulse width tWLPH 30 - - ns VDD = +2.5 - +4.5V Data setup time tSU 30 - - ns Data hole time tH 50 - - ns Input signal rise time tr - 50 ns Input signal fall time tf - 50 ns tSD 100 - - ns tWDL 1.2 - - µs Output delay time (1) tDL - - 200 ns CL = 15pF Output delay time (2) tpd1, tpd2 - - 1.2 µs CL = 15pF Output delay time (3) tpd3 - - 1.2 µs CL = 15pF DISPOFF Removal time DISPOFF enable pulse width 25 NT7702 Timing Characteristics of Common Mode tWLP LP tr tWLPH tSU tf tH EIO2 (DI7) tDL EIO1 tWDL tSD DISPOFF FR tpd1 LP tpd2 DISPOFF tpd3 Y1 - Y240 26 NT7702 Application Circuit (for reference only) SEG640 SEG639 EIO1 Y1~Y240 MD FR S/C L/R LP DISPOFF XCK D0~D7 EIO2 EIO1 Y1~Y240 MD FR S/C L/R DISPOFF 1920*480 DOT MATRIX LCD PANEL D0~D7 NT7702*4 LP EIO2 XCK EIO1 Y1~Y240 MD FR S/C LP L/R DISPOFF XCK D0~D7 EIO2 EIO1 Y1~Y240 MD SEG3 SEG2 FR S/C SEG1 XCK D0~D7 EIO2 XCK EIO2 LP DISPOFF D0~D7 L/R Y1~Y240 FR S/C MD EIO1 XCK EIO2 LP DISPOFF D0~D7 L/R Y1~Y240 FR S/C EIO1 XCK EIO2 LP DISPOFF L/R D0~D7 FR S/C MD NT7702*3 L/R DISPOFF /8 EIO1 LP C O M 4 8 0 C O M 4 7 9 C O M 3 MD C O M 2 Y1~Y240 C O M 1 /5 /5 VEE V0 R V1 (n-4)R V2 R V3 R V4 V5 VDD VSS 27 LCD controller XD0~XD7 XCK LP DISPOFF FR YD (case of 1/n bias) 50~100Ω /8 R NT7702 Bonding Diagram 11720um 59 x x x x 282 283 58 Dummy Pad x x NT7702 Y X (0,0) Dummy Pad 1030um 45 x x x x x 296 ALK_R x x ALK_L 1 44 Pad Location Pad No. Designation X Y Pad No. Designation X Y 1 V5L -5440 -440 31 LP 1440 -440 2 V5L -5280 -440 32 LP 1600 -440 3 VSS -5120 -440 33 EIO1 1760 -440 4 VSS -4960 -440 34 EIO1 1920 -440 5 VDD -4800 -440 35 FR 2080 -440 6 VDD -4640 -440 36 FR 2240 -440 7 SC -2400 -440 37 L/R 2400 -440 8 SC -2240 -440 38 L/R 2560 -440 9 EIO2 -2080 -440 39 MD 2720 -440 10 EIO2 -1920 -440 40 MD 2880 -440 11 D0 -1760 -440 41 VSS 4960 -440 12 D0 -1600 -440 42 VSS 5120 -440 13 D1 -1440 -440 43 V5R 5280 -440 14 D1 -1280 -440 44 V5R 5440 -440 15 D2 -1120 -440 45 V43R 5779 -300 16 D2 -960 -440 46 V43R 5779 -250 17 D3 -800 -440 47 V12R 5779 -200 18 D3 -640 -440 48 V12R 5779 -150 19 D4 -480 -440 49 V0R 5779 -100 20 D4 -320 -440 50 V0R 5779 -50 21 D5 -160 -440 51 Y1 5779 0 22 D5 0 -440 52 Y2 5779 50 23 D6 160 -440 53 Y3 5779 100 24 D6 320 -440 54 Y4 5779 150 25 D7 480 -440 55 Y5 5779 200 26 D7 640 -440 56 Y6 5779 250 27 XCK 800 -440 57 Y7 5779 300 28 XCK 960 -440 58 Y8 5779 350 29 DISPOFF 1120 -440 59 Y9 5575 440 30 DISPOFF 1280 -440 60 Y10 5525 440 28 NT7702 Pad Location (continued) Pad No. Designation X Y Pad No. Designation X Y 61 Y11 5475 440 101 Y51 3475 440 62 Y12 5425 440 102 Y52 3425 440 63 Y13 5375 440 103 Y53 3375 440 64 Y14 5325 440 104 Y54 3325 440 65 Y15 5275 440 105 Y55 3275 440 66 Y16 5225 440 106 Y56 3225 440 67 Y17 5175 440 107 Y57 3175 440 68 Y18 5125 440 108 Y58 3125 440 69 Y19 5075 440 109 Y59 3075 440 70 Y20 5025 440 110 Y60 3025 440 71 Y21 4975 440 111 Y61 2975 440 72 Y22 4925 440 112 Y62 2925 440 73 Y23 4875 440 113 Y63 2875 440 74 Y24 4825 440 114 Y64 2825 440 75 Y25 4775 440 115 Y65 2775 440 76 Y26 4725 440 116 Y66 2725 440 77 Y27 4675 440 117 Y67 2675 440 78 Y28 4625 440 118 Y68 2625 440 79 Y29 4575 440 119 Y69 2575 440 80 Y30 4525 440 120 Y70 2525 440 81 Y31 4475 440 121 Y71 2475 440 82 Y32 4425 440 122 Y72 2425 440 83 Y33 4375 440 123 Y73 2375 440 84 Y34 4325 440 124 Y74 2325 440 85 Y35 4275 440 125 Y75 2275 440 86 Y36 4225 440 126 Y76 2225 440 87 Y37 4175 440 127 Y77 2175 440 88 Y38 4125 440 128 Y78 2125 440 89 Y39 4075 440 129 Y79 2075 440 90 Y40 4025 440 130 Y80 2025 440 91 Y41 3975 440 131 Y81 1975 440 92 Y42 3925 440 132 Y82 1925 440 93 Y43 3875 440 133 Y83 1875 440 94 Y44 3825 440 134 Y84 1825 440 95 Y45 3775 440 135 Y85 1775 440 96 Y46 3725 440 136 Y86 1725 440 97 Y47 3675 440 137 Y87 1675 440 98 Y48 3625 440 139 Y88 1625 440 99 Y49 3575 440 139 Y89 1575 440 100 Y50 3525 440 140 Y90 1525 440 29 NT7702 Pad Location (continued) Pad No. Designation X Y Pad No. Designation X Y 141 Y91 1475 440 181 Y131 -525 440 142 Y92 1425 440 182 Y132 -575 440 143 Y93 1375 440 183 Y133 -625 440 144 Y94 1325 440 184 Y134 -675 440 145 Y95 1275 440 185 Y135 -725 440 146 Y96 1225 440 186 Y136 -775 440 147 Y97 1175 440 187 Y137 -825 440 148 Y98 1125 440 188 Y138 -875 440 149 Y99 1075 440 189 Y139 -925 440 150 Y100 1025 440 190 Y140 -975 440 151 Y101 975 440 191 Y141 -1025 440 152 Y102 925 440 192 Y142 -1075 440 153 Y103 875 440 193 Y143 -1125 440 154 Y104 825 440 194 Y144 -1175 440 155 Y105 775 440 195 Y145 -1225 440 156 Y106 725 440 196 Y146 -1275 440 157 Y107 675 440 197 Y147 -1325 440 158 Y108 625 440 198 Y148 -1375 440 159 Y109 575 440 199 Y149 -1425 440 160 Y110 525 440 200 Y150 -1475 440 161 Y111 475 440 201 Y151 -1525 440 162 Y112 425 440 202 Y152 -1575 440 163 Y113 375 440 203 Y153 -1625 440 164 Y114 325 440 204 Y154 -1675 440 165 Y115 275 440 205 Y155 -1725 440 166 Y116 225 440 206 Y156 -1775 440 167 Y117 175 440 207 Y157 -1825 440 168 Y118 125 440 208 Y158 -1875 440 169 Y119 75 440 209 Y159 -1925 440 170 Y120 25 440 210 Y160 -1975 440 171 Y121 -25 440 211 Y161 -2025 440 172 Y122 -75 440 212 Y162 -2075 440 173 Y123 -125 440 213 Y163 -2125 440 174 Y124 -175 440 214 Y164 -2175 440 175 Y125 -225 440 215 Y165 -2225 440 176 Y126 -275 440 216 Y166 -2275 440 177 Y127 -325 440 217 Y167 -2325 440 178 Y128 -375 440 218 Y168 -2375 440 179 Y129 -425 440 219 Y169 -2425 440 180 Y130 -475 440 220 Y170 -2475 440 30 NT7702 Pad Location (continued) Pad No. Designation X Y Pad No. Designation X Y 221 Y171 -2525 440 260 Y210 -4475 440 222 Y172 -2575 440 261 Y211 -4525 440 223 Y173 -2625 440 262 Y212 -4575 440 224 Y174 -2675 440 263 Y213 -4625 440 225 Y175 -2725 440 264 Y214 -4675 440 226 Y176 -2775 440 265 Y215 -4725 440 227 Y177 -2825 440 266 Y216 -4775 440 228 Y178 -2875 440 267 Y217 -4825 440 229 Y179 -2925 440 268 Y218 -4875 440 230 Y180 -2975 440 269 Y219 -4925 440 231 Y181 -3025 440 270 Y220 -4975 440 232 Y182 -3075 440 271 Y221 -5025 440 233 Y183 -3125 440 272 Y222 -5075 440 234 Y184 -3175 440 273 Y223 -5125 440 235 Y185 -3225 440 274 Y224 -5175 440 236 Y186 -3275 440 275 Y225 -5225 440 237 Y187 -3325 440 276 Y226 -5275 440 238 Y188 -3375 440 277 Y227 -5325 440 239 Y189 -3425 440 278 Y228 -5375 440 240 Y190 -3475 440 279 Y229 -5425 440 241 Y191 -3525 440 280 Y230 -5475 440 242 Y192 -3575 440 281 Y231 -5525 440 243 Y193 -3625 440 282 Y232 -5575 440 244 Y194 -3675 440 283 Y233 -5779 350 245 Y195 -3725 440 284 Y234 -5779 300 246 Y196 -3775 440 285 Y235 -5779 250 247 Y197 -3825 440 286 Y236 -5779 200 248 Y198 -3875 440 287 Y237 -5779 150 249 Y199 -3925 440 288 Y238 -5779 100 250 Y200 -3975 440 289 Y239 -5779 50 251 Y201 -4025 440 290 Y240 -5779 0 252 Y202 -4075 440 291 V0L -5779 -50 253 Y203 -4125 440 292 V0L -5779 -100 254 Y204 -4175 440 293 V12L -5779 -150 255 Y205 -4225 440 294 V12L -5779 -200 256 Y206 -4275 440 295 V43L -5779 -250 257 Y207 -4325 440 296 V43L -5779 -300 258 Y208 -4375 440 ALK_R 5668 -323 259 Y209 -4425 440 ALK_L -5668 -323 31 NT7702 Dummy Pad Location (Total: 35 pad) NO X Y NO X Y NO X Y NO X Y 1 -5600 -440 10 -3200 -440 19 3680 -440 28 5779 -410 2 -4480 -440 11 -3040 -440 20 3840 -440 29 5779 -350 3 -4320 -440 12 -2880 -440 21 4000 -440 30 5779 410 4 -4160 -440 13 -2720 -440 22 4160 -440 31 5635 440 5 -4000 -440 14 -2560 -440 23 4320 -440 32 -5635 440 6 -3840 -440 15 3040 -440 24 4480 -440 33 -5779 410 7 -3680 -440 16 3200 -440 25 4640 -440 34 -5779 -350 8 -3520 -440 17 3360 -440 26 4800 -440 35 -5779 -410 9 -3360 -440 18 3520 -440 27 5600 -440 32 NT7702 Package Information A1 D3 D3 A2 A2 C2 C1 m1 NT7702 m2 J m1 m1 m2 D1 14nm2 r D3 D1 m2 r m1 H D3 C1 n m1 D3 m1 C1 A1 D1 224m2n D3 m1 n C2 B 71m1n D2 14nm2 H n n J Chip Outline Dimensions C1 B unit: um Symbol Dimensions in um Symbol Dimensions in um A1 225 D3 60 A2 81 m1 57 B 260 m2 37 C1 105 n 59 C2 75 r 35 D1 50 H 117 D2 160 J 111 33 NT7702 TCP Pin Layout DUMMY Y1 33 Y2 34 Y3 35 Y4 36 Y5 37 Y118 150 Y119 151 Y120 152 Y121 153 Y122 154 Y123 155 NT7702 DUMMY 32 V0R 31 V0R 30 V12R 29 V43R 28 V5R 27 NC 26 VSS 25 NC 24 MD 23 L/R 22 FR 21 EIO1 20 LP 19 DISPOFF 18 XCK 17 D7 16 D6 15 D5 14 D4 13 D3 12 D2 11 D1 10 D0 9 EIO2 8 S/C 7 VDD 6 VSS 5 V5L 4 V43L 3 V12L 2 V0L 1 V0L DUMMY Y236 268 Y237 269 Y238 270 Y239 271 Y240 272 DUMMY (Copper Side View) 34 NT7702 External view of TCP pins 35 NT7702 Cautions concerning storage: 1. When storing the product, it is recommended that it be left in its shipping package. After the seal of the packing bag has been broken, store the products in a nitrogen atmosphere. 2. Storage conditions : Storage state Storage conditions Temperature: 5 to 30; humidity: 80%RH or less. unopened (less than 90 days) After seal of broken (less than 30 days) Room temperature, dry nitrogen atmosphere 3. Don't store in a location exposed to corrosive gas or excessive dust. 4. Don't store in a location exposed to direct sunlight of subject to sharp changes in temperature. 5. Don't store the product such that it is subjected to an excessive load weight, such as by stacking. 6. Deterioration of the plating may occur after long-term storage, so special care is required. It is recommended that the products be inspected before use. 36 NT7702 Tray Information f Y e 5*33 X W1 W2 T2 T1 X SECTION Y-Y c d Y g h W1 W2 a b e g f h T2 T1 SECTION X-X Symbol Dimensions in mm Symbol Dimensions in mm a 1.46 g 0.84 b 2.04 h 4.20 c 12.14 W1 76.0 d 13.35 W2 68.0 e 1.60 T1 71.0 f 1.40 T2 68.3 37 NT7702 Ordering Information Part No. NT7702H-BDT NT7702H-TABF4 Package Au bump on chip tray TCP Form 38