ETC PEEL16V8P-25

Commercial
PEEL16V8 -15/-25
CMOS Programmable Electrically Erasable Logic
Features
■ ICC
 45mA typical ICC
■ Compatible with Popular 16V8 Devices
 16V8 socket and function compatible
 Programs with standard 16V8 JEDEC file
 20-pin DIP and PLCC packages
■ Development/Programmer Support
 Third party software and programmers
 ICT PLACE Development Software and
PDS-3 programmer
 Automatic programmer translation and
JEDEC file translation software available
for the most popular PAL devices
■ CMOS Electrically Erasable Technology
 Superior factory testing
 Reprogrammable in plastic package
 Reduces retrofit and development costs
■ Application Versatility
 Replaces random logic
 Super-sets standard 20-pin PLDs (PALs)
General Description
The PEEL16V8 is a Programmable Electrically
Erasable Logic (PEEL) device providing an attractive alternative to ordinary PLDs. The PEEL16V8
offers the performance, flexibility, ease-of-design
and production practicality needed by logic designers today. The PEEL16V8 is available in 20-pin DIP
and PLCC packages (see Figure 1) with speeds
ranging from 15ns to 25ns and power consumption
less than 45mA. EE-reprogrammability provides the
convenience of instant reprogramming for development and a reusable production inventory minimizing the impact of programming changes or errors.
EE-reprogrammability also improves factory testability, thus ensuring the highest quality possible.
The PEEL16V8 architecture allows it to replace
standard 20-pin PAL devices. (See Figure 2). ICT’s
PEEL16V8 can be programmed with any existing
16V8 JEDEC file. Some programmers also allow
the PEEL16V8 to be programmed directly from PAL
16L8, 16R4, 16R6 and 16R8 JEDEC files. Additional development and programming support for
the PEEL16V8 is provided by popular third-party
programmers and development software. ICT also
offers free PLACE development software and a lowcost development system (PDS-3).
Pin Configuration (Figure 1)
I/CLK
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OE
I
I
I
I
I
I
I
I
GND
Block Diagram (Figure 2)
CLK
I/CLK
PEEL
"AND"
ARRAY
64 TERMS
X
32 INPUTS
DIP
I/OE
I/OE
PLCC
3-7
MACRO
CELL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PEEL 16V8
Functional Description
The PEEL16V8 implements logic functions as sumof-products expressions in a programmableAND/fixed-OR logic array. User-defined functions
are created by programming the connections of input signals into the array. User-configurable output
structures in the form of macrocells further increase
logic flexibility.
Architecture Overview
The PEEL16V8 features ten dedicated input pins
and eight I/O pins, which allow a total of up to 16
inputs and 8 outputs for creating logic functions. At
the core of the device is a programmable electrically-erasable AND array which drives a fixed OR
array. With this structure the PEEL16V8 can implement up to 8 sum-of-products logic expressions.
Associated with each of the eight OR functions is a
macrocell which can be independently programmed
to one of up to four different basic configurations.
The programmable macrocells allow each I/O to
create sequential or combinatorial logic functions of
active-high or active-low polarity, while providing two
possible feedback paths into the array.
Three different device modes, Simple, Complex and
Registered, support various user configurations. In
Simple mode, a macrocell can be configured for
combinatorial function with the output buffer permanently enabled, or the output buffer can be disabled
and the I/O pin used as a dedicated input. In Complex mode, a macrocell is configured for combinatorial function with the output buffer enable controlled by a product term. In Registered mode, a macrocell can be configured for registered operation with
the register clock and output buffer enable controlled directly from pins, or can be configured for combinatorial function with the output buffer enable controlled by a product term. In most cases, the device
mode is set automatically by the development software based on the features specified in the design.
16 additional lines carry the true and complement
of 8 macrocell feedback signals or inputs from I/O
pins or the clock/OE pins
64 product terms:
56 product terms (arranged in 8 groups of 7) form
sum-of-product functions for macrocell combinatorial or registered logic
8 product terms (arranged 1 per macrocell) add an
additional product term for macrocell sum-of-products functions or I/O pin output enable control
At each input-line/product-term intersection there is
an EEPROM memory cell which determines
whether or not there is a logical connection at that
intersection. Each product term is essentially a 32input AND gate. A product term which is connected to
both the true and complement of an input signal will
always be FALSE and thus will not affect the OR function that it drives. When all the connections on a product
term are opened, that term will always be TRUE.
When programming the PEEL16V8, the device programmer first performs a bulk erase to remove the
previous pattern. The erase cycle opens every logical
connection in the array. The device is configured to
perform the user-defined function by programming
selected connections in the AND array. (Note that
PEEL device programmers automatically program all
of the connections on unused product terms so that
they will have no effect on the output function.)
Table 1. PEEL16V8/PAL Device Compatibility
The three device modes support designs created
explicitly for the PEEL16V8, as well as designs created originally for popular PAL devices such as the
16R4, 16R8 and 16L8. Table 1 shows the device
mode used to emulate the various PALs. Design
conversion into the 16V8 is accommodated by
JEDEC-to-JEDEC translators available from ICT, as
well as several programmers which can read the
original PAL JEDEC file and automatically program
the 16V8 to perform the same function.
AND/OR Logic Array
The programmable AND array of the PEEL16V8 is
formed by input lines intersecting product terms.
The input lines and product terms are used as follows:
32 input lines:
16 input lines carry the true and complement of
the signals applied to the 8 dedicated input pins
3-8
PAL Architecture
Compatibility
Device Mode
10H8
10L8
10P8
12H6
12L6
12P6
14H4
14L4
14P4
16H2
16HD8
16L2
16LD8
16P2
16H8
16L8
16P8
16R4
16R6
PEEL16V8
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Complex
Complex
Complex
Registered
Registered
PEEL 16V8
16R8
16RP4
16RP6
14RP8
Registered
Registered
Registered
Registered
Programmable Macrocell
The macrocell provides complete control over the
architecture of each output. The ability to configure
each output independently permits users to tailor
the configuration of the PEEL16V8 to the precise
requirements of their designs.
Simple Mode
In Simple mode, all eight product terms feed the OR
array which can generate a purely combinatorial
function for the output pin. The programmable output polarity selector allows active-high or active-low
logic, eliminating the need for external inverters.
For output functions, the buffer can be permanently
enabled. Feedback into the array is available on all
macrocell I/O pins, except for pins 15 and 16. Figure
1 Simple Mode
Active Low Output
Macrocell Architecture
Each macrocell consists of an OR function, a D-type
flip-flop, an output polarity selector, and a programmable feedback path. Four EEPROM architecture
bits MS0, MS1, OP and RC control the configuration
of each macrocell. Bits MS0 and MS1 are global,
and select between Simple, Complex and Registered mode for the whole device. Bits OP and RC
are local for each macrocell; bit OP controls the
output polarity and bit RC selects between registered and combinatorial operation and also specifies the feedback path. Table 2 shows the architecture bit settings for each possible configuration.
Equivalent circuits for the possible macrocell configurations are illustrated in Figures 3, 4 and 5.
When creating a PEEL device design, the desired
macrocell configuration generally is specified explicitly in the design file. When the design is assembled
or compiled, the macrocell configuration bits are
defined in the last lines of the JEDEC programming
file.
2
VCC
3
Simple Mode
Active High Output
VCC
Simple Mode
I/O Pin Input
Figure 3. Macrocell Configurations for the Simple
Mode of the PEEL16V8
Table 2. PEEL16V8 Device Mode/Macrocell Architecture Configuration Bits
Config.
Mode
#
Architecture Bits
MS0
MS1
OP
RC
Function
Polarity
Feedback
1
Simple
1
0
0
0
Combinatorial
Active Low
I/O Pin
2
Simple
1
0
1
0
Combinatorial
Active High
I/O Pin
3
Simple
1
0
X
1
None
None
I/O Pin
1
Complex
1
1
0
1
Combinatorial
Active Low
I/O Pin
2
Complex
1
1
1
1
Combinatorial
Active High
I/O Pin
1
Registered
0
1
0
0
Registered
Active Low
Registered
2
Registered
0
1
1
0
Registered
Active High
Registered
3
Registered
0
1
0
1
Combinatorial
Active Low
I/O Pin
4
Registered
0
1
1
1
Combinatorial
Active High
I/O Pin
3-9
PEEL 16V8
6 shows the logic array of the PEEL16V8 configured
in Simple mode.
Simple mode also provides the option of configuring
an I/O pin as a dedicated input. In this case, the
output buffer is permanently disabled and the I/O
pin feedback is used to bring the input signal from
the pin into the logic array. This option is available
for all I/O pins except pins 15 and 16.
1
PRODUCT T ERM
2
2 Registered Mode
Active High Registered Output
OE PIN
OE PIN
D
Q
D
Q
3
Registered Mode
Active Low Combinatorial Output
PRODUCT TERM
Q
Q
CLK PIN
Complex Mode
In Complex mode, seven product terms feed the OR
array which can generate a purely combinatorial
1 Complex Mode
Active L ow Output
Registered Mode
Active Low Registered Output
CLK PIN
4
Registered Mode
Active High Combinatorial Output
PRODUCT TERM
Complex Mode
Active High Output
Figure 5. Macrocell Configurations for the Registered Mode of the PEEL16V8
PRODUCT T ERM
Figure 4. Macrocell Configurations for the Complex Mode of the PEEL16V8
function for the output pin. The programmable output polarity selector provides active-high or activelow logic, eliminating the need for external inverters.
The output buffer is controlled by the eighth product
term, allowing the macrocell to be configured for
input, output or bidirectional functions. Feedback
into the array for input or bidirectional functions is
available on all pins except 12 and 19. Figure 7
shows the logic array of the PEEL16V8 configured
in Complex mode.
Registered Mode
In Registered mode, eight product terms are provided to the OR array for registered functions. The
programmable output polarity selector provides active-high or active-low logic, eliminating the need for
external inverters. (Note, however, that PEEL16V8
registers power-up reset and so before the first
clock arrives, the output at the pin will be low if the
user has selected active-high logic and high if the
user has selected active-low logic.) For registered
functions, the output buffer enable is controlled directly from the /OE control pin. Feedback into the
array comes from the macrocell register. In Registered mode, input pins 1 and 11 are permanently
allocated as CLK and /OE, respectively. Figure 8
shows the logic array of the PEEL16V8 configured
in Registered mode.
The programmable output polarity selector provides
active-high or active-low logic. The output buffer enable is controlled by the eighth product term, allowing the macrocell to be configured for input, output
or bidirectional functions. Feedback into the array
for input or bidirectional functions is available on all
I/O pins.
Design Security
The PEEL16V8 provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the device. The
security bit is set by the PLD programmer, either at
the conclusion of the programming cycle or as a
separate step after the device has been programmed. Once the security bit has been set, it is
impossible to verify (read) or program the PEEL
until the entire device has first been erased with the
bulk-erase function.
Signature Word
The signature word feature allows a 64-bit code to
be programmed into the PEEL16V8. The code cannot be read back after the security bit has been set.
The signature word can be used to identify the
pattern programmed into the device or to record the
design revision, etc.
Registered mode also provides the option of configuring a macrocell for combinatorial operation, with
seven product terms feeding the OR function.
3 - 10
PEEL 16V8
I
1
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I
MACRO
CELL
I
2
MACRO
CELL
I
3
MACRO
CELL
I
4
MACRO
CELL
I
5
MACRO
CELL
I
6
MACRO
CELL
I
7
MACRO
CELL
I
8
MACRO
CELL
I
9
Figure 6. PEEL16V8 Logic Array - Simple Mode
3 - 11
PEEL 16V8
I
1
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I
MACRO
CELL
I
2
MACRO
CELL
I
3
MACRO
CELL
I
4
MACRO
CELL
I
5
MACRO
CELL
I
6
MACRO
CELL
I
7
MACRO
CELL
I
8
MACRO
CELL
I
9
Figure 7. PEEL16V8 Logic Array - Complex Mode
3 - 12
PEEL 16V8
CLK
1
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
OE
MACRO
CELL
I
2
MACRO
CELL
I
3
MACRO
CELL
I
4
MACRO
CELL
I
5
MACRO
CELL
I
6
MACRO
CELL
I
7
MACRO
CELL
I
8
MACRO
CELL
I
9
Figure 8. PEEL16V8 Logic Array - Registered Mode
3 - 13
PEEL 16V8
This device has been designed and tested for the
specified operating ranges. Proper operation outside
of these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage.
Absolute Maximum Ratings
Rating
Unit
Symbol Parameter
Conditions
VCC
Supply Voltage
Relative to Ground
-0.5 to + 7.0
V
VI, VO
Voltage Applied to Any Pin2
Relative to Ground1
-0.5 to VCC + 0.6
V
IO
Output Current
Per pin (IOL, IOH)
±25
mA
TST
Storage Temperature
-65 to +150
°C
TLT
Lead Temperature
+300
°C
Soldering 10 seconds
Operating Ranges
Symbol Parameter
Conditions
Min
Max
Unit
VCC
Supply Voltage
Commercial
4.75
5.25
V
TA
Ambient Temperature
Commercial
0
+70
°C
TR
Clock Rise Time
See Note 3
20
ns
TF
Clock Fall Time
See Note 3
20
ns
TRVCC
VCC Rise Time
See Note 3
250
ms
Max
Unit
D.C. Electrical Characteristics Over the operating range
Symbol Parameter
Conditions
Min
VOH
Output HIGH Voltage
VCC=Min, IOH=-4.0mA
2.4
VOL
Output LOW Voltage
VCC=Min, IOL=16mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIL
Input Leakage Current LOW
IIH
IOZ
ISC
ICC10
CIN7
COUT
0.5
V
2.0
VCC + 0.3
V
-0.3
0.8
V
VCC = Max, VIN = GND
0 (Typ)
-10
µA
Input Leakage Current HIGH
VCC = Max, VIN = VCC
0 (Typ)
40
µA
Output Leakage Current
I/O = High-Z, GND ≤ VO ≤ VCC
±10
µA
-150
mA
9
Output Short Circuit Current
VCC = 5V, VO = 0.5V , TA = 25°C
VCC Current
VIN = 0V or 3V
f = 25MHz
All outputs disabled4
Input Capacitance
7
V
Output Capacitance
TA = 25°C, VCC = 5.0V
@ f = 1MHz
3 - 14
-30
-15
45
-25
37
mA
6
pF
12
pF
PEEL 16V8
A.C. Electrical Characteristics
Over the Operating Range
8, 11
-15
Symbol Parameter
5
-25
Unit
Min
Max
Min
Max
tPD
Input to non-registered output
3
15
3
25
ns
tOE
Input5 to output enable6
3
15
3
20
ns
5
6
tOD
Input to output disable
3
15
3
20
ns
tCO1
Clock to output
2
10
2
12
ns
tCO2
Clock to comb. output delay via
internal registered feedback
25
35
ns
tCF
Clock to Feedback
8
10
ns
5
tSC
Input or feedback setup to clock
12
15
ns
tHC
Input5 hold after clock
0
0
ns
8
tCL, tCH
Clock low time, clock high time
8
12
ns
tCP
Min clock period Ext (tSC + tCO1)
22
27
ns
fMAX1
Internal Feedback (1/tSC+tCF)12
50
40
MHz
12
fMAX2
External Feedback (1/tCP)
45.5
37
MHz
fMAX3
No Feedback (1/tCL+tCH)12
62.5
41.6
MHz
tAW
Asynchronous Reset pulse width
15
25
ns
tAP
Input5 to Asynchronous Reset
15
25
ns
tAR
Asynch. Reset recovery time
15
25
ns
tRESET
Power-on reset time for
registers in clear state
5
5
µs
Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Notes
1. Minimum DC input is -0.5V, however inputs may
2.
3.
4.
5.
6.
7.
8. Test conditions assume: signal transition times of 3ns
undershoot to -2.0V for periods less than 20ns.
VI and VO are not specified for program/verify
operation.
Test points for Clock and VCC in tR, tF are referenced at
10% and 90% levels.
I/O pins are 0V and 3V.
“Input” refers to an Input pin signal.
tOE is measured from input transition to VREF ± 0.1V,
tOD is measured from input transition to VOH - 0.1V or
VOL + 0.1V; VREF = VL see test loads in Section 6 of the
Data Book.
Capacitances are tested on a sample basis.
9.
10.
11.
12.
3 - 15
or less from the 10% and 90% points, timing reference
levels of 1.5V (unless otherwise specified).
Test one output at a time for a duration of less than 1
sec.
ICC for a typical application: This parameter is tested
with the device programmed as an 8-bit Counter.
PEEL Device test loads are specified in Section 6 of
the Data Book.
Parameters are not 100% tested. Specifications are
based on initial characterization and are tested after
any design or process modification which may affect
operational frequency.
PEEL 16V8
Ordering Information
PART NUMBER
PEEL16V8P-15
PEEL16V8J-15
PEEL16V8P-25
PEEL16V8J-25
SPEED
15ns
15ns
25ns
25ns
TEMPERATURE
C
C
C
C
Part Number
Device
Suffix
PEEL16V8P-25
Speed
-15 = 15ns tpd
-25 = 25ns tpd
Package
P = Plastic 300mil DIP
J = Plastic (J) Leaded Chip Carrier (PLCC)
3 - 16
PACKAGE
P20
J20
P20
J20