Electronics Semiconductor Division RM3182 ARINC 429 Differential Line Driver Features Description • • • • • • • • The RM3182 consists of a bus interface line driver circuit plus auxiliary gating and synchronization circuitry. Designed to address the ARINC 429 standard, the RM3182 has output rise and fall times adjustable by the selection of two external capacitor values, and the output voltage swing range can be adjusted through an externally applied VREF signal. The logic inputs as well as the sync control inputs are TTL-CMOS compatible. The device is constructed on a monolithic IC using a junction-isolated bipolar process. Sputtered SiCr resistors are used in the internal bias circuitry, providing stable internal bias currents. The RM3182 is available in 16-lead ceramic DIP and 28-pad LCC, and can be ordered with MIL-STD883B high reliability screening. Adjustable rise and fall times Adjustable output voltage swing Short circuit protected Output overvoltage protected Sync and clock enable inputs TTL and CMOS compatible inputs MIL-STD-883B types available 100 Kbits/second data rate Block Diagram V REF +VS (1) CA (9) (5) (4) Level Shifter And Slope Control (A) Data (A) (14) (6) Output Driver (A) A OUT R OUT /2 Clock (8) RL Gnd (3) CL Sync Level Shifter And Slope Control (B) (13) Data (B) R OUT /2 Output Driver (B) B OUT (11) (16) V1 Power Enable Current Regulator (2) (7) (12) -V S OverVoltage Clamps CB Notes: 1. RL and CL are external. Full load values are: RL = 400Ω, CL = 0.03µF. 2. Pin numbers are for 16-lead DIP. 65-3182-01 Rev. 1.0.0 RM3182 PRODUCT SPECIFICATION Sync PWR Enable NC VREF V1 NC NC Pin Assignments Sidebraze DIP 1 16 V1 PWR Enable 2 15 NC Sync 3 14 Clock Data (A) 4 13 Data (B) CA 5 12 CB AOUT 6 11 BOUT –VS 7 10 NC GND 8 9 +VS NC Data (A) NC NC CA NC NC Clock NC Data (B) CB NC NC NC 28 1 LCC NC AOUT –VS GND +VS BOUT NC VREF 65-3182-03 65-3182-02 Absolute Maximum Ratings Max. Units Supply Voltage (+VS to –VS) Parameter 36 V V1 Voltage +7 V VREF Voltage +6 V +VS + 0.3 V Logic Input Voltage Min. -0.3 Output Short Circuit Duration See Note 1 Output Overvoltage –6.5 +6.5 V Storage Temperature Range -65 +150 °C Operating Temperature Range (see Note 2) -55 +125 °C +300 °C Lead Soldering Temperature (60 sec.) Notes: 1. Heatsinking may he required for output short circuit at +125°C. 2. Heatsinking may be required depending on load and signal frequencies Thermal Characteristics (Still air, soldered into PC board) Sidebrazed DIP LCC +175°C +175°C 1470 mW 1040 mW Thermal Resistance θJC 25°C/W 25°C/W Thermal Resistance θJA 85°C/W 120°C/W For TA > 50°C Derate at 11.7 mW/°C 8.3 mW/°C Maximum Junction Temperature Max. PD TA < 50°C 2 PRODUCT SPECIFICATION RM3182 Electrical Characteristics (VS = ± 15V, VREF = V1 = +5V, PWR Enable = 0V, RL = open circuit, -55°C ≤ TA ≤ +125°C) Parameters Test Conditlons Positive Supply Current Data Rate = 0 to 100 Kbits/sec Negative Supply Current Data Rate = 0 to 100 Kbits/sec V1 Supply Current Data Rate = 0 to 100 Kbits/sec VREF Supply Current Data Rate = 0 to 100 Kbits/sec Min. Input Logic Level High Typ. Max. Units 11 16 mA -16 -10 mA 200 975 µA -1.0 -0.4 -0.15 mA 2.0 V Input Logic Level Low Output Voltage High 0.5 V V With Respect to Ground 4.75 5.0 5.25 Output Voltage Low With Respect to Ground -5.25 -5.0 -4.75 V Output Voltage Null Both Data Input = Logic 0 -250 0 +250 mV Input Current High VIN = 2.0V 1 10 µA Input Current Low VIN = 0.5V Output Short Circuit Current Output in High State, to Gnd -20 Output Short Circuit Current Output in Low State, to Gnd Positive Supply Current Output High and Shorted to Gnd Negative Supply Current Output Low and Shorted to Gnd -133 80 µA -1 -80 mA 150 mA 133 mA -150 1 mA 5 Input Capacitance 15 pF Note: 1. Guaranteed by design. Typical Power Dissipation Characteristics (VS = ± 15V, V1 = VREF = +5V, Pwr Enable = 0V, TA = + 25°C) Data Rate (Kbits/sec) Load 0 to 100 Open Circuit 12.5 to 14 100 Positive Supply Current Negative Supply Current Pin V1 Supply Current Internal Power Dissipatlon Load Power Dissipatlon 11 mA -10 mA 200 µA 325 mW 0 1 24 mA -24 mA 200 µA 660 mW 60 mW 1 46 mA -46 mA 200 µA 1000 mW 325 mW Full Load Full Load Note: 1. RL = 400Ω, CL = 0.03 µF (see Block Diagram). 3 RM3182 PRODUCT SPECIFICATION Principles of Operation low, AOUT will swing to +VREF and BOUT will swing to VREF (constituting a logic high state). Reversing the data input states will cause AOUT to swing to -VREF and BOUT to +VREF. With both data input signals at a logic low state, the outputs will both swing to 0V (output in null state). Each device consists of one differential driver and associated gating circuitry. The gating circuitry consists of clock and sync signal inputs which are ANDed with the two data inputs. See the block diagram and truth table. Three power supplies are required to operate the RM3182 in a typical ARINC 429 bus application: +15V, -15V, and +5V. The +5V supply, in addition to powering the internal bus current regulator, provides a reference voltage that determines the output voltage swing. The differential output swing will equal 2 VREF. If a value of VREF other than +5V is used, then a separate +5V supply is required for pin V1. The slew rate of the outputs, and consequently rise and fall times, can be adjusted through the selection of two external capacitor values. Typical values are CA = CB = 75 pF for high-speed operation (100 Kbits/sec) and CA = CB = 500 pF for low-speed operation (12.5 to 14 Kbits/sec). The device can be powered down by applying a logic high signal to the Power Enable pin. If the power down feature is not used, then the Power Enable pin should be tied directly to ground. Figure 1 depicts connections for the ARINC 429 application. The driver output impedance is nominally 75Ω. With the Data(A) input at a logic high and Data (B) input at a logic +15V +5V 1 V REF 16 V1 4 Data (A) 3 Sync 14 9 Clock +V S 6 RM3182 A OUT Inputs To Bus 13 Power Enable Data (B) Gnd CB 8 CA 12 -VS 11 B OUT 7 2 5 Note: Pin numbers are for the 16-lead DIP. -15V 65-3182-04 Figure 1. ARINC 429 Bus Application 4 PRODUCT SPECIFICATION RM3182 0V Data A 0V Data B Adjust By CB or Rate Select +VREF Out A or Amp A -VREF Adjust By CA or Rate Select Out B or Amp B +V REF -VREF High = +VREF Differential Output Out A- Out B or Amp Out AAmp Out B Null 0V Low = -VREF Note: Outputs unloaded 65-3182-05 Figure 1. Switching Waveforms Truth Table Sync Clock Data (A) Data (B) AOUT BOUT Comments X L X X 0V 0V Null L X X X 0V 0V Null H H L L 0V 0V Null H H L H -VREF +VREF Low H H H L +VREF -VREF High H H H H 0V 0V Null 5 RM3182 PRODUCT SPECIFICATION Mechanical Dimensions 16-Lead Sidebraze DIP Inches Symbol Min. A b1 b2 c1 D E e eA L L1 Q s1 s2 Notes: Millimeters Max. Min. — .200 .014 .023 .045 .065 .008 .015 — .860 .280 .310 .100 BSC .300 BSC .125 .200 .140 — .015 .070 .005 — .005 — Notes Max. — 5.08 .36 .58 1.14 1.65 .20 .38 — 21.84 7.11 7.87 2.54 BSC 7.62 BSC 3.18 5.08 3.56 — .38 1.78 .13 — .13 — 7 2 7 4, 8 6 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 8, 9 and 16 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within ±.010 (.25mm) of its exact longitudinal position relative to pins 1 and 16. 5. Applies to all four corners (leads number 1, 8, 9, and 16). 6. "eA" shall be measured at the centerline of the leads. 3 5 7. All leads – Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 8. Fourteen spaces. D 8 1 9 16 NOTE 1 E s1 S2 eA A Q L b2 6 b1 e L1 c1 PRODUCT SPECIFICATION RM3182 Mechanical Dimensions (continued) 28 Terminal Leadless Chip Carrier (LCC) Inches Symbol A A1 B1 B3 D/E D1/E1 D2/E2 e h j L1 L2 L3 Min. Max. Min. Max. .060 .050 .022 .006 .100 .088 .028 .022 1.52 1.27 .56 .15 2.54 2.24 .71 .56 .442 .460 .300 BSC .150 BSC .050 BSC 11.23 11.68 7.62 BSC 3.81 BSC 1.27 BSC .040 REF .020 REF 1.02 REF .51 REF .045 .075 .003 Notes: Millimeters .055 .095 .015 1.14 1.91 .08 Notes 3, 6 3, 6 2 2, 5 7 7 N 28 28 2. Unless otherwise specified, a minimum clearance of .015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.). 3. Dimension "A" controls the overall package thickness. The maximum "A" dimension is the package height before being solder dipped. 4 4 1.40 2.41 .38 ND/NE 1. The index feature for terminal 1 identification, optical orientation or handling purposes, shall be within the shaded index areas shown on planes 1 and 2. Plane 1 terminal 1 identification may be an extension of the length of the metallized terminal which shall not be wider than the B1 dimension. 5 4. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. The index corner shall be clearly unique. 5. Dimension "B3" minimum and "L3" minimum and the appropriately derived castellation length define an unobstructed three dimensional space traversing all of the ceramic layers in which a castellation was designed. Dimension "B3" maximum and "L3" maximum define the maximum width and depth of the castellation at any point on its surface. Measurement of these dimensions may be made prior to solder dripping. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. LID PLANE 2 PLANE 1 D See Note 1 A1 L3 B3 B1 E DETAIL "A" A Index Corner (j) x 45° (h) x 45° 4 3 PLCS DETAIL "A" D2 e D1 L2 L1 7 PRODUCT SPECIFICATION RM3182 Ordering Information Part Number Package Operating Temperature Range RM3182S S -55°C to +125°C RM8182S/883B S -55°C to +125°C RM3182L L -55°C to +125°C RM3182L/883B L -55°C to +125°C Notes: /883B suffix denotes MIL-STD-883, Level B processing S = 16 Lead sidebraze ceramic DIP L = 28 Terminal Leadless Chip Carrier The information contained in this data sheet has been carefully compiled; however, it shall not by implication or otherwise become part of the terms and conditions of any subsequent sale. Raytheon’s liability shall be determined solely by its standard terms and conditions of sale. No representation as to application or use or that the circuits are either licensed or free from patent infringement is intended or implied. Raytheon reserves the right to change the circuitry and any other data at any time without notice and assumes no liability for errors. LIFE SUPPORT POLICY: Raytheon’s products are not designed for use in life support applications, wherein a failure or malfunction of the component can reasonably be expected to result in personal injury. The user of Raytheon components in life support applications assumes all risk of such use and indemnifies Raytheon Company against all damages. Raytheon Electronics Semiconductor Division 350 Ellis Street Mountain View, CA 94043 650.968.9211 FAX 650.966.7742 8/97 0.0m Stock# DS30003182 © Raytheon Company 1997