RTD2010 REALTEK FLAT PANEL DISPLAY CONTROLLER RTD2010 Product Brief This document contains introductory information pertaining to the Realtek RTD2010 Flat Panel Display Controller. Because proprietary and confidential information is contained in the complete specifications, this brief is offered to those interested in the chip. For a more detailed description of the device, please contact your Realtek sales representative. 1. Features.................................................................................................................................................................................... 2 2. General Description ................................................................................................................................................................ 3 3. Block Diagram......................................................................................................................................................................... 4 4. Pin Assignments....................................................................................................................................................................... 5 5. Pin Descriptions....................................................................................................................................................................... 6 5.1 ADC ................................................................................................................................................................................... 6 5.2 PLL..................................................................................................................................................................................... 6 5.3 Control Interface ................................................................................................................................................................ 7 5.4 Digital Input ....................................................................................................................................................................... 8 5.5 Display Port........................................................................................................................................................................ 8 5.6 Miscellaneous Interface...................................................................................................................................................... 9 5.7 DDC Channel ..................................................................................................................................................................... 9 5.8 Power & Ground ................................................................................................................................................................ 9 5.9 MCU Interface.................................................................................................................................................................. 10 2002/11/12 1 Rev1.20 RTD2010 1. Features Color Processor ! Digital brightness and contrast adjustments ! Gamma correction ! Dithering logic for 18-bit panel color depth enhancement General ! Integrated Spread-Spectrum DCLK PLL ! Integrated 8-bit triple-channel 110MHz ADC/PLL ! Integrated programmable timing controller ! Integrated microcontroller compatible with the standard 8032 ! 24 General-purpose input/outputs (GPIOs) ! Embedded fully functional multi-language OSD support ! Embedded DDC supports DDC1, DDC2B, and DDC/CI ! Supports ISP functionality on DDC channel ! 3 Embedded programmable PWM ! Zoom scaling up and down ! Embedded Pattern Generator ! No external memory required ! Requires only one crystal to generate all timing Output Interface ! Fully programmable, built-in display timing generator ! 1 and 2-pixel/clock panel support, up to 110MHz ! Pin swap, odd/even swap and red/blue group swap ! Programmable TCON function support ! Reduced EMI and Power saving features Host Interface ! Supports 3/4 pins MCU serial bus interface ! Support parallel bus interface while using internal MCU Analog RGB Input Interface ! Supports up to 110MHz (XGA @ 75Hz) ! Supports Sync On Green (SOG) and de-composite sync modes ! On-chip high-performance PLLs Embedded OSD ! 12*18 dot font per character ! Embedded 256 characters and symbols including 16 multi-color symbols ! User font RAM, which allows programming of 128 special symbols ! 7 background colors and 8 character colors ! Programmable width and height control ! 4 background windows ! Selectable shadow color for windows and characters ! Intensity, blinking effects ! Fade-in/out effect ! Frame shadowing and independent row shadowing ! Frame bordering and independent row bordering ! 4 channel 8-bits PWM output, and selectable PWM clock frequency ! Row-to-Row spacing to maintain constant display height ! Window alpha-blending effect Digital Input Interface ! Supports 24-bit pixel digital input up to 160MHz ! Supports 12-bit DVO input ! Supports 16/24-bit YUV422/444 video format input ! Supports 8-bit video format input ! Built-in YUV to RGB color space converter & de-interlace ! Capture window auto position & auto phase tracking capability Auto Detection /Auto Calibration ! Input format detection ! Compatibility with standard VESA mode and support for user-defined mode ! Smart engine for Phase and Image position calibration Power & Technology ! 2.5V/3.3V power supply ! 0.25µm CMOS process; 208-pin PQFP package Scaling ! Fully programmable zoom ratios ! Independent horizontal/vertical scaling ! Advanced zoom algorithm provides high image quality ! Sharpness/Smooth filter enhancement 2002/11/12 2 Rev1.20 RTD2010 2. General Description The Realtek RTD2010 is a highly-integrated single chip IC controller solution for producing real time, top quality digital video and computer graphic images on LCD monitor/flat panel displays, such as XGA LCD monitors. LCD monitors and flat panel displays provide a sharp, flicker free display while saving space and energy for desktop PC applications. The RTD2010 provides an ideal interface between industry standard digital graphics controllers and a wide variety of LCD panel devices. Flat panel devices using the RTD2010 can support all incoming VESA modes and interface to any TFT LCD device, up to XGA (1024x768) resolution. For increased flexibility, the RTD2010 supports both analog and digital interface inputs. The embedded 8-bit triple-channel 110MHz high-quality Analog to Digital Converter (ADC) and PLL support up to a 1024x768 75Hz RGB analog input signal. The digital interface can support Transmission Minimized Differential Signaling (TMDS) receiver or Video-Decoder or DVO digital output signals up to 160MHz. The RTD2010 features an embedded On-Screen Display (OSD) engine. This OSD enables either character based or bit map based menu display. Through this menu, display parameters, such as brightness and contrast, can be controlled, and information on resolution and frequency, can be displayed. The embedded display pattern generator is a function for panel testing. Processing 24-bit RGB or 16-bit YUV input data streams, and conversion of input VGA signals to high resolution output, the RTD2010 implements a sophisticated scaling algorithm. This feature allows the RTD2010 to perform horizontal and vertical interpolation or replication and up & down image scaling, based on programmable parameters, to create images of the highest quality. The built-in advanced filtering engine enables independent vertical and horizontal zoom/shrink, and, through enhancement of individual pixels, enhances image sharpness, and provides superb visual quality. This allows appropriate sized display of crisp, sharp text and smooth, clear graphics, taking full advantage of LCD flat panel technology. Also featured are enhanced color processing functions, including gamma correction and dithering logic. Brightness, contrast and gamma correction can be programmed through the internal gamma correction lookup tables. Full control of output panel data is obtained by color mapping input RGB data. The 8-bit/color pixel path offers up to 16.7 million color support for 24-bit TFT LCD panels. 18-bit LCD panels are also supported through spatial and temporal dither algorithms. Increased integration in the RTD2010 includes components such as an 8032 compatible micro controller, and DDC RAM to provide monitor information the PC through the DDC1/DDC2B protocol. Internal System Programming (ISP) is accomplished through the DDC serial bus, supporting enhanced DDC-communication from PC to monitor, such as DDC/CI is also supported. Finally, the Timing-Controller (TCON) generates the control signals for LCD-panel rather than LCD-monitor, and the embedded spread-spectrum technology reduces EMI effects. All these features make the RTD2010 is the optimum solution for superior-quality image display. 2002/11/12 3 Rev1.20 RTD2010 3. Block Diagram Program ROM (64KB~128KB) Data Addr Ctrl VS HS R/G/B NTSC PAL RTD2010 Flat Panel Display 5C 16D 8D Video Decoder IIC Rx0~2 RxC IIC TMDS Receiver IIC 5C 24.576MHz EEPROM TCON 5C 48D LCD Panel Row/Column Driver 5C 48D TTL Signal LCD Panel 48D 5C TMDS/LVDS LCD Panel Key-In Application System Block Diagram Analog RGB Triple-ADC FIFO Color Conversion Timing Control Sync Processor Control Register Scaling Up Built-In Build-In OSD PLL Onchip MCU Color Processing OSD MUX Digital RGB/YUV HS & VS Panel Driver Panel 24.576MHz Flat Panel Display -- RTD2010 Chip Functional Block Diagram 2002/11/12 4 Rev1.20 RTD2010 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 P2.4/TCON15 P2.3/TCON14 P2.2/TCON13 P2.1/TCON12 P2.0/TCON11 P1.7/TCON10 P1.6/TCON9 GNDIK P1.5/TCON8 P1.4/TCON7 VCCK BBLU0 BBLU1 BBLU2 BBLU3 BBLU4 BBLU5 BBLU6 BBLU7 BGRN0 BGRN1 BGRN2 BGRN3 BGRN4 BGRN5 GNDIK BGRN6 BGRN7 VCCK BRED0 BRED1 BRED2 BRED3 BRED4 BRED5 BRED6 BRED7 BCLK BEN BVS BHS VODD PWM0 P2.7/PWM2 P2.6/PWM1 P3.3 INT0#/P3.2 DDCSCL DDCSDA AVS GNDO AHS 4. Pin Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Realtek RTD2020 RTD2010 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VCC3IO EXT# ADC_VDD ADC_VDD R ADC_GND ADC_GND G ADC_VDD ADC_VDD B ADC_GND ADC_GND ADC_TEST ADC_VDD ADC_VDD ADC_REFIO ADC_GND ADC_GND WE#/P0.4 ROM_ADDR_BANK GNDIK ROM_ADDR15 VCCK ROM_ADDR14 ROM_ADDR13 ROM_ADDR12 GNDIK ROM_ADDR11 VCCK ROM_ADDR10 GNDO ROM_ADDR9 ROM_ADDR8 VCC3IO ROM_ADDR7 ROM_ADDR6 ROM_ADDR5 ROM_ADDR4 ROM_ADDR3 ROM_ADDR2 ROM_ADDR1 ROM_ADDR0 ROM_DATA0 ROM_DATA1 ROM_DATA2 ROM_DATA3 GNDO ROM_DATA4 ROM_DATA5 VCC3IO ROM_DATA6 DAGRN4 DAGRN5 DAGRN6 GNDO DAGRN7 DARED0 DARED1 VCC3IO DARED2 GNDIK DARED3 VCCK DARED4 DARED5 DARED6 DARED7 DEN/TCON4 DVS/TCON5 DHS/TCON6 VCC3IO DCLK/ECLK GNDO P1.0/TCON0 P1.1/TCON1 P1.2/TCON2 VCCK P1.3/TCON3 GNDIK T0#/P3.4/SCSB T1#/P3.5/SCLK P3.6/SDI P3.7/SDO INT1#/P3.1/IRQ# P3.0/PWDN# RESET# PLL_VDD PLL_GND PLL_GND PLL_GND XI XO PLL_VDD PLL_VDD PLL_TEST1 PLL_TEST2 PLL_GND PLL_GND PLL_VDD PLL_VDD PLL_GND PSEN# ROM_DATA7 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 P2.5/TCON16 DBBLU0 DBBLU1 VCC3IO DBBLU2 GNDO DBBLU3 DBBLU4 DBBLU5 DBBLU6 DBBLU7 GNDIK DBGRN0 DBGRN1 DBGRN2 VCCK DBGRN3 VCC3IO DBGRN4 GNDO DBGRN5 DBGRN6 DBGRN7 DBRED0 DBRED1 DBRED2 GNDIK DBRED3 VCCK DBRED4 DBRED5 VCC3IO DBRED6 GNDO DBRED7 REFCLK/OCLK DABLU0 DABLU1 DABLU2 DABLU3 VCCK DABLU4 DABLU5 GNDIK DABLU6 VCC3IO DABLU7 GNDO DAGRN0 DAGRN1 DAGRN2 DAGRN3 RTD2010 Pin-Out Diagram 2002/11/12 5 Rev1.20 RTD2010 5. Pin Descriptions In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation. A = Analog P = Power I = Input G = Ground O = Output 5.1 ADC Name ADC_REFIO ADC_TEST B G R ADC_VDD ADC_GND Type AI AIO AI AI AI AP AG Pin No 140 143 146 149 152 141,142 147,148 153,154 138,139 144,145 150,151 Description ADC Reference Pad ADC Test Pin / SOG input Analog Input from BLUE Channel Analog Input from GREEN Channel Analog Input from RED Channel ADC Analog Power ADC Analog Ground Total: 17 Pins 5.2 PLL Name XI XO PLL_TEST1 PLL_TEST2 PLL_VDD PLL_GND Type AI AO AIO AIO AP AG Pin No 92 93 96 97 88,94 95,100 101 89,90 91,98 99,102 Description Reference Clock Input Reference Clock Output Test Pin 1 Test Pin 2 PLL Analog Power PLL Analog Ground Total: 15 Pins 2002/11/12 6 Rev1.20 RTD2010 5.3 Control Interface Name (EXT# =0): SCSB (EXT# =1): GPIO_P3.4 (EXT# =0): SCLK (EXT# =1): GPIO_P3.5 (EXT# =0): SDI (EXT# =1): GPIO_P3.6 (EXT# =0): SDO (EXT# =1): GPIO_P3.7 (EXT# =0): IRQ# (EXT# =1): GPIO_P3.1 (EXT# =0): PWDN# (EXT# =1): GPIO_P3.0 RESET# 2002/11/12 Type I I/O Pin No 81 Description I I/O 82 Serial Control I/F Clock GPIO_P3.5 / T1# I I/O 83 Serial Control I/F Data in GPIO_P3.6 O I/O 84 Serial Control I/F Data out GPIO_P3.7 O I/O 85 Controller’s IRQ# Output; GPIO_P3.1 / INT#1 I I/O 86 PowerDown# for Controller GPIO_P3.0 I 87 (EXT#=0): RESET# for Controller; (EXT#=1): RESET# for MCU Total: 7 Pins Serial Control I/F Chip Select GPIO_P3.4 / T0# 7 Rev1.20 RTD2010 5.4 Digital Input Name AHS AVS VODD BHS BVS BENA BCLK BRED/YIN [7:0] / DVODATA [11:4] / VIDEO8 BGRN [7:0] / DVODATA [3:0] BBLU/UVIN [7:0] Type I I I I I I I I I I Pin No 158 160 167 168 169 170 171 172,173 174,175 176,177 178,179 181,182 184,185 186,187 188,189 190,191 192,193 194,195 196,197 Description VGA-port Horizontal Sync VGA-port Vertical Sync Video ODD Signal VGB-port Horizontal Sync VGB-port Vertical Sync VGB-port Input Data Enable VGB-port Input Clock VGB-port Input Data (Red/Y) VGB-port Input Data (Green) VGB-port Input Data (Blue/UV) Total: 31 Pins 5.5 Display Port Name DCLK DHS DVS DEN DARED [7:0] Type O O O O O DAGRN [7:0] O DABLU [7:0] O DBRED [7:0] O DBGRN [7:0] O DBBLU [7:0] O Pin No 73 71 70 69 68, 67, 66 65, 63, 61 59, 58 57, 55, 54 53, 52, 51 50, 49 47, 45, 43 42, 40, 39 38, 37 35, 33, 31 30, 28, 26 25, 24 23, 22, 21 19, 17, 15 14, 13 11, 10, 9, 8 7, 5, 3, 2 Description Display clock; / TCON_ECLK Display Horizontal Sync; / TCON_6 Display Vertical Sync; / TCON_5 Display Data Enable; / TCON_4 Display A-port RED Data Display A-port GREEN Data Display A-port BLUE Data Display B-port RED Data Display B-port GREEN Data Display B-port BLUE Data Total: 52 Pins 2002/11/12 8 Rev1.20 RTD2010 5.6 Miscellaneous Interface Name REFCLK PWM_0 Type IO O Pin No 36 166 Description In/out Test Pin for DCLK; / TCON_OCLK PWM_0 Output Total: 2 Pins 5.7 DDC Channel Name DDCSDA DDCSCL Type I O I Pin No 156 161 Description DDC Serial Control I/F Data Input DDC Serial Control I/F Data Output DDC Serial Control I/F Clock Total: 2 Pins 5.8 Power & Ground Name 3.3V Power Type P 3.3V Ground G 2.5V Power P 2.5V Ground G Pin No 4, 18 32, 46 60, 72 106,122 157 6, 20 34, 48 56, 74 109,125 159 16, 29 41, 64 78,127 133,180 198 12, 27 44, 62 80,129 135,183 201 Description VCC3IO: 9 GNDO: 9 VCCK: 9 GNDIK: 9 Total: 36 Pins 2002/11/12 9 Rev1.20 RTD2010 5.9 MCU Interface Name I/O Pin No PSEN# ROM_DATA [7:0] O IO ROM_ADDR [15:9] O I ROM_ADDR [8:0] O ROM_ADDR_BA NK GPIO_P0.4 EXT# GPIO_P1.0 GPIO_P1.1 GPIO_P1.2 GPIO_P1.3 GPIO_P1.4 GPIO_P1.5 GPIO_P1.6 GPIO_P1.7 GPIO_P2.0 GPIO_P2.1 GPIO_P2.2 GPIO_P2.3 GPIO_P2.4 GPIO_P2.5 GPIO_P2.6 GPIO_P2.7 (EXT# =0): PWDN# (EXT# =1): GPIO_P3.0 (EXT# =0): IRQ# (EXT# =1): GPIO_P3.1 GPIO_P3.2 GPIO_P3.3 (EXT# =0): SCSB (EXT# =1): GPIO_P3.4 (EXT# =0): SCLK (EXT# =1): GPIO_P3.5 (EXT# =0): SDI (EXT# =1): GPIO_P3.6 (EXT# =0): SDO (EXT# =1): GPIO_P3.7 O 103 104,105,107 108,110,111 112,113 134,132,131 130,128,126 124 123,121,120 119,118,117 116,115,114 136 Description Program Load Enable ROM Data Input ROM Address Output DDC_CA latch ROM Address Output XDATA/PROG# Bank Select I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O 137 155 75 76 77 79 199 200 202 203 204 205 206 207 208 1 164 165 Share GPIO_P0.4 / WR# External MCU, Internal MCU Disable GPIO_P1.0 / TCON_0 GPIO_P1.1 / TCON_1 GPIO_P1.3 / TCON_2 GPIO_P1.3 / TCON_3 GPIO_P1.4 / TCON_7 GPIO_P1.5 / TCON_8 GPIO_P1.6 / TCON_9 GPIO_P1.7 / TCON_10 GPIO_P2.0 / TCON_11 GPIO_P2.1 / TCON_12 GPIO_P2.2 / TCON_13 GPIO_P2.3 / TCON_14 GPIO_P2.4 / TCON_15 GPIO_P2.5 / TCON_16 GPIO_P2.6 / PWM1 GPIO_P2.7 / PWM2 PowerDown# for Controller GPIO_P3.0 O I/O Share Controller’s IRQ# output; GPIO_P3.1 / INT1# I/O I/O I I/O 162 163 Share GPIO_P3.2 / INT0# GPIO_P3.3 Serial control I/F chip select GPIO_P3.4 / T0# I I/O Share Serial control I/F clock GPIO_P3.5 / T1# I I/O Share Serial control I/F data in GPIO_P3.6 O I/O Share Serial control I/F data out GPIO_P3.7 Total: 46 pins (6 share) 2002/11/12 10 Rev1.20 RTD2010 Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw 2002/11/12 11 Rev1.20