Datasheet (Advance Information) TC2411 14-Bit, 1 GSPS Digital-to-Analog Converter with Standby Mode of Operation The TC2411 is a 14-bit, 1 GSPS digital-to-analog converter that delivers exceptional high-frequency performance. The TC2411 is designed to support single or multiple transmit IF signals up to 500 MHz and to deliver superior dynamic range at a sampling rate up to a guaranteed 1 GSPS. A power down feature has been incorporated into the TC2411 which allows the part to be placed into a Standby Mode of operation. • • • Applications The TC2411’s high sample rate makes it ideal for the following applications: • Signal generation • Direct digital synthesis (DDS) • Test and measurement • Software radio • Single- and multi-carrier transceivers • Radar (Including Burst mode capability) High resolution High Clock rate Standby Mode for lower power dissipation Technical Features • • • • • • • • • Description As shown in the functional block diagram below, the TC2411 features a 5-Bit Unary + 9-Bit Binary R2R architecture. 14-bit straight binary data can be input to the DAC at a sample rate of up to 1 GSPS. The DAC provides low-noise and low-spurious performance with digital IF input signals across the first Nyquist band. Ordering Information The highly linear analog output produced by the TC2411 may be filtered externally to reject the signal image, and is suitable for single-stage upconversion applications. 5 Digital Input Clock In 2.5V Ref Out 2.5V Ref In Buffer + Register 14 5 MSB Decode 9 Signal-Noise Ratio…..……......74dBc @126MHz Signal Input……………1000MSPS, 14bits LVDS Spur Free Dynamic Range…...75dBc @126MHz Clock Input Drive.. 0 to +13dBm, 25Ω differential Full Scale Output……..…-2dBm, 50Ω differential Voltage Reference……...2.5V Bandgap On-Chip Power Dissipation …..……………………….1.8W Technology ……………….0.5 µm SiGe BiCMOS Packaging......96 ball, Pb-free, Cavity-down BGA PART NUMBER TEMP RANGE (°C) PACKAGE CLOCK SPEED TC2411-IB -40°C to +85°C 96 ball Pb-free BGA 1000 MHz TC2411-KIT +25C 31 31 Analog Output Unary Register 9 Buf Amp Evaluation Kit Binary R-2R Ladder Band Gap Amp Ref Cell Figure 1: TC2411 Functional Block Diagram 1 Copyright 2004 TelASIC Communications, Inc. All rights reserved. www.telasic.com Tel: 310.955.3838. Specifications subject to change without notice. Datasheet (Advance Information) TC2411 Absolute Maximum Ratings (Electrical performance is not guaranteed at absolute maximum ratings. Exposure to absolute maximum ratings for an extended period of time may impair the useful life of the product) Parameter Max Unit Electrical +5.0V Supply Voltage AVCC, DVDD +5.5 V +3.3V Supply Voltage DVCC +3.6 V -5.0V Supply Voltage AVEE, DVEE -5.5 V Clock Input Voltage +4.0 Vpp Environmental Operating Temp Range Storage Temp Range Maximum Junction Temperature Reflow Soldering Peak Temperature -40 to +85 -65 to +150 +110 +260 o C C o C o C o TC2411 Electrical Specifications (AVEE, DVEE = -5V; AVCC, DVDD = +5V; DVCC = +3.3V; IOUT = 20 mA, -40oC to +85°C ambient, unless otherwise noted) DC SPECIFICATIONS CONDITION MIN TYP MAX UNITS 4.75 5.0 5.25 V Supply Voltages AVCC, DVDD DVCC 3.13 3.3 3.46 V AVEE -5.25 -5.0 -4.75 V DVEE -5.25 -5.0 -4.75 V Normal Mode AVCC + DVDD + DVCC Current 30 mA AVEE + DVEE Current 330 mA Power Consumption Reference Voltage info Reference Output Load Regulation Resolution Vout_REF 1.8 W 2.5 V 14 Bits 0 < Isource < Imax mV Standby Mode 2 AVCC + DVDD + DVCC Current 40 mA AVEE + DVEE Current 140 mA Power Consumption 850 mW MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 TC2411 Electrical Specifications continued (AVEE, DVEE = -5V; AVCC, DVDD = +5V; DVCC = +3.3V; IOUT = 20 mA, -40oC to +85°C ambient, unless otherwise noted) DIGITAL SPECIFICATIONS CONDITION MIN TYP MAX UNITS Logic Inputs (N1- N14, P1 – P14) Compatibility LVDS Input Impedance 100 ohms Common Mode Voltage (VCM) +1.2 V Differential Input High Level VCM = +1.2V Differential Input Low Level VCM = +1.2V Data Coding +100 -100 mV mV Binary Switching characteristics Setup Time 130 ps Hold Time 440 ps Propagation Delay Time 400 ps Data Rise Time 10% to 90 % 220 ps Data Fall Time 90% to 10 % 230 ps 3.3 Volts 0 Volts Reset (RST) High Level Low Level Pulse Width 2.5 Pulse Repetition Rate DC Propagation Delay ns 200 MHz Clock cycles 3 Standby Mode (SLP, SLN) Single Ended Drive Low Level 0 Volts High Level 3.3 Volts Differential drive (External100Ω) Low Level 1.0 Volts High Level 1.4 Volts ANALOG SPECIFICATIONS CONDITION MIN Guaranteed 1000 TYP MAX UNITS DAC Clock (CLKP, CLKN) Maximum Conversion Rate MSPS Differential Input Voltage 1.5 Vpp Common-mode Input Voltage -3.1 V Differential Input Resistance 25 ohms 0.480 Vp-p 50 ohms Analog Output (VOP, VON) Full Scale Output Voltage Differential Output Resistance 3 20 mA Differential Output Current MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 DYNAMIC SPECIFICATIONS CONDITION MIN TYP MAX UNITS DAC Output vs Frequency @ -0.5 dBFS fout = 33 MHz -3 dBm fout = 126 MHz -3 dBm fout = 251 MHz -5 dBm fout = 376 MHz -8 dBm fout = 490 MHz -9 dBm fout = 33 MHz -166 dBm/Hz fout = 126 MHz -164 dBm/Hz fout = 251 MHz -161 dBm/Hz fout = 376 MHz -161 dBm/Hz fout = 490 MHz -160 dBm/Hz fout = 33 MHz -78 dBc fout = 126 MHz -75 dBc fout = 251 MHz -70 dBc fout = 376 MHz -65 dBc fout = 490 MHz -60 dBc Noise Spectral Density @ -0.5 dBFS SFDR vs Frequency @ -0.5 dBFS IMD IF = 135 MHz, 145 MHz 2 Tones @ -6.5 dBFS -82 dBc IF = 110 MHz, 120 MHz, 130 MHz, 140 MHz 4 Tones @ -12.5 dBFS -82 dBc ACPR (EDGE) IF = 260 MHz 1 Tone @ -3.5 dBFS -95 dBc 4 Tones @ -15.5 dBFS -88 dBc IF = 260 MHz 1 Tone @ -10.5 dBFS -75 dBc IF = 230 MHz, 240 MHz, 260 MHz, 270 MHz 4 Tones @ -17.5 dBFS -76 dBc IF = 230 MHz, 240 MHz, 260 MHz, 270 MHz ACPR (WCDMA) Analog Output Response Output Settling Time pS Output Rise Time (10 - 90%) 220 pS Output Fall Time (90 – 10%) 230 pS FS = Full-Scale 0.5 ps-V 0.1 ps-V MS = Mid-Scale 0.4 ps-V 0.2 ps-V Glitch Energy -FS to +FS transition +FS to -FS transition -MS to +MS transition +MS to -MS transition 4 MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 TC2411 Thermal Characteristics Normal Mode of Operation • • • • • • θJA (oC/W) Package θJC (oC/W) 0 m/s 2m/s 3m/s 19X19 Cavity-down BGA 96L 2.72 20.2 18.5 17.5 Note Results based on FEA simulation without heat sink. The DC power of the TC2411 is 1.8 W in normal mode of operation Maximum Junction Temperature is not to exceed 110oC. There is no need for an external heat sink if maximum ambient temperature is +70oC. An external heat sink is recommended for ambient temperatures in excess of +70oC to insure that the junction temperature does not exceed 110oC maximum. Use of standby mode reduces the average power dissipation proportional to the normal mode / standby mode duty cycle and allows a higher ambient temperature before a heat sink must be used to insure that the junction temperature does not exceed 110oC maximum. In the above table, θJA is presented according to JEDEC JESD 51-2 (natural convection) and 51-6 (forced convection). Thermal simulation assumes the package is mounted on the test board specified by JEDEC JESD51-9 (101.6X114.3X1.6 mm, four layers). Note: θJC: Thermal resistance from junction to case. θJA: Thermal resistance from junction to ambient. Figure 2: Standby Mode Operational Truth Table Control Signal Normal Mode Standby Mode STDBY_P L H STDBY_N H L Figure 3: Standby/Normal Mode Timing STDBY_P Standby Mode Standby Mode Normal Mode STDBY_N <5µS 5 <5µS MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 Figure 4: TC2411 Typical Application Circuit +5VD2 R5 510 J3 Stdby R4 560 DGN D 1 C4 1000pF +5V A R1 2.0K B2 A4 B1 3 D V CC Analog O utput AGN D 6 C14 +5V D2 AGN D R8 110 TP33 R7 330 -5V A1 J2 1 2 A8 C3 0.01uF VOP M2 An o de C a th o d e EXTCAP B3 D1 T2 VON A3 D ig ita l I n p u t D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 N[1:14] Data P[1:14] 14 pairs C6 1000pF 4 D14 U1 TC2411 AGN D J3 M1 CLKN V re f _RA V o u t_Re f F14 D V CC D V CC 4 CLKP K13 AGN D G14 R6 1K DGN D RS T V bb 6 2 M 14 L14 3 SLN T1 J1 SLP Clk In C5 1000pF C7 1000pF AGN D DGN D 6 MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 -5VA1 AGND +5VD2 TP37 A2 (AVCC) L13 (DVDD) B8 (DVDD) B7 (DVDD) B4 (VP1N7_TR) A11 (NC) A10 (DGND) A9 (DGND) A7 (DGND) A6 (DGND) A5 (DGND) B10 (GND_TRIM) B9 (GND_TRIM) J13 (GND) J2 (GND) H2 (GND) DGND J1 (GND) TP36 A1 (NC) E2 (AGND) F2 (AGND) B11 (AGND) E14 (AGND) B14 (AGND) A14 (AGND) G13 (AGND) F13 (AGND) E13 (AGND) D13 (AGND) C13 (AGND) B13 (AGND) A13 (AGND) G2 (AGND) H14 (AVEE) H13 (AVEE) B12 (AVEE) A12 (AVEE) G1 (AVEE) -5VA2 H1 (GND) -5VDT F1 (AVEE) E1 (AVEE) B6 (DVEE) B5 (DVEE) L2 (DVEE) L1 (DVEE) -5VD C2 (NC) -5VD1 K2 (DVEE) K1 (DVEE) K14 (DVEE) J14 (DVEE) Figure 4 (Cont): TC2411 Typical Application Circuit +5VA J4 9 8 1 +5VPS Power 7 6 5 4 -5VPS 3 4 VR1 6.2V 2 U2 BNX002 3 5 C8 68uF 6 FL7 +5V +5VD2 FL3 C9 0.01uF +5VA C18 0.1uF C14 0.1uF 2 1 DGND AGND PS_GND AGND FL1 PS_GND FL4 FL8 -5VA2 VR2 6.2V 4 3 1 5 C10 68uF 6 U3 BNX002 2 -5VD1 FL5 DGND PS_GND -5VA1 C12 0.1uF C11 0.01uF C13 0.1uF C16 0.1uF DGND AGND AGND -5V C19 0.1uF FL2 FL9 -5VDT -5VD C15 0.1uF C20 0.1uF DGND DGND TC2411 Typical Application Circuit Parts List FIND # QTY 1 2 3 4 3 2 TOLERANCE Capacitor Capacitor Capacitor 1000pF 0.01uF 68uF 10% 10% 10% X7R X7R Tantalum Capacitor 0.1uF 10% X7R Ferrite Bead BLM18A G221SN 1 T2 Transformer 1 2 2 U1 U2, U3 VR1, VR2 DAC EMI Filter Zener 8 7 VALUE 1 1 1 1 1 1 1 8 13 14 15 16 TYPE C4, C5, C6, C7 C3, C9, C11 C8, C10 C12, C13, C14, C15, C16, C18, C19, C20 Fl1, Fl2, Fl3, Fl4, Fl5, Fl7, Fl8, Fl9 R1 R4 R5 R6 R7 R8 T1 4 5 6 7 8 9 10 11 12 REFERENCE DESIGNATOR Resistor Resistor Resistor Resistor Resistor Resistor Transformer 2.0K 560 510 1K 330 110 TX-2-5-1 ADT11WT TC2411 BNX002 6.2V MANUFACTURER / DESCRIPTION Murata 5% 1% 1% 2% 2% 2% 2% Mini-Circuits, 2:1 impedance ratio 2% Mini-Circuits, 1:1 impedance ratio TelASIC, 14 Bit, 1GHz DAC Murata 1 Watt MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 TC2411 Performance Characteristics Figure 6: Noise Floor vs. Frequency Figure 5: SFDR vs. Frequency @ -0.5 dBFS* Noise Floor vs. Frequency SFDR vs. Frequency 0 -158 -10 -159 -20 -160 Noise Floor (dBm/Hz SFDR (dBc) -30 -40 -50 -60 -161 -162 -163 -164 -165 -70 -166 -80 -167 -90 0 0 50 100 150 200 250 300 350 400 450 50 100 150 200 500 250 300 350 400 450 500 Frequency (MHz) Frequency (MHz) * The values in Figure 1 include coax and filter losses in the setup. Figure 7: Clock Power Level vs. Noise Figure 8: DAC Output Level vs. Frequency Noise Floor vs Clock Power DAC Output Level vs Frequency -158 0 Fout = 49 MHz -159 -1 -160 -2 Fout = 249 MHz DAC Output (dBm) Noise Floor (dBm/Hz) Fout = 149 MHz -161 -162 -163 -3 -4 -5 -6 -164 -7 -165 -8 -166 -6 -4 -2 0 2 4 6 8 -9 10 0 Clock Power (dBm) 50 100 150 200 250 300 350 400 450 500 Frequency (MHz) Figure 9: Two tone IMD (dBc) vs. Frequency Intermodulation Distortion vs. Frequency 0 Intermodulation Distortion (dBc) -10 -20 -30 -40 -50 -60 -70 -80 -90 0 50 100 150 200 250 300 350 400 Frequency Center (MHz) 8 MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 Figure 10: SFDR at 33 MHz Figure 12: SFDR at 251 MHz 9 (-77 dBc) (-72 dBc) Figure 11: SFDR at 126 MHz (-75 dBc) Figure 13: SFDR at 490 MHz (-61 dBc) MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 Figure 14: 2-Tone IMD (-82 dBc)* Figure 15: 4-Tone IMD (-82 dBc)* Figure 16: ACPR 4-Tone WCDMA (-76 dBc)* * listed values indicate the actual measured levels, whereas plots shown here are limited by the instrument dynamic range 10 MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 Figure 17: TC2411 Timing Diagram 11 MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 Figure 18: TC2411 Pinouts – 96 Ball Cavity-Down BGA Package (Ball Side UP) 14 12 13 12 11 AVEE NC A AGND AGND B AGND AGND AVEE C VON D VOP 10 9 8 DGND DGND DVCC AGND AGND AGND 7 DGND 6 5 DGND DGND 4 VBB 3 ANODE 2 1 AVCC AGND VP1N7_ CATHODE VREF_ RA VOUT_ REF AGND AGND DNC1 AGND DNC2 EXTCAP E AGND AGND AGND AVEE F CLKN AGND AGND AVEE G CLKP AGND AGND AVEE H AVEE AVEE DGND DGND J DVEE DGND DGND DGND K DVEE DVCC DVEE DVEE L SLP DVDD DVEE DVEE M SLN DNC3 DVCC RST N D0P D1P D2P D3P D4P D5P D6P D7P D8P D9P D10P D11P D12P D13P P D0N D1N D2N D3N D4N D5N D6N D7N D8N D9N D10N D11N D12N D13N DVDD DVDD DVEE DVEE TR MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 TC2411 I/O Descriptions PIN NAME DESCRIPTION NAME DESCRIPTION A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 AGND AVCC ANODE VBB DGND DGND DGND DVCC DGND DGND NC AVNS AGND AGND ANALOG GND +5V REF AMP SUPPLY ANODE FOR TEMPERATURE DIODE +2.4V Bias DIGITAL GND DIGITAL GND DIGITAL GND +3.3V SUPPLY FOR ESD DIGITAL GND DIGITAL GND NO CONNECT -5V ANALOG SUPPLY ANALOG GND ANALOG GND PIN N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 D13P D12P D11P D10P D9P D8P D7P D6P D5P D4P D3P D2P D1P D0P B1 VOUT_REF VOLTAGE REFERENCE OUTPUT, +2.5V P1 D13N B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 VREF_RA CATHODE VP1N7_TR DVEE DVEE DVDD DVDD AGND AGND AGND AVEE AGND REFAMP INPUT CATHODE FOR TEMPERATURE DIODE -1.7V TEST POINT -5V SUPPLY -5V SUPPLY +5V DIGITAL SUPPLY +5V DIGITAL SUPPLY ANALOG GND ANALOG GND ANALOG GND -5V ANALOG SUPPLY ANALOG GND P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 D12N D11N D10N D9N D8N D7N D6N D5N D4N D3N D2N D1N DATA INPUT BIT 13 (MSB) DATA INPUT BIT 12 DATA INPUT BIT 11 DATA INPUT BIT 10 DATA INPUT BIT 9 DATA INPUT BIT 8 DATA INPUT BIT 7 DATA INPUT BIT 6 DATA INPUT BIT 5 DATA INPUT BIT 4 DATA INPUT BIT 3 DATA INPUT BIT 2 DATA INPUT BIT 1 DATA INPUT BIT 0 (LSB) DATA INPUT BIT 13 – COMPLEMENT (MSB) DATA INPUT BIT 12 – COMPLEMENT DATA INPUT BIT 11 – COMPLEMENT DATA INPUT BIT 10 – COMPLEMENT DATA INPUT BIT 9 – COMPLEMENT DATA INPUT BIT 8 – COMPLEMENT DATA INPUT BIT 7 – COMPLEMENT DATA INPUT BIT 6 – COMPLEMENT DATA INPUT BIT 5 – COMPLEMENT DATA INPUT BIT 4 – COMPLEMENT DATA INPUT BIT 3 – COMPLEMENT DATA INPUT BIT 2 – COMPLEMENT DATA INPUT BIT 1 – COMPLEMENT DATA INPUT BIT 0 – COMPLEMENT (LSB) DIGITAL GND DIGITAL GND -5V ANALOG SUPPLY -5V ANALOG SUPPLY DIGITAL GND DIGITAL GND DIGITAL GND -5V DIGITAL SUPPLY -5V DIGITAL SUPPLY -5V DIGITAL SUPPLY +3.3V DIGITAL SUPPLY -5V DIGITAL SUPPLY -5V DIGITAL SUPPLY -5V DIGITAL SUPPLY +5V DIGITAL SUPPLY STANDBY INPUT RESET/BURST MODE +3.3V SUPPLY FOR ESD DO NOT CONNECT STANDBY INPUT - COMPLEMENT B14 AGND ANALOG GND P14 D0N C1 C2 C13 C14 D1 D2 D13 D14 E1 E2 E13 E14 F1 F2 F13 F14 G1 G2 G13 G14 DNC1 AGND AGND VON EXTCAP DNC2 AGND VOP AVEE AGND AGND AGND AVEE AGND AGND CLKN AVEE AGND AGND CLKP DO NOT CONNECT ANALOG GND ANALOG GND DAC ANALOG OUPUT – COMPLEMENT REF AMP BYPASS CAPACITOR DO NOT CONNECT ANALOG GND DAC ANALOG OUPUT -5V ANALOG SUPPLY ANALOG GND ANALOG GND ANALOG GND -5V ANALOG SUPPLY ANALOG GND ANALOG GND DAC CLOCK INPUT – COMPLEMENT -5V ANALOG SUPPLY ANALOG GND ANALOG GND DAC CLOCK INPUT H1 H2 H13 H14 J1 J2 J13 J14 K1 K2 K13 K14 L1 L2 L13 L14 M1 M2 M13 M14 DGND DGND AVEE AVEE DGND DGND DGND DVEE DVEE DVEE DVCC DVEE DVEE DVEE DVDD SLP RST DVCC DNC3 SLN 13 MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 Application Notes: A. Power Supply Decoupling Add power supply decoupling nearby package pins as summarized below: 1. AVEE – bypass each group of pins with 0.1 uF capacitor to AGND. a. A12, B12 b. E1, F1, G1 c. H13, H14 2. DVEE – bypass each group of pins with 0.1 uF capacitor to DGND. a. K1, K2, L1, L2 b. J14, K14 c. B5, B6 3. DVDD – bypass each group of pins with 0.1 uF capacitor to DGND. a. B7, B8 b. L13 4. AVCC – bypass pin A2 with 0.1 uF capacitor to AGND. 5. DVCC – bypass pins A8, M2 and K13 with 1000 pF capacitor to DGND. B. Analog Outputs (VOP, VON) The TC2411 supplies differential analog DAC outputs at pins VOP and VON. Each pin is internally terminated with 25 ohms to analog ground, creating an effective 50 ohm differential source. When these outputs are connected to a single-ended, 50 ohm load through a 1:1 transformer, the resulting full-scale AC swing is approximately 500 mVpp (20 mA into 25 ohms). Each DAC output may be dc-coupled to a groundreferenced load. C. Clock Inputs (CLKP, CLKN) To achieve excellent phase noise performance, the TC2411 requires a differential clock input with low jitter characteristics. A 2:1 transformer may be used to convert a single-ended, 50 ohm clock source and provide a 25 ohm, ac-coupled, differential drive into CLKP and CLKN. These inputs are internally biased and terminated with 12.5 ohms per side. A very low-phase noise (low jitter) sinewave clock signal should be used for enhanced SNR performance. A sinewave oscillator featuring at least -130 dBc/Hz phase noise, above 20 KHz from the carrier is recommended. Best noise performance is achieved with clock sources capable of 1.5 Vpp or greater outputs. D. LVDS-Compliant Digital Inputs (D0P/N to D13P/N) The TC2411 offers an LVDS-compliant interface into the 14 bit data inputs. These inputs are differentially terminated on-chip with 100 ohms. 0000 corresponds to minus full-scale, while 3FFF represents plus fullscale. E. Reset/Burst Mode (RST) The TC2411 offers a burst mode capability whereby the DAC analog output can be asynchronously reset to the all zeros code (00 0000 0000 0000) irrespective of input data. Under normal operation, the RST pin should be held high at +3.3V. When a low signal (0V) is applied to RST, the DAC output resets to the all zeros code (minus full scale). Contact TelASIC sales for further information. 14 MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 F. Temperature Diode (ANODE, CATHODE) The TC2411 provides an on-chip temperature diode which may be used to monitor die temperature. Applying +5V to the anode pin and measuring the cathode node voltage into a 2K ohm load, the user can convert the resulting voltage into a temperature. Contact TelASIC sales for further information. G. External Capacitor for Ref Amp (EXTCAP) The on-chip reference amplifier requires an external capacitor to maintain excellent phase noise and jitter characteristics. Attach two capacitors, 0.01 uF and 1000 pF, in parallel between the EXTCAP pin and -5V analog supply. H. Ref Amp Input (VREF_RA) VOUT_REF is an internally generated, +2.5V precision bandgap reference. Tie this output to VREF_RA, the ref amp input. I. Standby Mode Function (SLP, SLN) The TC2411 offers a Standby Mode capability whereby the power dissipation is reduced to 850mW. The standby function comes in on pins L14 (SLP) and M14 (SLN). Under normal operation both pins are left floating. This mode may be enabled with either a single-ended drive or a differential drive. Single-ended drive, M14 (SLN) pin should be left floating and L14 (SLP) pin should be held low at +0.0V for normal operation, L14 (SLP) pin should be held high at +3.3V (CMOS) for standby mode. Differential drive level requires external 100 ohm resistor between pins L14 (SLP) and M14 SLN) and uses standard LVDS, (i.e. low level is 1.0V, high level is 1.4V). For normal mode M14 (SLN) is set low and L14 (SLP) is set high. For sleep mode M14 (SLN) is set high and L14 (SLP) is set low. J. Do Not Connect Pins Pins DNC1 (C1), DNC2 (D2), and DNC3 (M13) should be left floating. Connecting these pins to ground or to either supply voltage will alter device performance and may damage the part. 15 MKDSTC2411 Rev- Datasheet (Advance Information) TC2411 Figure 19: TC2411 96 Ball, Cavity-Down BGA Package Outline Dimensions (mm) The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. TelASIC assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, TelASIC assumes no responsibility for the functioning of undescribed features or parameters. TelASIC reserves the right to make changes without further notice. TelASIC makes no warranty, representation or guarantee out of the application or use of any product or circuit, and specifically disclaims any and all liability, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the TelASIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use TelASIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold TelASIC harmless against all claims and damages. 16 MKDSTC2411 Rev-