ETC UD61256DC08

Maintenance only
UD61256
256K x 1 DRAM
Features
Description
p Dynamic random access memory
p
p
p
p
p
p
p
p
p
p
262144 x 1 bit manufactured
using a CMOS technology
RAS access times 70 ns, 80 ns
TTL-compatible
Three-state output
256 refresh cycles
4 ms refresh cycle time
FAST PAGE MODE
Operating modes: Read, Write,
Read - Write,
RAS only Refresh,
Hidden Refresh with address
transfer
Power Supply Voltage 5 V
Packages PDIP16 (300 mil)
SOJ20/26 (300 mil)
Operating temperature range
0 to 70 °C
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90112
Addressing
The UD61256 is a dynamic WriteRead-memory with random access.
FPM facilitates faster data operation
with predefined row address. Via 9
address inputs the 18 address bits
are transmitted into the internal
address memories in a time-multiplex operation. The falling RASedge takes over the row address.
During RAS Low, the column
address together with the CAS
signal are taken over. The selection
of one or more memory circuits can
be made by activation of the RAS
input.
Read-Write-Control
The choice between Read or Write
cycle is made at the W input. HIGH
at the W input causes a Read cycle,
meanwhile LOW leads to a Write
cycle.
Both CAS-controlled and W-controlled Write cycles are possible with
activated RAS signal.
Pin Description
Pin Configuration
A8
1
26
V
D
2
25
CAS
W
3
24
Q
RAS
4
23
A6
n.c.
5
22
n.c.
SOJ
n.c.
9
18
n.c.
A0
10
17
A3
A2
11
16
A4
A1
12
15
A5
13
14
A7
VCC
Signal Name
Signal Description
A8
1
16
VSS
A0 - A8
Address Inputs
D
2
15
CAS
D
Data Input
W
3
14
Q
W
Read, Write Control
A6
RAS
Row Address Strobe
UCC
Power Supply Voltage
RAS
4
A0
5
A2
PDIP
13
12
A3
6
11
A4
A1
7
10
VCC
8
9
Top View
Top View
December 12, 1997
Data Output Control
The usual state of the data output is
the High-Z state. Whenever CAS is
inactive (HIGH), Q will float (High-Z).
Thus, CAS functions as data output
control.
After access time, in case of a Read
cycle, the output is activated, and it
contains the logic „0“ or „1“.
Q is then valid until CAS returns into
to inactive state (HIGH).
The memory cycle being a Read,
Read-Write or a Write cycle (W-controlled), Q changes from High-Z
state to the active state („0“ or „1“).
After the access time the contents of
the selected cell is available, except
for the Write cycle.
The output remains active until CAS
becomes inactive, irrespective of
RAS becoming inactive or not. The
memory cycle being a Write cycle
(CAS-controlled), the data output
keeps its High-Z state throughout
the whole cycle. This configuration
makes Q fully controllable by the
user merely through the timing of W.
The output storaging the data, they
remain valid from the end of access
time until the start of another cycle.
1
USS
Ground
CAS
Column Address Strobe
A5
Q
Data Output
A7
n.c.
no connected
UD61256
Block Diagram
Data Output
Amplifier
Output Control
CAS
D
Data Input Amplifier
W
Write-Read Control
Decoder
1 out of 4
Q
4 Write-Read
Amplifier
Data
RAS
A1
A8X
A3
A4
A5
Address Input
A2
M
U
X
A8Y
128 Kbit Array with
Sensor Amplifier
A0
Column Decoder
128 Kbit Array with
Sensor Amplifier
Clock Generator
Row
Decoder
Row
Decoder
A6
A0X to A7X
A7
A0Y to A7Y
A8
VCC
Operation
VSS
Address
Function
RAS
Stand-by
H
Read
FPM
Write
FPM
Read-Write
C
D
Q
X
X
X
High-Z
L
H
Row
Column
X
L
L
L
Row
Column
Input Data
High-Z
L
L
H→L
Row
Column
Input Data
Output
Data
L
H→L
H
Row
Column
X
Output
Data
L
H→L
H
Column
X
Output
Data
1st
cycle
L
H→L
L
Column
Input Data
High-Z
2nd
cycle
L
H→L
L
Column
Input Data
High-Z
1st
cycle
L
H→L
H→L
Column
Input Data
Output
Data
2nd
cycle
L
H→L
H→L
Column
Input Data
Output
Data
L
H
X
Row
X
High-Z
Read L → H → L
L
H
Row
Column
X
Output
Data
Write L → H → L
L
L
Row
Column
Input Data
High-Z
1st
cycle
2nd
cycle
RAS only Refresh
HIDDEN Refresh*)
X
R
L
Read-Write
Read
X
Data
W
Output
Data
Write
FPM
CAS
Row
Row
*) Transfer of Refresh Address required
2
December 12, 1997
UD61256
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and operating temperature range indicated below.
Absolute Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
VCC
-0.5
7.0
V
Input Voltage
1)
VI
-1.0
7.0
V
Output Voltage
1)
VO
-1.0
7.0
V
Output Current
IO
-50
50
mA
Power Dissipation
PD
1
W
Operating Temperature
Ta
0
70
°C
Storage Temperature
Tstg
-55
125
°C
Symbol
Min.
Max.
Unit
VCC
4.5
5.5
V
VIL
-1.0
0.8
V
VIH
2.4
5.5
V
Remarks: see page 7
Recommended Operating Conditions
Power Supply Voltage
1)
Input Low Voltage
Input High Voltage
Remark: see page 7
Capacitances
Input Capacitance
A0 to A8, D
Input Capacitance
RAS, CAS, W
Conditions
VCC
VI
f
Ta
Symbol
= 5.0 V
= VSS
= 1 MHz
= 25 °C
Output Capacitance
Max.
Unit
CI1
6
pF
CI2
7
pF
CO
7
pF
All pins not under test must be connected with ground by capacitors.
December 12, 1997
3
Min.
UD61256
Min.
Static Characteristics
Conditions
Unit
07
Power Supply Current
(average value of RAS-CAS cycles)
2)
Max.
Symbol
08
07
08
tcW = tcWmin
tcR = tcRmin
ICC1
70
60
mA
Refresh Current
(average value of RAS cycles)
2)
tcW = tcWmin
tcR = tcRmin
CAS = VIH
ICC2
70
60
mA
FPM Current
(average value of FPM cycles)
2)
tcPG = tcPGmin
RAS = VIL
ICC3
50
40
mA
Stand-by Current (TTL Level)
RAS = CAS
= VIH
ICC4
2
2
mA
Stand-by Current (CMOS Level)
RAS = CAS
= VCC - 0.2 V
ICC5
1
1
mA
Output High Voltage
IOH = -5 mA
VOH
Output Low Voltage
IOL = 4.2 mA
VOL
Input Leakage Current
at any input,
all other pins = 0 V
VI = 0 V to
5.5 V
II
-10
Output Leakage Current
Q = High-Z
VO = 0 V to
5.5 V
RAS = CAS
= VIH
IO
-10
2.4
2.4
V
0.4
0.4
V
-10
10
10
µA
-10
10
10
µA
Remarks: see page 7
4
December 12, 1997
UD61256
Symbol
Min.
Max.
3)
Dynamic Characteristics
Unit
Alt.
IEC
07
08
07
08
p ALL CYCLES
4)
Transition Time (Rise and Fall)
tT
tt
RAS Precharge Time
CAS Precharge Time
tRP
tCP
Row Address Set-up Time
Column Address Set-up Time
Row Address Hold Time
Column Address Hold Time
Column Address Hold Time ref. to RAS
Output Buffer Turn-off Delay
CAS to RAS Precharge Time
RAS to Column Address Delay Time
Column Address to RAS Lead Time
CAS to Output in Low-Z
Refresh Period
5)
6)
p READ
Random Read Cycle Time
Access Time from RAS
Access Time from Column Address
Access Time from CAS
12)
7), 8)
7), 8)
7), 8)
RAS Pulse Width
CAS Pulse Width
Read Command Set-up Time
Read Command Hold Time ref. to RAS
Read Command Hold Time
RAS to CAS Delay Time
CAS Hold Time
RAS Hold Time
9)
9)
6)
p WRITE
Random Write Cycle Time
RAS Pulse Width
CAS Pulse Width
Write Command Pulse Width
12)
3
3
tw(RASH)
tw(CASH)
50
10
60
10
ns
ns
tASR
tASC
tsu(RA-RAS)
tsu(CA-CAS)
0
0
0
0
ns
ns
t RAH
tCAH
tAR
th(RAS-RA)
th(CAS-CA)
th(RAS-CA)
10
15
55
10
15
60
ns
ns
ns
tOFF
tv(CAS)
0
0
tCRP
tRAD
tRAL
tCLZ
tREF
tCASH-RASL
tRAS-CA
tCA-RASH
tCASL-QX
trf
5
15
35
0
5
15
40
0
tRC
tcR
130
tRAC
tAA
tCAC
ta(RAS)
ta(CA)
ta(CAS)
tRAS
tCAS
tw(RASL)
tw(CASL)
70
20
80
20
tRCS
tRRH
tRCH
tsu(R-CAS)
th(RAS-R)
th(CAS-R)
0
0
0
0
0
0
tRCD
tCSH
tRSH
tRASL-CASL
tRASL-CASH
tCASL-RASH
20
70
20
20
80
20
tRC
tcW
130
150
tRAS
tCAS
tWP
tw(RASL)
tw(CASL)
tw(W)
70
20
15
80
20
15
Remarks: see page 7
December 12, 1997
5
50
50
20
20
35
40
4
4
150
ns
ns
ns
ns
ns
ns
ms
ns
70
35
20
80
40
20
ns
ns
ns
10000
10000
10000
10000
ns
ns
ns
ns
ns
50
60
ns
ns
ns
ns
10000
10000
10000
10000
ns
ns
ns
UD61256
Symbol
Dynamic Characteristics
Min.
Max.
3)
Unit
Alt.
IEC
07
08
07
08
tWCS
tDS
tDS
tsu(W-CAS)
tsu(D-CAS)
tsu(D-W)
0
0
0
0
0
0
ns
ns
ns
tWCH
tRWL
tCWL
tDHR
tDH
tDH
th(CAS-W)
th(W-RAS)
th(W-CAS)
th(RAS-D)
th(CAS-D)
th(W-D)
15
20
20
55
15
15
15
20
20
60
15
15
ns
ns
ns
ns
ns
ns
6)
tRCD
tCSH
tRSH
tRASL-CASL
tRASL-CASH
tCASL-RASH
20
70
20
20
80
20
12)
tRWC
tcRW
155
175
tRAS
tCAS
tw(RASL)RW
tw(CASL)RW
95
45
105
45
t(RASL-
95
105
ns
80
20
40
ns
ns
ns
p WRITE (continuation)
Write Command Set-up Time
Data Set-up Time ref. to CAS
Data Set-up Time ref. to W
10)
11)
11)
Write Command Hold Time
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data Hold Time ref. to RAS
Data Hold Time ref. to CAS
Data Hold Time ref. to W
RAS to CAS Delay Time
CAS Hold Time
RAS Hold Time
p READ-WRITE
Read-Write Cycle Time
RAS Pulse Width
CAS Pulse Width
CAS Hold Time
tCSH
RAS to WRITE Delay Time
CAS to WRITE Delay Time
Column to WRITE Delay Time
10)
10)
Fast Page Mode Cycle Time
RAS Pulse Width
12)
50
60
ns
ns
ns
ns
10000
10000
10000
10000
ns
ns
CASH)RW
tRAS-W
tCAS-W
tRWD
tCWD
tAWD
t(CA-W)RW
70
20
35
tPC
tRASP
tcPG
tw(RASL)
50
70
50
80
Access Time from CAS Precharge
tCPA
ta(CASH)
35
40
ns
CAS Hold Time (CAS before RAS Cycle)
tCHR
tRASL-CASH
15
15
ns
10)
p FPM
p HIDDEN-REFRESH
100000 100000
ns
ns
Remarks: see page 7
6
December 12, 1997
UD61256
Remarks:
1)
2)
3)
4)
5)
6)
7)
The Input Low Voltage must not
drop below -0.3 V for more than
40 ns.
tRASL-CASLmax and tRAS-CA are
given as reference points only;
they do not represent restrictive
conditions.
December 12, 1997
- if none of these conditions is
satisfied, the condition of the
data output (at access time) is
indeterminate, since a WRITE
cycle (W-controlled) is carried
out.
- if tRASL-CASL > tRASL-CASLmax and
tsu(CA-CAS) < (ta(CA)max - ta(CAS)max)
t a(CA) is valid,
For test conditions see test configuration for functional test and
timing diagrams.
tv(CAS) and tv(RAS) define the time
at which the data output goes to
High-Z; this time is not related to
any level.
- if tCAS-W > tCAS-Wmin,
tRAS-W > tRAS-Wmin and tsu(CA-W)RW
> tsu(CA-W)RWmin, the cycle is a
READ-WRITE cycle and the
content of the cell is available at
the data output,
- if tRASL-CASL < tRASL-CASLmax and
tRAS-CA < tRAS-CAmax ta(RAS) is
valid,
The current is inversely proportional to the cycle time; the max.
current is measured in the shortest cycle time.
VIHmin and VILmax are reference
levels for time measurement of
the input signals; transition times
are measured between VIH and
VIL.
The access time is determined
by the three times ta(RAS), ta(CAS)
and ta(CA):
- if tRASL-CASL > tRASL-CASLmax and
tsu(CA-CAS) > (ta(CA)max - ta(CAS)max)
t a(CAS) is valid.
8)
Measured with a load equivalent
to 2 TTL loads.
9)
In a READ cycle either th(RAS-R)
or th(CAS-R) must be kept.
10)
tsu(W-CAS), tRAS-W, tCAS-W and tsu(A)
do not represent restrictive parameters:
- if tsu(W-CAS) ≥ tsu(W-CAS)min, the
cycle is a WRITE cycle (CAScontrolled) and the data output
remains in High-Z throughout the
whole CAS cycle,
7
11)
These parameters refer to CAS
in the WRITE cycle (CAS-controlled) and to W during WRITE
(W-controlled) or to W in the
READ-WRITE cycle, resp.
12)
The values of tcmin are used for
indication of the particular cycle
time in which full function is guaranteed in the temperature range
from 0 to 70 °C. Values below
the one shown above may cause
permanent damage to the component.
UD61256
Test Configuration for Functional Check
VIL
A0
A1
A2
A3
A4
A5
A6
A7
A8
VCC
1,2 K
Q
100 pF
RAS
CAS
W
D
680
VSS
Output voltage check according to timing
diagrams
VIH
Input voltage according to timing diagrams (at
least 8 operating cycles before measurement).
All addresses are to be checked.
5V
IC Code Numbers
UD61256
D
C
07
Type
Package
D = PDIP
J = SOJ
Access Time
07 = 70 ns
08 = 80 ns
Operating Temperature Range
C = 0 to 70 °C
The date of manufacture is given by the 4 last digits of the mark, the 2 first digits indicating the year, and the last 2
digits the calendar week.
8
December 12, 1997
UD61256
Read
tcR
tw(RASH)
tw(RASL)
RAS
VIH
VIL
tCA SL-RASH
tCA SH-RA SL
tRA SL-CA SH
tCA SH-RA SL
CAS
tRA SL-CA SL
tw(CASL)
VIH
VIL
tsu(R-CAS)
tsu(CA -CAS)
W
th(RA S-R)
th(CA S-R)
AAAAAAAAAA
VIH AAAA
AAAAAAAAAAAAAA
VIL AAAAAAAAAAAAAA
AAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAA
AAA
tCA-RASH
tsu(RA-RAS)
th(RAS-CA )
th(RAS-RA )
V
A
A0-A8 VIH AAAA
IL AAAA
AAAAA
At
AAA
AAA
AAA
RAS-CA
ta(CA )
th(CAS-CA )
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
ta(RA S)
tv(CA S)
ta(CA S)
Q
VOH
VOL
AAAAAA
AAAA
AAAAAA
AA
tCA SL-QX
Write (CAS-controlled)
tcW
tw(RA SL)
RAS
VIH
VIL
tRASL-CASH
tCA SH-RA SL
CAS
tw(RASH)
tCASL-RASH
tw(CASL)
tRASL-CASL
VIH
VIL
tCA SH-RA SL
th(W-CAS)
th(W-RA S)
tsu(W-CAS)
W
VIH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAA
VIL AAAAAAAAAAAAAAAA
th(RAS-CA)
tsu(RA -RA S)
V AAAAAA
A0-A8 VIH AAAA
IL AAAAA
th(RAS-RA )
AAA
AAA
AAA
tsu(CA -CA S)
tsu(D-CAS)
D
VIH
VIL
Q
VOH
VOL
tw(W)
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
th(CAS-W)
tCA-RASH
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
th(CA S-CA)
th(RA S-D)
th(CAS-D)
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
December 12, 1997
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
High-Z
9
UD61256
Read-Write
tcRW
tw(RASL)RW
RAS
tw(RA SH)
VIH
VIL
tRASL-CASH
tCA SH-RA SL
CAS
tCASH-RASL
tRASL-CASL
tCASL-RASH
tw(CA SL)RW
VIH
VIL
tsu(R-CAS)
th(W-CAS)
th(W-RA S)
tCAS-W
tRAS-W
W
VIH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
VIL AAAAAAAAAAAAAAAAAA
th(RAS-CA )
th(RAS-RA )
tsu(RA -RAS)
V
A
A0-A8 VIH AAAA
IL AAAA
AAAAA
A
th(CAS-CA)
AAAA
AAAA
AAAA
tsu(CA-CAS)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
t(CA-W)RW
tsu(D-W)
D
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tw(W)
th(W-D)
VIH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
VIL AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAA
AA
t
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
a(CA S)
ta(CA )
tv(CA S)
ta(RAS)
Q
VOH
VOL
tCA SL-QX
AAAAAAAA
AAAA
AAAAAAAA
AAAA
FPM Read
tw(RA SH)
tw(RA SL)
RAS
VIH
VIL
tcPG
tRA SL-CASH
tRA SL-CA SL tw(CASL)
tCASH-RASL
CAS
tcPG
tw(CASH)
tw(CA SL)
tCA SL-RA SH
tw(CASL
tw(CASH)
VIH
VIL
tsu(R-CA S)
tsu(R-CA S)
W
VIH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
VIL AAAAAAAAAAAAAAA
AAAA
A
AAAA
AAAAA
A
th(RAS-RA )
tRAS-CA
Q
VOH
VOL
AAAA
AAA
AAAA
AAAAAAA
AAA
ta(CAS)
tCA SL-QX
ta(RA S)
th(CAS-CA )
AAAA
AA
AAAA
AAAAAA
AA
th(RAS-CA )
ta(CA)
AAAA
A
AAAA
AAAAA
A
AAAA
AAA
AAAA
AAAAAAA
AAA
tsu(CA-CAS)
th(CAS-CA)
tsu(RA-RAS)
V
A0-A8 VIH
IL
tsu(CA-CAS)
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
ta(CAS)
ta(CAS)
ta(CA )
tCASL-QX
AAAA
AAAA
AAAA
tv(CAS)
AAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
tCA-RASH
tsu(CA-CAS)
th(CA S-CA)
AAAA
AAAAAA
AAAA
AAAAAAAA
AAAAAA
AA
ta(CA)
tCASL-QX
th(RA S-R)
th(CAS-R)
tsu(R-CA S)
th(CAS-R)
th(CAS-R)
ta(CASH)
AAAA
A
AAAA
AAAAAA
tv(CAS)
tv(CA S)
ta(CASH)
10
December 12, 1997
UD61256
FPM Write (CAS-controlled)
tw(RASL)
tw(RASH)
tRA SL-CASH
RAS
VIH
VIL
tcPG
tw(CA SL)
tcPG
tCASH-RASL
CAS
tRA SL-CA SL
tw(CASL)
tw(W)
th(CA S-W)
VIH
VIL
AAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAAAAAAAAAA
AA
A0-A8 VIH AAAA
VIL AAAA
AAAAAA
AA
th(RAS-RA )
tsu(CA-CAS)
th(RA S-CA)
tsu(CA-CAS)
Q
th(RA S-D)
tsu(D-CAS)
AAAAAAAA
AAAA
AAAAAAAA
AAAA
th(W-RAS)
AAAA
AAAAAA
AAAAA
tsu(W-CA S)
AAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAAAAAAAAAA
tsu(CA-CAS)
tCA -RA SH
AAAAAA
AAAA
AAAAAA
AA
th(CA SL-D)
VIH
VIL
tsu(W-CA S)
th(CAS-CA )
tCA SL-RASH
tw(CASL)
tw(W)
th(CA S-W)
tw(W)
th(CAS-W)
AAAA
AAAAAA
AAAAA
th(CA S-CA)
tsu(RA-RAS)
D
tw(CA SH)
VIH
VIL
tsu(W-CAS)
W
tw(CASH)
AAAAAAAAA
AAAA
AAAAAAAA
AAAAAA
th(CA SL-D)
tsu(D-CA S)
VOH
VOL
AAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
t
h(CA S-CA)
th(CA SL-D)
tsu(D-CAS)
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
High-Z
RAS only Refresh
tcR
tw(RA SL)
RAS
tw(RASH)
VIH
VIL
tCA SH-RA SL
CAS
VIH
VIL
W
VIH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAA
AAAAAAAA
VIL AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
tsu(RA-RAS)
V
A0-A8 VIH AAAA
AAAAAA
AA
IL AAAAAA
th(RA S-RA)
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
D
VIH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Q
VOH
VOL
December 12, 1997
High-Z
11
UD61256
HIDDEN-Refresh with address transfer
tcR
tw(RA SL)
RAS
VIH
VIL
CAS
VIH
VIL
tCASH-RASL
tRASL-CASL
tw(RASH)
tCASL-RASH
tcR
tw(RA SL)
tRA SL-CA SH
tw(RASH)
tCASH-RASL
tsu(R-CAS)
th(RA S-R)
W
VIH AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAA
VIL AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
th(RA S-CA)
tsu(RA-RAS)
AAAAAAAA
A0-A8 VIH AAAA
AAAAAAAA
AAAA
VIL
th(RA S-RA)
AAAAA
AAAA
AAAAA
A
tRAS-CA
th(RAS-RA )
tsu(RA -RA S)
tCA -RA SH
AAAAAAAAA
AAAA
AAAAAAAA
AAAAAA
ta(CA)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
ta(CA S)
tCASL-QX
Q
VOH
VOL
ta(RAS)
tv(CAS)
AAAAAA
AAAA
AAAAAA
AA
12
December 12, 1997
Memory Products 1998
256K x 1 DRAM UD61256
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intend for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.
The information describes the type of component and shall not be considered as
assured characteristics.
Terms of delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden GmbH
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Email: [email protected]
Internet Web Site: http://www.zmd.de