ETC VS1011E

VS1011 E
VS1011e
VS1011e - MPEG AUDIO CODEC
Features
Description
• Decodes MPEG 1.0 & 2.0 audio layer III
(CBR, VBR, ABR); layers I & II optional;
WAV (PCM + IMA ADPCM)
• 320 kbit/s MP3 with 12.0 MHz external clock
• Streaming support for MP1/2/3 and WAV
• Bass and treble controls
• Operates with single 12..13 MHz or 24..26
MHz external clock
• Internal clock doubler
• Low-power operation
• High-quality stereo DAC with no phase error between channels
• Stereo earphone driver capable of driving a
30Ω load
• Separate 2.5 .. 3.6 V operating voltages for
analog and digital
• Serial control and data interfaces
• Can be used as a slave co-processor
• 5.5 KiB On-chip RAM for user code / data
• SPI flash boot for special applications
• New functions may be added with software
and 4 GPIO pins
• Lead-free and RoHS-compliant packages
LPQFP-48, BGA-49, and SOIC-28
GPIO
VS1011
GPIO
VS1011e is a single-chip MPEG audio decoder.
The chip contains a high-performance, low-power
DSP processor core VS DSP4 , working memory,
5 KiB instruction RAM and 0.5 KiB data RAM
for user applications, serial control and input data
interfaces, 4 general purpose I/O pins, as well as
a high-quality variable-sample-rate stereo DAC,
followed by an earphone amplifier and a common
buffer.
VS1011e receives its input bitstream through a serial input bus, which it listens to as a system slave.
The input stream is decoded and passed through a
digital volume control to an 18-bit oversampling,
multi-bit, sigma-delta DAC. The decoding is controlled via a serial control bus. In addition to basic
decoding, it is possible to add application specific
features, like DSP effects, to the user RAM memory.
Stereo
DAC
4
Stereo Ear−
phone Driver
audio
L
R
output
X ROM
DREQ
SO
SI
SCLK
XCS
4
Serial
Data/
Control
Interface
X RAM
VSDSP
Y ROM
XDCS
Y RAM
Instruction
RAM
Version 1.04,
2007-10-08
Instruction
ROM
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VS1011e
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Solution
VS1011 E
CONTENTS
Contents
1
License
8
2
Disclaimer
8
3
Definitions
8
4
Characteristics & Specifications
9
4.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
4.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
4.3
Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
4.4
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
4.5
Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
4.6
Switching Characteristics - Boot Initialization . . . . . . . . . . . . . . . . . . . . . . .
11
5
Packages and Pin Descriptions
12
5.1
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
5.1.1
LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
5.1.2
BGA-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
5.1.3
SOIC-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
5.2.1
LQFP-48 and BGA-49 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . .
14
5.2.2
SOIC-28 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
5.2
6
Connection Diagram, LQFP-48
16
7
SPI Buses
17
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Solution
CONTENTS
7.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
7.2
SPI Bus Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
7.2.1
VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . . . . . .
17
7.2.2
VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
Serial Protocol for Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . .
18
7.3.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
7.3.2
SDI in VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . .
18
7.3.3
SDI in VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . .
18
7.4
Data Request Pin DREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
7.5
Serial Protocol for Serial Command Interface (SCI) . . . . . . . . . . . . . . . . . . . .
19
7.5.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
7.5.2
SCI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
7.5.3
SCI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
7.6
SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
7.7
SPI Examples with SM SDINEW and SM SDISHARED set . . . . . . . . . . . . . . .
23
7.7.1
Two SCI Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
7.7.2
Two SDI Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
7.7.3
SCI Operation in Middle of Two SDI Bytes . . . . . . . . . . . . . . . . . . . .
24
7.3
8
VS1011 E
Functional Description
25
8.1
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
8.2
Supported Audio Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
8.2.1
Supported MP1 (MPEG layer I) Formats . . . . . . . . . . . . . . . . . . . . .
25
8.2.2
Supported MP2 (MPEG layer II) Formats . . . . . . . . . . . . . . . . . . . . .
26
8.2.3
Supported MP3 (MPEG layer III) Formats . . . . . . . . . . . . . . . . . . . .
26
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2007-10-08
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8.2.4
9
VS1011 E
CONTENTS
Supported RIFF WAV Formats . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
8.3
Data Flow of VS1011e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
8.4
Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
8.5
Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
8.6
SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
8.6.1
SCI MODE (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
8.6.2
SCI STATUS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
8.6.3
SCI BASS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
8.6.4
SCI CLOCKF (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
8.6.5
SCI DECODE TIME (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
8.6.6
SCI AUDATA (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
8.6.7
SCI WRAM (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
8.6.8
SCI WRAMADDR (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
8.6.9
SCI HDAT0 and SCI HDAT1 (R) . . . . . . . . . . . . . . . . . . . . . . . . .
34
8.6.10 SCI AIADDR (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
8.6.11 SCI VOL (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
8.6.12 SCI AICTRL[x] (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
Operation
36
9.1
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
9.2
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
9.3
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
9.4
SPI Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
9.5
Play/Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
9.6
Feeding PCM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
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9.7
VS1011 E
CONTENTS
SDI Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
9.7.1
Sine Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
9.7.2
Pin Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
9.7.3
Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
9.7.4
SCI Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
10 VS1011e Registers
40
10.1 Who Needs to Read This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
10.2 The Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
10.3 VS1011e Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
10.4 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
10.5 Serial Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
10.6 DAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
10.7 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
10.8 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
10.9 System Vector Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
10.9.1 AudioInt, 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
10.9.2 SciInt, 0x21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
10.9.3 DataInt, 0x22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
10.9.4 UserCodec, 0x0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
10.10System Vector Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
10.10.1 WriteIRam(), 0x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
10.10.2 ReadIRam(), 0x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
10.10.3 DataBytes(), 0x6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
10.10.4 GetDataByte(), 0x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
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VS1011 E
CONTENTS
10.10.5 GetDataWords(), 0xa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 VS1011 Version Changes
46
47
11.1 Changes Between VS1011b and VS1011e, 2005-07-13 . . . . . . . . . . . . . . . . . .
47
11.2 Migration Checklist from VS1011b to VS1011e, 2005-07-13 . . . . . . . . . . . . . . .
47
12 Document Version Changes
48
12.1 Version 1.04 for VS1011e, 2007-10-08 . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
12.2 Version 1.03 for VS1011e, 2005-09-05 . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
12.3 Version 1.02 for VS1011e, 2005-07-13 . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
12.4 Version 1.01 for VS1011b, 2004-11-19 . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
12.5 Version 1.00 for VS1011b, 2004-10-22 . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
12.6 Version 0.71 for VS1011, 2004-07-20 . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
12.7 Version 0.70 for VS1011, 2004-05-13 . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
12.8 Version 0.62 for VS1011, 2004-03-24 . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
13 Contact Information
Version 1.04,
2007-10-08
49
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VS1011 E
LIST OF FIGURES
List of Figures
1
Pin Configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
2
Pin Configuration, BGA-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
3
Pin Configuration, SOIC-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
4
Typical Connection Diagram Using LQFP-48. . . . . . . . . . . . . . . . . . . . . . . .
16
5
BSYNC Signal - one byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
6
BSYNC Signal - two byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
7
SCI Word Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
8
SCI Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
9
SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
10
Two SCI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
11
Two SDI Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
12
Two SDI Bytes Separated By an SCI Operation. . . . . . . . . . . . . . . . . . . . . . .
24
13
Data Flow of VS1011e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
14
User’s Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
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1
VS1011 E
1. LICENSE
License
MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and Thomson.
Note: if you enable Layer I and Layer II decoding, you are liable for any patent issues that may
arise from using these formats. Joint licensing of MPEG 1.0 / 2.0 Layer III does not cover all patents
pertaining to layers I and II.
2
Disclaimer
All properties and figures are subject to change.
3
Definitions
B Byte, 8 bits.
b Bit.
Ki “Kibi” = 210 = 1024 (IEC 60027-2).
Mi “Mebi” = 220 = 1048576 (IEC 60027-2).
VS DSP VLSI Solution’s DSP core.
W Word. In VS DSP, instruction words are 32-bit and data words are 16-bit wide.
Version 1.04,
2007-10-08
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VS1011 E
VS1011e4. CHARACTERISTICS & SPECIFICATIONS
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Solution
4
Characteristics & Specifications
4.1
Absolute Maximum Ratings
Parameter
Analog Positive Supply
Digital Positive Supply
Current at Any Digital Output
Voltage at Any Digital Input
Operating Temperature
Functional Operating Temperature
Storage Temperature
1
Symbol
AVDD
DVDD
Min
-0.3
-0.3
DGND-1.0
-30
-40
-65
Max
3.6
3.6
±50
DVDD+1.01
+85
+95
+150
Unit
V
V
mA
V
◦C
◦C
◦C
Must not exceed 3.6 V
4.2
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Analog and Digital Ground 1
Positive Analog
Positive Digital
Input Clock Frequency
Input Clock Frequency, with clock doubler
Internal Clock Frequency
Master Clock Duty Cycle
Symbol
AGND DGND
AVDD
DVDD
XTALI
XTALI
CLKI
Min
-40
2.5
2.3
24
12
242
40
Typ
0.0
2.7
2.5
24.576
12.288
24.576
50
Max
+85
3.6
3.6
26
13
26
60
Unit
◦C
V
V
V
MHz
MHz
MHz
%
1
Must be connected together as close to the device as possible for latch-up immunity.
The maximum sample rate that can be played with correct speed is CLKI/512.
Thus, if CLKI is 24 MHz, 48 kHz sample rate is played 2.5% off-key.
2
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VS1011 E
VS1011e4. CHARACTERISTICS & SPECIFICATIONS
y
Solution
4.3
Analog Characteristics
Unless otherwise noted: AVDD=2.5..3.6V, DVDD=2.3..3.6V, TA=-40..+85◦ C, XTALI=12..13MHz,
internal Clock Doubler active. DAC tested with 1307.894 Hz full-scale output sinewave, measurement
bandwidth 20..20000 Hz, analog output load: LEFT to GBUF 30Ω, RIGHT to GBUF 30Ω.
Parameter
DAC Resolution
Total Harmonic Distortion
Dynamic Range (DAC unmuted, A-weighted)
S/N Ratio (full scale signal)
Interchannel Isolation (Cross Talk)
Interchannel Isolation (Cross Talk), with GBUF
Interchannel Gain Mismatch
Frequency Response
Full Scale Output Voltage (Peak-to-peak)
Deviation from Linear Phase
Analog Output Load Resistance
Analog Output Load Capacitance
1
2
Symbol
THD
IDR
SNR
AOLR
Min
70
50
Typ
18
0.1
90
85
75
40
-0.5
-0.1
1.4
1.61
16
302
Max
0.2
0.5
0.1
2.0
5
100
Unit
bits
%
dB
dB
dB
dB
dB
dB
Vpp
◦
Ω
pF
3.2 volts can be achieved with +-to-+ wiring for mono difference sound.
AOLR may be much lower, but below Typical distortion performance may be compromised.
4.4 Power Consumption
Average current tested with an MPEG 1.0 Layer III 128 kbit/s sample and generated sine, output at full
volume, XTALI = 12.288 MHz, internal clock doubler enabled, DVDD = 2.5 V, AVDD = 2.7 V.
Parameter
Power Supply Consumption AVDD, Reset
Power Supply Consumption DVDD, Reset
Power Supply Consumption AVDD, sine test, 30Ω
Power Supply Consumption AVDD, sine test, 30Ω + GBUF
Power Supply Consumption DVDD, sine test
Power Supply Consumption AVDD, no load
Power Supply Consumption AVDD, output load 30Ω
Power Supply Consumption AVDD, 30Ω + GBUF
Power Supply Consumption DVDD
Version 1.04,
2007-10-08
Min
Typ
0.5
1
20
39
8
6
10
16
16
Max
30
30
50
17
Unit
µA
µA
mA
mA
mA
mA
mA
mA
mA
10
VLSI
VS1011 E
VS1011e4. CHARACTERISTICS & SPECIFICATIONS
y
Solution
4.5
Digital Characteristics
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage at IO = -2.0 mA
Low-Level Output Voltage at IO = 2.0 mA
Input Leakage Current
SPI Input Clock Frequency 2
Rise time of all output pins, load = 50 pF
1
2
Symbol
Must not exceed 3.6V
Value for SCI reads. SCI and SDI writes allow
Min
0.7×DVDD
-0.2
0.7×DVDD
Typ
Max
DVDD+0.31
0.3×DVDD
0.3×DVDD
1.0
-1.0
CLKI
6
50
Unit
V
V
V
V
µA
MHz
ns
CLKI
4 .
4.6 Switching Characteristics - Boot Initialization
Parameter
XRESET active time
XRESET inactive to software ready
Power on reset, rise time of DVDD
1
Symbol
Min
2
Max
500001
10
Unit
XTALI
XTALI
V/s
DREQ rises when initialization is complete. You should not send any data or commands before that.
Version 1.04,
2007-10-08
11
VLSI
VS1011e
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Solution
5
VS1011 E
5. PACKAGES AND PIN DESCRIPTIONS
Packages and Pin Descriptions
5.1
Packages
Both LPQFP-48 and BGA-49 are lead (Pb) free and also RoHS compliant packages. RoHS is a short
name of Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical
and electronic equipment.
SOIC-28 is a lead-free RoHS-compliant package starting from VS1011e.
5.1.1
LQFP-48
48
1
Figure 1: Pin Configuration, LQFP-48.
LQFP-48 package dimensions are at http://www.vlsi.fi/ .
Version 1.04,
2007-10-08
12
VLSI
Solution
VS1011e
y
5.1.2
VS1011 E
5. PACKAGES AND PIN DESCRIPTIONS
BGA-49
A1 BALL PAD CORNER
1
2
4
3
5
6
7
A
D
7.00
0.80 TYP
C
4.80
B
E
F
G
1.10 REF
1.10 REF
0.80 TYP
4.80
7.00
TOP VIEW
Figure 2: Pin Configuration, BGA-49.
BGA-49 package dimensions are at http://www.vlsi.fi/ .
5.1.3
SOIC-28
28
27
26
25
24
23
22
21
20
19
18
17
16
15
9
10
11
12
13
14
SOIC − 28
1
2
3
4
5
6
7
8
Figure 3: Pin Configuration, SOIC-28.
SOIC-28 package dimensions are at http://www.vlsi.fi/ .
Version 1.04,
2007-10-08
13
VLSI
VS1011e
y
Solution
5.2
5.2.1
LQFP-48 and BGA-49 Pin Descriptions
XRESET
DGND0
DVDD0
DREQ
GPIO22 / DCLK1
GPIO32 / SDATA1
XDCS4 / BSYNC1
DVDD1
DGND1
XTALO
XTALI
DVDD2
DGND2
DGND3
DGND4
XCS4
SCLK2
SI2
SO
TEST
GPIO0 / SPIBOOT2,3
GPIO12
AGND0
AVDD0
RIGHT
AGND1
AGND2
GBUF
AVDD1
RCAP
AVDD2
LEFT
AGND3
2
3
4
5. PACKAGES AND PIN DESCRIPTIONS
Pin Descriptions
Pin Name
1
VS1011 E
LQFP48 Pin
3
4
6
8
9
10
13
14
16
17
18
19
20
21
22
23
28
29
30
32
33
34
37
38
39
40
41
42
43
44
45
46
47
BGA49
Ball
B1
D2
D3
E2
E1
F2
E3
F3
F4
G3
E4
G4
F5
G5
F6
G6
D6
E7
D5
C6
C7
B6
C5
B5
A6
B4
A5
C4
A4
B3
A3
B2
A2
Pin
Type
DI
PWR
PWR
DO
DI
DI
DI
PWR
PWR
AO
AI
PWR
PWR
PWR
PWR
DI
DI
DI
DO3
DI
DIO
DIO
PWR
PWR
AO
PWR
PWR
AO
PWR
AIO
PWR
AO
PWR
Function
active low asynchronous reset, schmitt-triggered
digital ground
digital power supply
data request, input bus
general purpose IO 2 / serial input data bus clock
general purpose IO 3 / serial data input
data chip select / byte sync, connect to DVDD if not used
digital power supply
digital ground
crystal output
crystal input
digital power supply
digital ground (in BGA-49, DGND2, 3, 4 conn. together)
digital ground
digital ground
chip select input (active low)
clock for serial bus
serial input
serial output, active when XCS=0, regardless of XRESET
reserved for test, connect to DVDD
general purpose IO 0, use 100 kΩ pull-down resistor
general purpose IO 1
analog ground, low-noise reference
analog power supply
right channel output
analog ground
analog ground
common buffer for headphones
analog power supply
filtering capacitance for reference
analog power supply
left channel output
analog ground
First pin function is active in New Mode, latter in Compatibility Mode.
If not used, use 100 kΩ pull-down resistor.
Use 100 kΩ pull-down resistor. If pull-up is used instead, SPI Boot is tried. See Chapter 9.4 for details.
If not used, use 100 kΩ pull-up resistor.
Pin types:
Type Description
DI
Digital input, CMOS Input Pad
DO
Digital output, CMOS Input Pad
DIO
Digital input/output
DO3 Digital output, CMOS Tri-stated Output Pad
Type
AI
AO
AIO
PWR
Description
Analog input
Analog output
Analog input/output
Power supply pin
In BGA-49, no-connect balls are A1, A7, B7, C1, C2, C3, D1, D4, D7, E5, E6, F1, F7, G1, G2, G7.
In LQFP-48, no-connect pins are 1, 2, 5, 7, 11, 12, 15, 24, 25, 26, 27, 31, 35, 36, 48.
Version 1.04,
2007-10-08
14
VLSI
VS1011e
y
Solution
5.2.2
VS1011 E
5. PACKAGES AND PIN DESCRIPTIONS
SOIC-28 Pin Descriptions
Pin Name
Pin
DREQ
GPIO22 / DCLK1
GPIO32 / SDATA1
XDCS4 / BSYNC1
DVDD1
DGND1
XTALO
XTALI
DVDD2
DGND2
XCS4
SCLK2
SI2
SO
TEST
GPIO0 / SPIBOOT2,3
GPIO12
AGND0
AVDD0
RIGHT
AGND2
RCAP
AVDD2
LEFT
AGND3
XRESET
DGND0
DVDD0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin
Type
DO
DIO
DI
DI
PWR
PWR
CLK
CLK
PWR
PWR
DI
DI
DI
DO3
DI
DIO
DIO
PWR
PWR
AO
PWR
AIO
PWR
AO
PWR
DI
PWR
PWR
Function
data request, input bus
serial input data bus clock
serial data input
byte synchronization signal
digital power supply
digital ground
crystal output
crystal input
digital power supply
digital ground
chip select input (active low)
clock for serial bus
serial input
serial output, active when XCS=0, regardless of XRESET
reserved for test, connect to DVDD
general purpose IO 0, use 100 kΩ pull-down resistor
general purpose IO 1
analog ground
analog power supply
right channel output
analog ground
filtering capacitance for reference
analog power supply
left channel output
analog ground
active low asynchronous reset
digital ground
digital power supply
1
First pin function is active in New Mode, latter in Compatibility Mode.
If not used, use 100 kΩ pull-down resistor.
3 Use 100 kΩ pull-down resistor. If pull-up is used instead, SPI Boot is tried. See Chapter 9.4 for details.
4 If not used, use 100 kΩ pull-up resistor.
2
Pin types:
Type
DI
DO
DIO
DO3
Version 1.04,
Description
Digital input, CMOS Input Pad
Digital output, CMOS Input Pad
Digital input/output
Digital output, CMOS Tri-stated Output Pad
2007-10-08
Type
AI
AO
AIO
PWR
Description
Analog input
Analog output
Analog input/output
Power supply pin
15
VLSI
VS1011e
y
Solution
6
VS1011 E
6. CONNECTION DIAGRAM, LQFP-48
Connection Diagram, LQFP-48
Figure 4: Typical Connection Diagram Using LQFP-48.
The common buffer GBUF can be used for common voltage (1.23 V) for earphones. This will eliminate
the need for large isolation capacitors on line outputs, and thus the audio output pins from VS1011e may
be connected directly to the earphone connector.
If GBUF is not used, LEFT and RIGHT must be provided with 1-100 µF capacitors depending on load
resistance.
Note: This connection assumes SM SDINEW is active (see Chapter 8.6.1). If also SM SDISHARE is
used, xDCS should have a pull-up resistor (see Chapter 7.2.1).
Version 1.04,
2007-10-08
16
VLSI
VS1011e
y
Solution
7
VS1011 E
7. SPI BUSES
SPI Buses
7.1
General
The SPI Bus - that was originally used in some Motorola devices - has been used for both VS1011e’s
Serial Data Interface SDI (Chapters 7.3 and 8.4) and Serial Control Interface SCI (Chapters 7.5 and 8.5).
7.2
SPI Bus Pin Descriptions
7.2.1
VS1002 Native Modes (New Mode)
These modes are active on VS1011e when SM SDINEW is set to 1. DCLK and SDATA are not used for
data transfer and they can be used as general-purpose I/O pins (GPIO2 and GPIO3). BSYNC function
changes to data interface chip select (XDCS).
SDI Pin
XDCS
SCI Pin
XCS
SCK
SI
-
7.2.2
SO
Description
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. If SM SDISHARE is 1, pin
XDCS is not used, but the signal is generated internally by inverting
XCS.
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
Serial input. If a chip select is active, SI is sampled on the rising CLK edge.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
VS1001 Compatibility Mode
This mode is active when SM SDINEW is 0 (default). In this mode, DCLK, SDATA and BSYNC are
active.
Version 1.04,
2007-10-08
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VLSI
VS1011e
y
Solution
SDI Pin
-
SCI Pin
XCS
BSYNC
DCLK
SCK
SDATA
-
SI
SO
7.3
7.3.1
VS1011 E
7. SPI BUSES
Description
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. There is no chip select for SDI, which
is always active.
SDI data is synchronized with a rising edge of BSYNC.
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
Serial input. SI is sampled on the rising SCK edge, if XCS is low.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
Serial Protocol for Serial Data Interface (SDI)
General
The serial data interface operates in slave mode so the DCLK signal must be generated by an external
circuit.
Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 8.6).
VS1011e assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or
LSb first, depending of contents of SCI MODE (Chapter 8.6).
7.3.2
SDI in VS1002 Native Modes (New Mode)
In VS1002 native modes (which are available also in VS1011e), byte synchronization is achieved by
XDCS (or XCS if SM SDISHARE is 1). The state of XDCS (or XCS) may not change while a data
byte transfer is in progress. To always maintain data synchronization even if there may be glitches in
the boards using VS1011e, it is recommended to turn XDCS (or XCS) every now and then, for instance
once after every flash data block or a few kilobytes, just to keep sure the host and VS1011e are in sync.
For new designs, using VS1002 native modes are recommended, as they are easier to implement than
BSYNC generation.
7.3.3
SDI in VS1001 Compatibility Mode
When VS1011e is running in VS1001 compatibility mode, a BSYNC signal must be generated to ensure
correct bit-alignment of the input bitstream. The first DCLK sampling edge (rising or falling, depending
on selected polarity), during which the BSYNC is high, marks the first bit of a byte (LSB, if LSB-first
Version 1.04,
2007-10-08
18
VLSI
Solution
VS1011 E
VS1011e
y
7. SPI BUSES
BSYNC
SDATA
D7
D6
D5
D4
D3
D2
D1
D0
DCLK
Figure 5: BSYNC Signal - one byte transfer.
order is used, MSB, if MSB-first order is used). If BSYNC is ’1’ when the last bit is received, the receiver
stays active and next 8 bits are also received.
BSYNC
SDATA
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
DCLK
Figure 6: BSYNC Signal - two byte transfer.
Using VS1001 compatibility mode in new designs is strongly discouraged.
7.4 Data Request Pin DREQ
The DREQ pin/signal is used to signal if VS1011e’s FIFO is capable of receiving data. If DREQ is high,
VS1011e can take at least 32 bytes of SDI data or one SCI command. When these criteria are not met,
DREQ is turned low, and the sender should stop transferring new data.
Because of a 32-byte safety area, the sender may send upto 32 bytes of SDI data at a time without
checking the status of DREQ, making controlling VS1011e easier for low-speed microcontrollers.
Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ should
only be used to decide whether to send more bytes. It should not abort a transmission that has already
started.
Note: In VS10XX products upto VS1002, DREQ was only used for SDI. In VS1011e DREQ is also used
to tell the status of SCI.
7.5 Serial Protocol for Serial Command Interface (SCI)
7.5.1
General
The serial bus protocol for the Serial Command Interface SCI (Chapter 8.5) consists of an instruction
byte, address byte and one 16-bit data word. Each read or write operation can read or write a single
register. Data bits are read at the rising clock edge, so the user should update data at the falling clock
edge. Bytes are always sent MSb firrst.
Version 1.04,
2007-10-08
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VLSI
Solution
VS1011e
y
VS1011 E
7. SPI BUSES
The operation is specified by an 8-bit instruction opcode. The supported instructions are read and write.
See table below.
Name
READ
WRITE
Instruction
Opcode
Operation
0000 0011 Read data
0000 0010 Write data
Note: VS1011e sets DREQ low after each SCI operation. The duration depends on the operation. It is
not allowed to start a new SCI/SDI operation before DREQ is high again.
Version 1.04,
2007-10-08
20
VLSI
Solution
VS1011e
y
7.5.2
VS1011 E
7. SPI BUSES
SCI Read
XCS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
0
0
0
0
0
0
1
1
0
0
0
30 31
SCK
3
SI
instruction (read)
2
1
0
don’t care
0
data out
address
15 14
SO
0
0
0
0
0
0
0
0
0
0
0
0
0
don’t care
0
0
1
0
0
X
execution
DREQ
Figure 7: SCI Word Read
VS1011e registers are read by the following sequence, as shown in Figure 7. First, XCS line is pulled
low to select the device. Then the READ opcode (0x3) is transmitted via the SI line followed by an 8-bit
word address. After the address has been read in, any further data on SI is ignored. The 16-bit data
corresponding to the received address will be shifted out onto the SO line.
XCS should be driven high after data has been shifted out.
DREQ is driven low for a short while when in a read operation by the chip. This is a very short time and
doesn’t require special user attention.
7.5.3
SCI Write
XCS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
SI
0
0
0
0
0
0
1
0
0
0
0
SO
0
0
0
0
0
0
0
30 31
SCK
3
instruction (write)
0
0
0
0
2
1
0
15 14
1
data out
address
0
0
X
0
0
0
0
0
0
0
0
0 X
execution
DREQ
Figure 8: SCI Word Write
VS1011e registers are written to using the following sequence, as shown in Figure 8. First, XCS line is
pulled low to select the device. Then the WRITE opcode (0x2) is transmitted via the SI line followed by
an 8-bit word address.
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2007-10-08
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VLSI
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Solution
VS1011 E
7. SPI BUSES
After the word has been shifted in and the last clock has been sent, XCS should be pulled high to end the
WRITE sequence.
After the last bit has been sent, DREQ is driven low for the duration of the register update, marked “execution” in the figure. The time varies depending on the register and its contents (see table in Chapter 8.6
for details). If the maximum time is longer than what it takes from the microcontroller to feed the next
SCI command or SDI byte, it is not allowed to finish a new SCI/SDI operation before DREQ has risen
up again.
7.6
SPI Timing Diagram
tWL
tXCSS
tWH
tXCSH
XCS
0
1
14
15
30
16
31
tXCS
SCK
SI
tH
tSU
SO
tZ
tV
tDIS
Figure 9: SPI Timing Diagram.
Symbol
tXCSS
tSU
tH
tZ
tWL
tWH
tV
tXCSH
tXCS
tDIS
1
Min
5
-26
2
0
2
2
Max
2 (+ 25ns1 )
-26
2
10
Unit
ns
ns
XTALI cycles
ns
XTALI cycles
XTALI cycles
XTALI cycles
ns
XTALI cycles
ns
25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance.
Note: As tWL and tWH, as well as tH require at least 2 clock cycles, the maximum speed for the SPI
bus that can be used for read operations is 1/6 of VS1011e’s external clock speed XTALI. For write
operations maximum speed is 1/4 of XTALI.
Note: Negative numbers mean that the signal can change in different order from what is shown in the
diagram.
Version 1.04,
2007-10-08
22
VLSI
VS1011e
y
Solution
7.7
7.7.1
VS1011 E
7. SPI BUSES
SPI Examples with SM SDINEW and SM SDISHARED set
Two SCI Writes
SCI Write 1
SCI Write 2
XCS
0
1
2
3
30
31
1
0
32
33
61
62
63
2
1
0
SCK
SI
0
0
0
0
X
0
0
X
DREQ up before finishing next SCI write
DREQ
Figure 10: Two SCI Operations.
Figure 10 shows two consecutive SCI operations. Note that xCS must be raised to inactive state between
the writes. Also DREQ must be respected as shown in the figure.
7.7.2
Two SDI Bytes
SDI Byte 1
SDI Byte 2
XCS
0
1
2
3
7
6
5
4
6
7
8
9
1
0
7
6
13
14
15
2
1
0
SCK
3
SI
5
X
DREQ
Figure 11: Two SDI Bytes.
SDI data is synchronized with a raising edge of xCS as shown in Figure 11. However, every byte doesn’t
need separate synchronization.
Version 1.04,
2007-10-08
23
VLSI
Solution
VS1011e
y
7.7.3
VS1011 E
7. SPI BUSES
SCI Operation in Middle of Two SDI Bytes
SDI Byte
SDI Byte
SCI Operation
XCS
0
1
7
8
9
39
40
41
7
6
46
47
1
0
SCK
7
SI
6
5
1
0
0
5
X
0
DREQ high before end of next transfer
DREQ
Figure 12: Two SDI Bytes Separated By an SCI Operation.
Figure 12 shows how an SCI operation is embedded in between SDI operations. xCS edges are used to
synchronize both SDI and SCI. Remember to respect DREQ as shown in the figure.
Version 1.04,
2007-10-08
24
VLSI
VS1011e
y
Solution
8
VS1011 E
8. FUNCTIONAL DESCRIPTION
Functional Description
8.1
Main Features
VS1011e is based on a proprietary digital signal processor, VS DSP. It contains all the code and data
memory needed for MPEG, WAV PCM and WAV IMA ADPCM audio decoding, together with serial
interfaces, a multirate stereo audio DAC and analog output amplifiers and filters.
VS1011e can play all MPEG 1.0, and 2.0 layer I, II and III files, as well as MPEG 2.5 layer III files, with
all sample rates and bitrates, including variable bitrate (VBR) for layer III. Note, that decoding of layers
I and II must be activated separately.
8.2 Supported Audio Codecs
Mark
+
?
8.2.1
Conventions
Description
Format is supported
Format exists but is not supported
Format not tested
Format doesn’t exist
Supported MP1 (MPEG layer I) Formats
MPEG 1.0:
Samplerate / Hz
48000
44100
32000
32
+
+
+
64
+
+
+
96
+
+
+
128
+
+
+
160
+
+
+
Bitrate / kbit/s
192 224 256 288
+
+
+
+
+
+
+
+
+
+
+
+
320
+
+
+
352
+
+
+
384
+
+
+
416
+
+
+
448
+
+
+
32
?
?
?
48
?
?
?
56
?
?
?
64
?
?
?
80
?
?
?
96
?
?
?
Bitrate / kbit/s
112 128 144
?
?
?
?
?
?
?
?
?
160
?
?
?
176
?
?
?
192
?
?
?
224
?
?
?
256
?
?
?
MPEG 2.0:
Samplerate / Hz
24000
22050
16000
Version 1.04,
2007-10-08
25
VLSI
VS1011e
y
Solution
8.2.2
VS1011 E
8. FUNCTIONAL DESCRIPTION
Supported MP2 (MPEG layer II) Formats
MPEG 1.0:
Samplerate / Hz
48000
44100
32000
32
+
+
+
48
+
+
+
56
+
+
+
64
+
+
+
80
+
+
+
96
+
+
+
Bitrate / kbit/s
112 128 160
+
+
+
+
+
+
+
+
+
192
+
+
+
224
+
+
+
256
+
+
+
320
+
+
+
384
+
+
+
8
+
+
+
16
+
+
+
24
+
+
+
32
+
+
+
40
+
+
+
48
+
+
+
Bitrate / kbit/s
56
64
80
+
+
+
+
+
+
+
+
+
96
+
+
+
112
+
+
+
128
+
+
+
144
+
+
+
160
+
+
+
MPEG 2.0:
Samplerate / Hz
24000
22050
16000
8.2.3
Supported MP3 (MPEG layer III) Formats
MPEG 1.01 :
Samplerate / Hz
48000
44100
32000
32
+
+
+
40
+
+
+
48
+
+
+
56
+
+
+
64
+
+
+
80
+
+
+
Bitrate / kbit/s
96
112 128
+
+
+
+
+
+
+
+
+
160
+
+
+
192
+
+
+
224
+
+
+
256
+
+
+
320
+
+
+
8
+
+
+
16
+
+
+
24
+
+
+
32
+
+
+
40
+
+
+
48
+
+
+
Bitrate / kbit/s
56
64
80
+
+
+
+
+
+
+
+
+
96
+
+
+
112
+
+
+
128
+
+
+
144
+
+
+
160
+
+
+
8
+
+
+
16
+
+
+
24
+
+
+
32
+
+
+
40
+
+
+
48
+
+
+
Bitrate / kbit/s
56
64
80
+
+
+
+
+
+
+
+
+
96
+
+
+
112
+
+
+
128
+
+
+
144
+
+
+
160
+
+
+
MPEG 2.01 :
Samplerate / Hz
24000
22050
16000
MPEG 2.51 :
Samplerate / Hz
12000
11025
8000
1
Also all variable bitrate (VBR) formats are supported.
Note: 24.0 MHz internal clock (24.0 MHz external clock or 12.0 MHz external clock with clockdoubler) is enough for VS1011e to be able to decode all bitrates and sample rates with bass enhancer and treble control active.
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8.2.4
VS1011 E
8. FUNCTIONAL DESCRIPTION
Supported RIFF WAV Formats
The most common RIFF WAV subformats are supported.
Format
0x01
0x02
0x03
0x06
0x07
0x10
0x11
0x15
0x16
0x30
0x31
0x3b
0x3c
0x40
0x41
0x50
0x55
0x64
0x65
Version 1.04,
Name
PCM
ADPCM
IEEE FLOAT
ALAW
MULAW
OKI ADPCM
IMA ADPCM
DIGISTD
DIGIFIX
DOLBY AC2
GSM610
ROCKWELL ADPCM
ROCKWELL DIGITALK
G721 ADPCM
G728 CELP
MPEG
MPEGLAYER3
G726 ADPCM
G722 ADPCM
2007-10-08
Supported
+
+
+
-
Comments
16 and 8 bits, any sample rate ≤ 48kHz
Any sample rate ≤ 48kHz
For supported MP3 modes, see Chapter 8.2.3
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Solution
8.3
VS1011 E
8. FUNCTIONAL DESCRIPTION
Data Flow of VS1011e
SDI
Bitstream
FIFO
AIADDR = 0
User
Application
AIADDR != 0
MP1 / MP2 /
MP3 / WAV /
ADPCM
decode
SB_AMPLITUDE=0
Bass
enhancer
SB_AMPLITUDE!=0
ST_AMPLITUDE=0
Treble
enhancer
ST_AMPLITUDE!=0
Volume
control
Audio
FIFO
SCI_VOL
512 stereo
samples
L
S.rate.conv.
R
and DAC
Figure 13: Data Flow of VS1011e.
First, depending on the audio data, MPEG or WAV audio is received and decoded from the SDI bus.
After decoding, if SCI AIADDR is non-zero, application code is executed from the address pointed to
by that register. For more details, see VS10XX Application Note: User Applications.
Then data may be sent to the Bass and Treble Enhancer depending on SCI BASS.
After that the signal is fed to the volume control unit, which also copies the data to the Audio FIFO.
The Audio FIFO holds the data, which is read by the Audio interrupt (Chapter 10.9.1) and fed to the
sample rate converter and DACs. The size of the audio FIFO is 512 stereo (2×16-bit) samples, or 2 KiB.
The sample rate converter converts all different sample rates to CLKI/512 and feeds the data to the DAC,
which in order creates a stereo in-phase analog signal. This signal is then forwarded to the earphone
amplifier.
8.4 Serial Data Interface (SDI)
The serial data interface is meant for transferring compressed MP3 audio data as well as WAV data.
Also several different tests may be activated through SDI as described in Chapter 9.
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Solution
8.5
VS1011 E
8. FUNCTIONAL DESCRIPTION
Serial Control Interface (SCI)
The serial control interface is compatible with the SPI bus specification. Data transfers are always 16
bits. VS1011e is controlled by writing and reading the registers of the interface.
The main controls of the control interface are:
•
•
•
•
•
8.6
Reg
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
control of the operation mode, clock, and builtin effects
access to status information and header data
access to encoded digital data
uploading user programs
feeding input data
SCI Registers
Type
rw
rw
rw
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
Reset
0
0x2C3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCI registers, prefix SCI
Time1 Abbrev[bits]
Description
4
70 CLKI
MODE
Mode control
40 CLKI STATUS
Status of VS1011e
2100 CLKI BASS
Built-in bass/treble enhancer
80 XTALI CLOCKF
Clock freq + multiplier
40 CLKI DECODE TIME Decode time in seconds
3200 CLKI AUDATA
Misc. audio data
80 CLKI WRAM
RAM write/read
80 CLKI WRAMADDR
Base address for RAM write/read
- HDAT0
Stream header data 0
- HDAT1
Stream header data 1
3200 CLKI2 AIADDR
Start address of application
2100 CLKI VOL
Volume control
2
50 CLKI
AICTRL0
Application control register 0
50 CLKI2 AICTRL1
Application control register 1
2
50 CLKI
AICTRL2
Application control register 2
50 CLKI2 AICTRL3
Application control register 3
1
This is the worst-case time that DREQ stays low after writing to this register. The user may choose to
skip the DREQ check for those register writes that take less than 100 clock cycles to execute.
2
In addition, the cycles spent in the user application routine must be counted.
3
Firmware changes the value of this register immediately to 0x28, and in less than 100 ms to 0x20.
4
When mode register write specifies a software reset the worst-case time is 9600 XTALI cycles.
Note that if DREQ is low when an SCI write is done, DREQ also stays low after SCI write processing.
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8.6.1
VS1011 E
8. FUNCTIONAL DESCRIPTION
SCI MODE (RW)
SCI MODE is used to control operation of VS1011e.
Bit
0
Name
SM DIFF
Function
Differential
1
SM LAYER12
Allow MPEG layers I & II
2
SM RESET
Soft reset
3
SM OUTOFWAV
Jump out of WAV decoding
4
SM SETTOZERO1
set to zero
5
SM TESTS
Allow SDI tests
6
SM STREAM
Stream mode
7
SM SETTOZERO2
set to zero
8
SM DACT
DCLK active edge
9
SM SDIORD
SDI bit order
10
SM SDISHARE
Share SPI chip select
11
SM SDINEW
VS1002 native SPI modes
12
SM SETTOZERO3
set to zero
13
SM SETTOZERO4
set to zero
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
normal in-phase audio
left channel inverted
no
yes
no reset
reset
no
yes
right
wrong
not allowed
allowed
no
yes
right
wrong
rising
falling
MSb first
MSb last
no
yes
no
yes
right
wrong
right
wrong
When SM DIFF is set, the player inverts the left channel output. For a stereo input this creates a virtual
surround, and for a mono input this effectively creates a differential left/right signal.
SM LAYER12 determines whether it is allowed to decode MPEG 1 and 2 layers I and II in addition to
layer III. If you enable Layer I and Layer II decoding, you are liable for any patent issues that may
arise. Joint licensing of MPEG 1.0 / 2.0 Layer III does not cover all patents pertaining to layers I and II.
By setting SM RESET to 1, the player is software reset. This bit clears automatically.
When the user decoding a WAV file wants to get out of the file without playing it to the end, set
SM OUTOFWAV, and send zeros to VS1002e until SM OUTOFWAV is again zero. If the user doesn’t
want to check SM OUTOFWAV, send 128 zeros.
If SM TESTS is set, SDI tests are allowed. For more details on SDI tests, look at Chapter 9.7.
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VS1011 E
8. FUNCTIONAL DESCRIPTION
SM STREAM activates VS1011e’s stream mode. In this mode, data should be sent with as even intervals
as possible (and preferable with data blocks of less than 512 bytes), and VS1011e makes every attempt
to keep its input buffer half full by changing its playback speed upto 5%. For best quality sound, the
average speed error should be within 0.5%, the bitrate should not exceed 160 kbit/s and VBR should not
be used. For details, see VS10XX Application Note: Streaming.
SM DACT defines the active edge of data clock for SDI. If clear data is read at the rising edge, and if set
data is read at the falling edge.
When SM SDIORD is clear, bytes on SDI are sent as a default MSb first. By setting SM SDIORD, the
user may reverse the bit order for SDI, i.e. bit 0 is received first and bit 7 last. Bytes are, however, still
sent in the default order. This register bit has no effect on the SCI bus.
Setting SM SDISHARE makes SCI and SDI share the same chip select, as explained in Chapter 7.2, if
also SM SDINEW is set.
Setting SM SDINEW will activate VS1002 native serial modes as described in Chapters 7.2.1 and 7.3.2.
8.6.2
SCI STATUS (RW)
SCI STATUS contains information on the current status of VS1011e and lets the user shutdown the chip
without audio glitches.
Name
SS VER
SS APDOWN2
SS APDOWN1
SS AVOL
Bits
6:4
3
2
1:0
Description
Version
Analog driver powerdown
Analog internal powerdown
Analog volume control
SS VER is 0 for VS1001, 1 for VS1011, 2 for VS1002 and VS1011e, and 3 for vs1003.
You can use SCI MODE to distinguish between VS1002 and VS1011e. After reset VS1011e has
SM SDINEW=0, while VS1002 has SM SDINEW=1.
SS APDOWN2 controls analog driver powerdown. Normally this bit is controlled by the system firmware.
However, if the user wants to powerdown VS1011e with a minimum power-off transient, turn this bit to
1, then wait for at least a few milliseconds before activating reset.
SS APDOWN1 controls internal analog powerdown. This bit is meant to be used by the system firmware
only.
SS AVOL is the analog volume control: 0 = -0 dB, 1 = -6 dB, 3 = -12 dB. This register is meant to be
used automatically by the system firmware only.
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8.6.3
VS1011 E
8. FUNCTIONAL DESCRIPTION
SCI BASS (RW)
Name
ST AMPLITUDE
ST FREQLIMIT
SB AMPLITUDE
SB FREQLIMIT
Bits
15:12
11:8
7:4
3:0
Description
Treble Control in 1.5 dB steps (-8..7, 0 = off)
Lower limit frequency in 1000 Hz steps (0..15)
Bass Enhancement in 1 dB steps (0..15, 0 = off)
Lower limit frequency in 10 Hz steps (2..15)
The Bass Enhancer VSBE is a powerful bass boosting DSP algorithm, which tries to take the most out
of the users earphones without causing clipping.
VSBE is activated when SB AMPLITUDE is non-zero. SB AMPLITUDE should be set to the user’s
preferences, and SB FREQLIMIT to roughly 1.5 times the lowest frequency the user’s audio system can
reproduce. For example setting SCI BASS to 0x00f6 will have 15 dB enhancement below 60 Hz.
Note: Because VSBE tries to avoid clipping, it gives the best bass boost with dynamical music material,
or when the playback volume is not set to maximum. It also does not create bass: the source material
must have some bass to begin with.
Treble Control VSTC is activated when ST AMPLITUDE is non-zero. For example setting SCI BASS
to 0x7a00 will have 10.5 dB treble enhancement at and above 10 kHz.
Bass Enhancer uses about 2.1 MIPS and Treble Control 1.2 MIPS at 44100 Hz sample rate. Both can be
on simultaneously.
8.6.4
SCI CLOCKF (RW)
SCI CLOCKF is used to tell if the input clock XTALI is running at something else than 24.576 MHz.
ALI
XTALI is set in 2 kHz steps. Thus, the formula for calculating the correct value for this register is XT
2000
(XTALI is in Hz). Values may be between 0..32767, although hardware limits the highest allowed speed.
Also, with speeds lower than 24.576 MHz all sample rates are no longer available. For example with
24 MHz clock 48 kHz is played 2.5% off-key.
Setting the MSB of SCI CLOCKF to 1 activates internal clock-doubling when the sample rate is next
configured.
Note: SCI CLOCKF must be set before beginning decoding audio data; otherwise the sample rate will
not be set correctly.
Example 1: For a 26 MHz clock the value would be
26000000
2000
= 13000.
Example 2: For a 13 MHz external clock and using internal clock-doubling for a 26 MHz internal
frequency, the value would be 0x8000 + 13000000
= 39268.
2000
Example 3: For a 24.576 MHz clock the value would be either 24576000
= 12288, or just the default
2000
value 0. For this clock frequency, SCI CLOCKF doesn’t need to be set.
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8.6.5
VS1011 E
8. FUNCTIONAL DESCRIPTION
SCI DECODE TIME (RW)
When decoding correct data, current decoded time is shown in this register in full seconds.
The user may change the value of this register. However, in that case the new value should be written
twice.
SCI DECODE TIME is reset at every software reset.
8.6.6
SCI AUDATA (RW)
When decoding correct data, the current sample rate and number of channels can be found in bits 15:1
and 0 of SCI AUDATA, respectively. Bits 15:1 contain the sample rate divided by two, and bit 0 is 0 for
mono data and 1 for stereo. Writing to this register will change the sample rate on the run to the number
given.
Example: 44100 Hz stereo data reads as 0xAC45 (44101).
Example: 11025 Hz mono data reads as 0x2B10 (11024).
Example: Writing 0xAC80 sets sample rate to 44160 Hz, stereo mode does not change.
8.6.7
SCI WRAM (RW)
SCI WRAM is used to upload application programs and data to instruction and data RAMs. The start
address must be initialized by writing to SCI WRAMADDR prior to the first write/read of SCI WRAM.
As 16 bits of data can be transferred with one SCI WRAM write/read, and the instruction word is 32 bits
long, two consecutive writes/reads are needed for each instruction word. The byte order is big-endian
(i.e. MSBs first). After each full-word write/read, the internal pointer is autoincremented.
8.6.8
SCI WRAMADDR (RW)
SCI WRAMADDR is used to set the program address and memory bus for following SCI WRAM
writes/reads.
SM WRAMADDR
Start. . . End
0x1380. . . 0x13FF
0x4780. . . 0x47FF
0x8030. . . 0x84FF
0xC000. . . 0xFFFF
Version 1.04,
2007-10-08
Dest. addr.
Start. . . End
0x1380. . . 0x13FF
0x0780. . . 0x07FF
0x0030. . . 0x04FF
0xC000. . . 0xFFFF
Bits/
Word
16
16
32
16
Description
X data RAM
Y data RAM
Instruction RAM
I/O
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Solution
VS1011e
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8.6.9
VS1011 E
8. FUNCTIONAL DESCRIPTION
SCI HDAT0 and SCI HDAT1 (R)
Bit
HDAT1[15:5]
HDAT1[4:3]
Function
syncword
ID
HDAT1[2:1]
layer
HDAT1[0]
protect bit
HDAT0[15:12]
HDAT0[11:10]
bitrate
sample rate
HDAT0[9]
pad bit
HDAT0[8]
HDAT0[7:6]
private bit
mode
HDAT0[5:4]
HDAT0[3]
extension
copyright
HDAT0[2]
original
HDAT0[1:0]
emphasis
Value
2047
3
2
1
0
3
2
1
0
1
0
3
2
1
0
1
0
3
2
1
0
1
0
1
0
3
2
1
0
Explanation
stream valid
ISO 11172-3 MPG 1.0
ISO 13818-3 MPG 2.0 (1/2-rate)
MPG 2.5 (1/4-rate)
MPG 2.5 (1/4-rate)
I
II
III
reserved
No CRC
CRC protected
see bitrate table
reserved
32/16/ 8 kHz
48/24/12 kHz
44/22/11 kHz
additional slot
normal frame
not defined
mono
dual channel
joint stereo
stereo
see ISO 11172-3
copyrighted
free
original
copy
CCITT J.17
reserved
50/15 microsec
none
When read, SCI HDAT0 and SCI HDAT1 contain header information that is extracted from MPEG
stream being currently being decoded. Right after resetting VS1011e, 0 is automatically written to both
registers, indicating no data has been found yet.
The “sample rate” field in SCI HDAT0 is interpreted according to the following table:
“sample rate”
3
2
1
0
ID=3 / Hz
32000
48000
44100
ID=2 / Hz
16000
24000
22050
ID=0,1 / Hz
8000
12000
11025
The “bitrate” field in HDAT0 is read according to the following table:
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“bitrate”
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Layer I
ID=3 ID=0,1,2
kbit/s
forbidden forbidden
448
256
416
224
384
192
352
176
320
160
288
144
256
128
224
112
192
96
160
80
128
64
96
56
64
48
32
32
-
Layer II
ID=3 ID=0,1,2
kbit/s
forbidden forbidden
384
160
320
144
256
128
224
112
192
96
160
80
128
64
112
56
96
48
80
40
64
32
56
24
48
16
32
8
-
VS1011 E
8. FUNCTIONAL DESCRIPTION
Layer III
ID=3 ID=0,1,2
kbit/s
forbidden forbidden
320
160
256
144
224
128
192
112
160
96
128
80
112
64
96
56
80
48
64
40
56
32
48
24
40
16
32
8
-
When decoding a WAV file, SPI HDAT0 and SPI HDAT1 read as 0x7761 and 0x7665, respectively.
8.6.10
SCI AIADDR (RW)
SCI AIADDR indicates the start address of the application code written earlier with SCI WRAMADDR
and SCI WRAM registers. If no application code is used, this register should not be initialized, or it
should be initialized to zero. For more details, see VS10XX Application Note: User Applications.
8.6.11
SCI VOL (RW)
SCI VOL is a volume control for the player hardware. For each channel, a value in the range of 0..254
may be defined to set its attenuation from the maximum volume level (in 0.5 dB steps). The left channel
value is then multiplied by 256 and the values are added. Thus, maximum volume is 0 and total silence
is 0xFEFE.
Example: for a volume of -2.0 dB for the left channel and -3.5 dB for the right channel: (4*256) + 7
= 0x407. Note, that at startup volume is set to full volume. Resetting the software does not reset the
volume setting.
Note: Setting SCI VOL to 0xFFFF will activate analog powerdown mode.
8.6.12
SCI AICTRL[x] (RW)
SCI AICTRL[x] registers ( x=[0 .. 3] ) can be used to access the user’s application program.
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Solution
9
VS1011 E
9. OPERATION
Operation
9.1
Clocking
VS1011e operates on a single, nominally 24.576 MHz fundamental frequency master clock. This clock
can be generated by external circuitry (connected to pin XTALI) or by the internal clock crystal interface
(pins XTALI and XTALO). Also, 12.288 MHz external clock can be internally clock-doubled to 24.576
MHz. This clock is sufficient to support a high quality audio output for all codecs, sample rates and
bitrates, with bass and treble enhancers.
9.2
Hardware Reset
When the XRESET -signal is driven low, VS1011e is reset and all the control registers and internal states
are set to the initial values. XRESET-signal is asynchronous to any external clock. The reset mode
doubles as a full-powerdown mode, where both digital and analog parts of VS1011e are in minimum
power consumption stage, and where clocks are stopped. Also XTALO and XTALI are grounded.
After a hardware reset (or at power-up), the user should set such basic software registers as SCI VOL
for volume (and SCI CLOCKF if the input clock is anything else than 24.576 MHz) before starting
decoding.
9.3 Software Reset
In some cases the decoder software has to be reset. This is done by activating bit 2 in SCI MODE register
(Chapter 8.6.1). Then wait for at least 2 µs, then look at DREQ. DREQ will stay down for at least 6000
clock cycles, which means an approximate 250 µs delay if VS1011e is run at 24.576 MHz. After DREQ
is up, you may continue playback as usual.
If you want to make sure VS1011e doesn’t cut the ending of low-bitrate data streams and you want to do
a software reset, it is recommended to feed 2048 zeros to the SDI bus after the file and before the reset.
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Solution
9.4
VS1011 E
9. OPERATION
SPI Boot
If GPIO0 is set with a pull-up resistor to 1 at boot time, VS1011e tries to boot from external SPI memory.
SPI boot redefines the following pins:
Normal Mode
GPIO0
GPIO1
DREQ
GPIO2
SPI Boot Mode
xCS
CLK
MOSI
MISO
The memory has to be an SPI Bus Serial EEPROM with 16-bit addresses (i.e. at least 1 KiB). The serial
speed used by VS1011e is 490 kHz with the nominal 24.576 MHz clock. The first three bytes in the
memory have to be 0x50, 0x26, 0x48. The exact record format is explained in the Application Notes for
VS10XX.
If SPI boot succeeds, SCI MODE is left with value 0x0800.
9.5
Play/Decode
This is the normal operation mode of VS1011e. SDI data is decoded. Decoded samples are converted to
analog domain by the internal DAC. If no decodable data is found, SCI HDAT0 and SCI HDAT1 are set
to 0 and analog outputs are muted.
When there is no input for decoding, VS1011e goes into idle mode (lower power consumption than
during decoding) and actively monitors the serial data input for valid data.
9.6 Feeding PCM data
VS1011e can be used as a PCM decoder by sending to it a WAV file header. If the length sent in the
WAV file is 0 or 0xFFFFFFF, VS1011e will stay in PCM mode indefinitely. 8-bit linear and 16-bit linear
audio is supported in mono or stereo.
9.7 SDI Tests
There are several test modes in VS1011e, which allow the user to perform memory tests, SCI bus tests,
and several different sine wave tests.
All tests are started in a similar way: VS1011e is hardware reset, SM TESTS is set, and then a test
command is sent to the SDI bus. Each test is started by sending a 4-byte special command sequence,
followed by 4 zeros. The sequences are described below.
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9.7.1
VS1011 E
9. OPERATION
Sine Test
Sine test is initialized with the 8-byte sequence 0x53 0xEF 0x6E n 0 0 0 0, where n defines the sine test
to use. n is defined as follows:
Name
F s Idx
S
Bits
7:5
4:0
n bits
Description
Sample rate index
Sine skip speed
F s Idx
0
1
2
3
4
5
6
7
Fs
44100 Hz
48000 Hz
32000 Hz
22050 Hz
24000 Hz
16000 Hz
11025 Hz
12000 Hz
The frequency of the sine to be output can now be calculated from F = F s ×
S
128 .
Example: Sine test is activated with value 126, which is 0b01111110. Breaking n to its components,
F s Idx = 0b011 = 3 and thus F s = 22050Hz. S = 0b11110 = 30, and thus the final sine frequency
30
≈ 5168Hz.
F = 22050Hz × 128
To exit the sine test, send the sequence 0x45 0x78 0x69 0x74 0 0 0 0.
Note: Sine test signals go through the digital volume control, so it is possible to test channels separately.
9.7.2
Pin Test
Pin test is activated with the 8-byte sequence 0x50 0xED 0x6E 0x54 0 0 0 0. This test is meant for chip
production testing only.
9.7.3
Memory Test
Memory test mode is initialized with the 8-byte sequence 0x4D 0xEA 0x6D 0x54 0 0 0 0. After this
sequence, wait for 200000 clock cycles. The result can be read from the SCI register SCI HDAT0, and
’one’ bits are interpreted as follows:
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Solution
VS1011e
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Bit(s)
15
14:7
6
5
4
3
2
1
0
Mask
0x8000
0x0040
0x0020
0x0010
0x0008
0x0004
0x0002
0x0001
0x807f
VS1011 E
9. OPERATION
Meaning
Test finished
Unused
Mux test succeeded
Good I RAM
Good Y RAM
Good X RAM
Good I ROM
Good Y ROM
Good X ROM
All ok
Memory tests overwrite the current contents of the RAM memories.
9.7.4
SCI Test
Sci test is initialized with the 8-byte sequence 0x53 0x70 0xEE n 0 0 0 0, where n − 48 is the register
number to test. The content of the given register is read and copied to SCI HDAT0. If the register to be
tested is HDAT0, the result is copied to SCI HDAT1.
Example: if n is 48, contents of SCI register 0 (SCI MODE) is copied to SCI HDAT0.
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10.1
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10. VS1011E REGISTERS
VS1011e Registers
Who Needs to Read This Chapter
User software is required when a user wishes to add some own functionality like DSP effects to VS1011e.
However, most users of VS1011e don’t need to worry about writing their own code, or about this chapter,
including those who only download software plug-ins from VLSI Solution’s Web site.
10.2
The Processor Core
VS DSP is a 16/32-bit DSP processor core that also had extensive all-purpose processor features. VLSI
Solution’s free VSKIT Software Package contains all the tools and documentation needed to write, simulate and debug Assembly Language or Extended ANSI C programs for the VS DSP processor core.
VLSI Solution also offers a full Integrated Development Environment VSIDE for full debug capabilities.
10.3 VS1011e Memory Map
VS1011e’s Memory Map is shown in Figure 14.
10.4 SCI Registers
SCI registers described in Chapter 8.6 can be found here between 0xC000..0xC00F. In addition to these
registers, there is one in address 0xC010, called SPI CHANGE.
Reg
0xC010
Type
r
Name
SPI CH WRITE
SPI CH ADDR
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0
SPI registers, prefix SPI
Abbrev[bits]
Description
CHANGE[5:0]
Last SCI access address.
Bits
4
3:0
SPI CHANGE bits
Description
1 if last access was a write cycle.
SPI address of last access.
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Instruction (32−bit)
X (16−bit)
Y (16−bit)
System Vectors
User
Instruction
RAM
Stack
Stack
0000
0030
0098
X DATA
RAM
Y DATA
RAM
0500
0000
0030
0098
0500
0780
0780
User
Space
0800
0C00
0800
0C00
1380
1380
User
Space
1400
1400
1800
1800
4000
4000
Instruction
ROM
X DATA
ROM
Y DATA
ROM
6000
6000
7000
7000
C000
C000
Hardware
Register
Space
C100
C100
Figure 14: User’s Memory Map.
10.5 Serial Data Registers
Reg
0xC011
0xC012
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0
SDI registers, prefix SER
Abbrev[bits]
Description
DATA
Last received 2 bytes, big-endian.
DREQ[0]
DREQ pin control.
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10. VS1011E REGISTERS
DAC Registers
Reg
0xC013
0xC014
0xC015
0xC016
Type
rw
rw
rw
rw
Reset
0
0
0
0
DAC registers, prefix DAC
Abbrev[bits]
Description
FCTLL
DAC frequency control, 16 LSbs.
FCTLH[4:0]
Clock doubler + DAC frequency control MSbs.
LEFT
DAC left channel PCM value.
RIGHT
DAC right channel PCM value.
Every fourth clock cycle an internal 26-bit counter is added to by (DAC FCTLH & 15) × 65536 +
DAC FCTLL. Whenever this counter overflows, values from DAC LEFT and DAC RIGHT are read and
a DAC interrupt is generated.
If DAC FCTL[4] is 1, the internal clock doubler is activated.
10.7
GPIO Registers
Reg
0xC017
0xC018
0xC019
Type
rw
r
rw
Reset
0
0
0
GPIO registers, prefix GPIO
Abbrev[bits]
Description
DDR[3:0]
Direction.
IDATA[3:0]
Values read from the pins.
ODATA[3:0]
Values set to the pins.
GPIO DIR is used to set the direction of the GPIO pins. 1 means output. GPIO ODATA remembers its
values even if a GPIO DIR bit is set to input.
GPIO registers don’t generate interrupts.
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10.8
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10. VS1011E REGISTERS
Interrupt Registers
Reg
0xC01A
0xC01B
0xC01C
0xC01D
Type
rw
w
w
rw
Reset
0
0
0
0
Interrupt registers, prefix INT
Abbrev[bits]
Description
ENABLE[2:0]
Interrupt enable.
GLOB DIS[-]
Write to add to interrupt counter.
GLOB ENA[-]
Write to subtract from interript counter.
COUNTER[4:0]
Interrupt counter.
INT ENABLE controls the interrupts. The control bits are as follows:
Name
INT EN SDI
INT EN SCI
INT EN DAC
Bits
2
1
0
INT ENABLE bits
Description
Enable Data interrupt.
Enable SCI interrupt.
Enable DAC interrupt.
Note: It may take upto 6 clock cycles before changing INT ENABLE has any effect.
Writing any value to INT GLOB DIS adds one to the interrupt counter INT COUNTER and effectively
disables all interrupts. It may take upto 6 clock cycles before writing to this register has any effect.
Writing any value to INT GLOB ENA subtracts one from the interrupt counter (unless INT COUNTER
already was 0). If the interrupt counter becomes zero, interrupts selected with INT ENABLE are restored. An interrupt routine should always write to this register as the last thing it does, because interrupts automatically add one to the interrupt counter, but subtracting it back to its initial value is the
responsibility of the user. It may take upto 6 clock cycles before writing this register has any effect.
By reading INT COUNTER the user may check if the interrupt counter is correct or not. If the register
is not 0, interrupts are disabled.
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10.9
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10. VS1011E REGISTERS
System Vector Tags
The System Vector Tags are tags that may be replaced by the user to take control over several decoder
functions.
10.9.1
AudioInt, 0x20
Normally contains the following VS DSP assembly code:
jmpi DAC_INT_ADDRESS,(i6)+1
The user may, at will, replace the instruction with a jmpi command to gain control over the audio
interrupt.
10.9.2
SciInt, 0x21
Normally contains the following VS DSP assembly code:
jmpi SCI_INT_ADDRESS,(i6)+1
The user may, at will, replace the instruction with a jmpi command to gain control over the SCI interrupt.
10.9.3
DataInt, 0x22
Normally contains the following VS DSP assembly code:
jmpi SDI_INT_ADDRESS,(i6)+1
The user may, at will, replace the instruction with a jmpi command to gain control over the SDI interrupt.
10.9.4
UserCodec, 0x0
Normally contains the following VS DSP assembly code:
jr
nop
If the user wants to take control away from the standard decoder, the first instruction should be replaced
with an appropriate j command to user’s own code.
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Unless the user is feeding MP3 data at the same time, the system activates the user program in less than
1 ms. After this, the user should steal interrupt vectors from the system, and insert user programs.
10.10
System Vector Functions
The System Vector Functions are pointers to some functions that the user may call to help implementing
his own applications.
10.10.1 WriteIRam(), 0x2
VS DSP C prototype:
void WriteIRam(register i0 u int16 *addr, register a1 u int16 msW, register a0 u int16 lsW);
This is the only supported way to write to the User Instruction RAM. This is because Instruction RAM
cannot be written when program control is in RAM. Thus, the actual implementation of this function is
in ROM, and here is simply a tag to that routine.
10.10.2
ReadIRam(), 0x4
VS DSP C prototype:
u int32 ReadIRam(register i0 u int16 *addr);
This is the only supported way to read from the User Instruction RAM. This is because Instruction RAM
cannot be read when program control is in RAM. Thus, the actual implementation of this function is in
ROM, and here is simply a tag to that routine.
A1 contains the MSBs and a0 the LSBs of the result.
10.10.3
DataBytes(), 0x6
VS DSP C prototype:
u int16 DataBytes(void);
If the user has taken over the normal operation of the system by switching the pointer in UserCodec
to point to his own code, he may read data from the Data Interface through this and the following two
functions.
This function returns the number of data bytes that can be read.
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10.10.4 GetDataByte(), 0x8
VS DSP C prototype:
u int16 GetDataByte(void);
Reads and returns one data byte from the Data Interface. This function will wait until there is enough
data in the input buffer.
10.10.5 GetDataWords(), 0xa
VS DSP C prototype:
void GetDataWords(register i0 y u int16 *d, register a0 u int16 n);
Read n data byte pairs and copy them in big-endian format (first byte to MSBs) to d. This function will
wait until there is enough data in the input buffer.
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VS1011 E
11. VS1011 VERSION CHANGES
VS1011 Version Changes
This chapter describes changes between different generations of VS1011.
11.1
Changes Between VS1011b and VS1011e, 2005-07-13
• Faster decoding: all codecs, bitrates and bass + treble controls can be used at CLKI = 24 MHz.
• Register SCI BASS now also has a treble control (Chapter 8.6.3). Loudness plugin not required.
• Can play IMA ADPCM in mono and stereo (Chapter 8.2.4).
• Register space can now be written to with SCI WRAM (Chapter 8.6.7).
• Memory and register space can now be read from with SCI WRAM (Chapter 8.6.7).
• Added optional playback of MPEG 1 and 2 layers I and II. (Chapters 8.2.2, 8.2.1 and 8.6.1).
• SPI Boot added (Chapter 9.4).
• MPEG 1, 2 and 2.5 layer III decoding more robust against bit errors.
• MPEG 2.5 decoding compatibility enhanced.
• DREQ goes down during SCI operations. (Chapter 7.4).
• DREQ goes down during memory test. (Chapter 7.4).
• In VS1011e the SS VER field in SCI STATUS is 2.
• Also SOIC-28 is now a lead-free RoHS-complian package.
11.2
Migration Checklist from VS1011b to VS1011e, 2005-07-13
• The SS VER field in SCI STATUS is 2. You can use SCI STATUS and SCI MODE to distinguish between VS1002 and VS1011e. VS1011b has SS VER=1, SM SDINEW=0, VS1011e has
SS VER=2, SM SDINEW=0, and VS1002 has SS VER=2, SM SDINEW=1.
• Use built-in bass enhancer and treble control instead of the Loudness plugin. The loudness plugin
works, but the builtin controls are much faster.
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12. DOCUMENT VERSION CHANGES
Document Version Changes
This chapter describes the most important changes to this document.
12.1
Version 1.04 for VS1011e, 2007-10-08
• Starting from VS1011e also SOIC-28 is a RoHS-compliant lead-free package.
12.2
Version 1.03 for VS1011e, 2005-09-05
• Production version, no longer preliminary
12.3
Version 1.02 for VS1011e, 2005-07-13
• New features for VS1011e added (see Chapter 11.1).
12.4
Version 1.01 for VS1011b, 2004-11-19
• Removed non-existing SCIMB POWERDOWN bit.
• Added SOIC-28 package to Chapters 5.1.3 and 5.2.2.
12.5
Version 1.00 for VS1011b, 2004-10-22
• Fully qualified values to tables in Chapter 4.
• Reassigned BGA-49 balls for pins DVDD2, DGND2 and DGND3 in Chapter 5.2.
12.6
Version 0.71 for VS1011, 2004-07-20
• Added instructions to add 100 kΩ pull-down resistor to unused GPIOs to Chapter 5.2.
12.7 Version 0.70 for VS1011, 2004-05-13
• Removed SM JUMP.
12.8 Version 0.62 for VS1011, 2004-03-24
• Rewrote and clarified Chapter 8.2, Supported Audio Codecs.
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13. CONTACT INFORMATION
Contact Information
VLSI Solution Oy
Entrance G, 2nd floor
Hermiankatu 8
FIN-33720 Tampere
FINLAND
Fax: +358-3-3140-8288
Phone: +358-3-3140-8200
Email: [email protected]
URL: http://www.vlsi.fi/
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