DATA SHEET AZ10E111 AZ100E111 ARIZONA MICROTEK, INC. 1:9 Differential Clock Driver FEATURES • • • • • • • • • Low Skew Guaranteed Skew Spec Differential Design Enable VBB Output Extended 100E VEE Range of -4.2V to -5.46V 75kΩ Internal Input Pulldown Resistors Direct Replacement for Motorola MC10EL111 & MC100EL111 Manufactured Under License By Lucent Technologies PACKAGE AVAILABILITY SUFFIX FN DESCRIPTION Plastic 28 PLCC DESCRIPTION The AZ10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or single-ended if the VBB output is used. The signal is fanned-out to 9 identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all QN outputs HIGH. The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot-to-lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met, both sides of the differential output must be terminated into 50Ω , even if only one side is used. In most applications all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. Q0 Q0N Q1 VCCO Q1N Q2 Q2N 25 24 23 22 21 20 19 LOGIC SYMBOL VEE 26 18 Q3 ENN 27 17 Q3N IN 28 16 Q4 15 VCCO Q0 Pinout: 28-Lead PLCC (Top View) VCC 1 INN 2 14 Q4N VBB 3 13 Q5 NC 4 12 Q5N 5 Q8N 6 Q8 7 8 Q7N VCCO 9 Q7 10 11 Q6N Q6 QON Q1 Q1N Q2 Q2N IN INN Q3 Q3N ENN Q4 Q4N Q5 Q5N PIN DESCRIPTION PIN IN, INN ENN Q0, Q0N-Q8N, Q8 6/99 FUNCTION Differential Input Pair Enable Differential Outputs VBB Output Q6 Q6N Q7 Q7N VBB Q8 Q8N AZ10E111 AZ100E111 DC Characteristics (VEE = 10E(-4.94V to -5.46V),100E(-4.2V to -5.46V); VCC = VCCO = GND) -40°C 0°C 25°C 85°C Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Reference Voltage 10E -1.43 -1.30 -1.38 -1.27 -1.35 -1.25 -1.31 -1.19 VBB V 100E -1.38 -1.26 -1.38 -1.26 -1.38 -1.26 -1.38 -1.26 Input HIGH Current 150 150 150 150 IIH µA Power Supply 10E 48 60 48 60 48 60 48 60 IEE mA Current 100E 48 60 48 60 48 60 55 69 VPP (DC) Input Sensitivity 50 50 50 50 mV VCMR Common Mode Range -1.6 -0.4 -1.6 -0.4 -1.6 -0.4 -1.6 -0.4 V 1. Differential input voltage required to obtain a full ECL swing on the outputs. 2. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP(min). Symbol Cond 1 2 AC Characteristics (VEE = 10E(-4.94V to -5.46V),100E(-4.2V to -5.46V); VCC = VCCO = GND) -40°C 0°C 25°C 85°C Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Propagation Delay tPLH to Output IN (Diff) 380 680 460 560 480 580 510 610 tPHL IN (SE) 280 780 410 610 430 630 460 660 ps Enable 400 900 450 850 450 850 450 850 Disable 400 900 450 850 450 850 450 850 tS Setup Time ENN to IN 250 0 200 0 200 0 200 0 ps th Hold Time IN to ENN 50 -200 0 -200 0 -200 0 -200 ps tR Release Time ENN to IN 350 100 300 100 300 100 300 100 ps tskew Within-Device Skew 25 75 25 50 25 50 25 50 ps VPP (AC) Minimum Input Swing 250 250 250 250 mV tr / tf Rise/Fall Time 250 450 650 275 375 600 275 375 600 275 375 600 ps 1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 3. Enable is defined as the propagation delay from the 50% point of a negative transition on ENN to the 50% point of a positive transition on Q (or a negative transition on QN). Disable is defined as the propagation delay from the 50% point of a positive transition on ENN to the 50% point of a negative transition on Q (or a positive transition on QN). 4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 5. The setup time is the minimum time that ENN must be asserted prior to the next transition of IN/INN to prevent an output response greater than ±75 mV to that IN/INN transition (see Figure 1). 6. The hold time is the minimum time that ENN must remain asserted after a negative going IN or a positive going INN to prevent an output response greater than ±75 mV to that IN/INN transition (see Figure 2). 7. The release time is the minimum time that ENN must be deasserted prior to the next IN/INN transition to ensure an output response that meets the specified IN to Q propagation delay and output transition times (see Figure 3). 8. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the E111, as a differential input as low as 50 mV will still produce full ECL levels at the output. Symbol ARIZONA MICROTEK, INC. Cond 1 2 3 3 5 6 7 4 8 225 E. FIRST ST., SUITE 107 •MESA, AZ 85201-6700 •(480) 962-5881 •FAX (480) 890-2541 http://www.azmicrotek.com