Configuration Devices for ® February 2002, ver. 12.1 Features Data Sheet ■ ■ ■ ■ ■ ■ ■ ■ Altera Corporation DS-EPROM-12.1 SRAM-Based LUT Devices Serial device family for configuring APEXTM II, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), MercuryTM, ACEX® 1K, and FLEX® (FLEX 6000, FLEX 10KE, and FLEX 10KA) devices Easy-to-use 4-pin interface to APEX II, APEX 20K, Mercury, ACEX, and FLEX devices Low current during configuration and near-zero standby current 5.0-V and 3.3-V operation Software design support with the Altera® Quartus® II and MAX+PLUS® II development systems for Windows-based PCs as well as Sun SPARCstation, and HP 9000 Series 700/800 Programming support with Altera’s Master Programming Unit (MPU) and programming hardware from Data I/O, BP Microsystems, and other manufacturers Available in compact plastic packages (see Figures 1 and 2) – 8-pin plastic dual in-line package (PDIP) – 20-pin plastic J-lead chip carrier (PLCC) package – 32-pin plastic thin quad flat pack (TQFP) package – 100-pin plastic thin quad flat pack (TQPF) package – 88-pin Ultra FineLine BGATM package EPC2 device has reprogrammable Flash configuration memory – 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface – Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 – ISP circuitry is compatible with IEEE Std. 1532 for EPC2 configuration device – Supports programming through Serial Vector Format Files (.svf), JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), and the MAX+PLUS II software via the MasterBlasterTM, ByteBlasterMVTM, or BitBlasterTM download cable – nINIT_CONF pin allows a JTAG instruction to initiate device configuration – Can be programmed with Programmer Object Files (.pof) for EPC1 and EPC1441 devices – Available in 20-pin PLCC and 32-pin TQFP packages 1 Configuration Devices for SRAM-based LUT Devices Data Sheet ■ f EPC4, EPC8, and EPC16 configuration devices have reprogrammable Flash configuration memory with density up to 16,000,000 or 32,000,000 bits with compression feature in these devices. For detailed information on configuration devices, refer to the Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet. DATA 1 8 VCC N.C. DATA N.C. VCC N.C. 3 2 1 20 19 18 DATA N.C. N.C. N.C. VCC N.C. N.C. Note (1) N.C. Figure 1. EPC1, EPC1441, EPC1213, EPC1064, & EPC1064V Package Pin-Out Diagrams 32 31 30 29 28 27 26 25 24 N.C. 1 N.C. DCLK 2 23 VCC N.C. 3 22 N.C. DCLK 4 VCC N.C. 4 21 N.C. N.C. 5 17 N.C. N.C. 5 20 N.C. 6 16 N.C. N.C. 6 19 N.C. 4 5 GND OE 8 14 13 N.C. N.C. 8 N.C. 9 10 11 12 9 10 11 12 13 14 15 17 16 N.C. N.C. nCS N.C. 18 N.C. 7 N.C. OE N.C. N.C. GND 15 nCS 7 N.C. N.C. N.C. nCASC (2) (2) nCASC VCC 6 N.C. 7 3 nCS 2 OE GND DCLK N.C. 8-Pin PDIP 20-Pin PLCC 32-Pin TQFP EPC1 EPC1441 EPC1213 EPC1064 EPC1064V EPC1 EPC1441 EPC1213 EPC1064 EPC1064V EPC1441 EPC1064 EPC1064V Notes to Figure 1: (1) (2) 2 EPC1, EPC1441, EPC1213, and EPC1064 devices are one-time programmable devices. ISP programming is not available in these devices because they do not have JTAG pins. The nCASC pin is available on EPC1 and EPC1213 devices. On the EPC1064, EPC1064V, and EPC1441 devices, it is a reserved pin and should not be connected. Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet TMS VCC TDO TMS N.C. TDO N.C. N.C. VCC 27 26 25 24 N.C. DCLK 2 23 VPP VCCSEL 3 22 N.C. N.C. 6 16 N.C. N.C. 6 19 N.C. N.C. 7 15 N.C. OE 7 18 OE 8 14 12 13 N.C. 8 17 15 16 10 11 12 13 14 32-Pin TQFP 20-Pin PLCC Functional Description 9 N.C. VPPSEL nINIT_CONF nINIT_CONF 10 11 TDI 9 VPPSEL nCASC N.C. N.C. 20 TDI 5 GND N.C. N.C. N.C. nCS 17 N.C. N.C. 5 nCASC 21 nCS 4 GND N.C. VCCSEL 1 30 29 28 VPP 4 2 32 31 1 20 19 18 DCLK 3 DATA TCK N.C. DATA TCK Figure 2. EPC2 Package Pin-Out Diagrams With SRAM-based devices, configuration data must be reloaded each time the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based APEX II, APEX 20K, Mercury, ACEX, and FLEX devices. Table 1 lists Altera configuration devices. Table 1. Configuration Devices Device Altera Corporation Description EPC16 16,000,000 × 1 bit with 3.3-V operation EPC8 8,000,000 × 1 bit with 3.3-V operation EPC4 4,000,000 × 1-bit device with 3.3-V operation EPC2 1,695,680 × 1-bit device with 5.0-V or 3.3-V operation EPC1 1,046,496 × 1-bit device with 5.0-V or 3.3-V operation EPC1441 440,800 × 1-bit device with 5.0-V or 3.3-V operation EPC1213 212,942 × 1-bit device with 5.0-V operation EPC1064 65,536 × 1-bit device with 5.0-V operation EPC1064V 65,536 × 1-bit device with 3.3-V operation 3 Configuration Devices for SRAM-based LUT Devices Data Sheet Table 2 lists the configuration device used with each APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device. Table 2. Configuration Devices Used for Each APEX II, APEX 20K, Mercury, ACEX & FLEX Device (Part 1 of 2) Family APEX II (1.5 V) Mercury (1.8 V) Device Data Size EPC1064 EPC1213 EPC1441 EPC1 EPC2 EPC4 EPC8 EPC16 (bits) EPC1064V EP2A15 4,714,000 3 1 1 EP2A25 6,276,000 4 1 1 EP2A40 9,612,000 6 1 1 EP2A70 17,390,000 11 EP1M120 1,297,000 1 1 1 1 EP1M350 1 4,383,000 3 1 1 APEX 20KC EP20K200C (1.8 V) EP20K400C 1,964,000 2 1 1 1 3,901,000 3 1 1 1 EP20K600C 5,564,000 4 1 1 EP20K1000C 8,938,000 6 1 1 1 APEX 20KE EP20K30E (2.5 V) EP20K60E APEX 20K (2.5 V) ACEX 1K (2.5 V) 4 347,000 1 1 1 1 641,000 1 1 1 1 1 EP20K100E 1,009,000 1 1 1 1 1 EP20K160E 1,523,000 1 1 1 1 EP20K200E 1,964,000 2 1 1 1 EP20K300E 2,733,000 2 1 1 1 EP20K400E 3,901,000 3 1 1 1 EP20K600E 5,564,000 4 1 1 EP20K1000E 8,938,000 6 1 1 EP20K1500E 12,011,000 8 1 1 EP20K100 985,000 EP20K200 EP20K400 1 1 1 1 1 1 1,950,000 2 1 1 1 3,878,000 3 1 1 1 1 1 1 1 1 EP1K10 178,000 1 1 EP1K30 470,000 1 1 1 1 1 EP1K50 785,000 1 1 1 1 1 EP1K100 1,337,000 1 1 1 1 Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Table 2. Configuration Devices Used for Each APEX II, APEX 20K, Mercury, ACEX & FLEX Device (Part 2 of 2) Family Device Data Size EPC1064 EPC1213 EPC1441 EPC1 EPC2 EPC4 EPC8 EPC16 (bits) EPC1064V FLEX 10KE EPF10K30E (2.5 V) EPF10K50E 470,000 1 1 1 1 1 785,000 1 1 1 1 1 EPF10K50S 785,000 1 1 1 1 1 EPF10K100B 1,2000,000 1 1 1 1 EPF10K100E 1,336,000 1 1 1 1 EPF10K130E 1,840,000 2 1 1 1 EPF10K200E 2,757,000 2 1 1 1 EPF10K200S 2,757,000 2 1 1 1 1 1 1 1 1 1 402,000 1 1 1 1 1 1 EPF10K50V 621,000 1 1 1 1 1 1 EPF10K100A 1,200,000 1 1 1 1 1 EPF10K130V 1,582,000 1 EPF10K250A 3,292,000 FLEX 10KA EPF10K10A (3.3 V) EPF10K30A 120,000 FLEX 10K (5.0 V) FLEX 6000/A (3.3 V) FLEX 8000A (5.0 V) 1 1 1 1 1 1 1 EPF10K10 118,000 1 1 1 1 1 1 EPF10K20 231,000 1 1 1 1 1 1 EPF10K30 376,000 1 1 1 1 1 1 EPF10K40 498,000 1 1 1 1 1 EPF10K50 621,000 1 1 1 1 1 EPF10K70 893,000 1 1 1 1 1 EPF10K100 1,200,000 1 1 1 1 EPF6010A 260,000 1 1 EPF6016 (5.0 V) / EPF6016A 260,000 1 1 EPF6024A 398,000 1 1 EPF8282A / EPF8282AV (3.3 V) 40,000 1 1 1 1 EPF8452A 64,000 1 1 1 1 EPF8636A 96,000 1 1 1 EPF8820A 128,000 1 1 1 EPF81188A 192,000 1 1 1 EPF1500A 250,000 1 1 Altera Corporation 1 1 2 5 Configuration Devices for SRAM-based LUT Devices Data Sheet Figure 3 shows the configuration device block diagram. Figure 3. Configuration Device Block Diagram PLD (except FLEX 8000) Configuration Using an EPC2, EPC1, or EPC1441 (1) DCLK CLK ENA nRESET Oscillator Oscillator Control Address Counter Address Decode Logic nCASC (2) nCS OE (3) Error Detection Circuitry EPROM Array DATA Shift Register DATA FLEX 8000 Device Configuration Using an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V DCLK CLK ENA nRESET Address Counter Address Decode Logic nCASC (2) nCS OE EPROM Array DATA Shift Register DATA Notes to Figure 3: (1) (2) (3) 6 Do not use EPC2 devices to configure FLEX 6000 devices. The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC2, EPC1, and EPC1213 devices support data cascading. The OE pin is a bidirectional open-drain pin. Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Device Configuration The control signals for configuration devices—nCS, OE, and DCLK— interface directly with APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device control signals. All APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices can be configured by a configuration device without requiring an external intelligent controller. The configuration device’s OE and nCS pins control the tri-state buffer on the DATA output pin, and enable the address counter (and the oscillator in EPC4, EPC 8, EPC16, EPC2, EPC1, and EPC1441 devices). When OE is driven low, the configuration device resets the address counter and tristates its DATA pin. The nCS pin controls the output of the configuration device. If nCS is held high after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven low, the counter and DATA output pin are enabled. When OE is driven low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of nCS. 1 The EPC4, EPC8, EPC16, EPC2, EPC1, and EPC1441 devices determine the operation mode and whether the APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, or FLEX 6000 protocols should be used when OE is driven high. When the configuration device has driven out all of its data and has driven nCASC low, the device tri-states the DATA pin to avoid contention with other configuration devices. The EPC2 device allows the user to initiate configuration of the PLD via an additional pin, nINIT_CONF, that can be tied to the nCONFIG pin of the PLD(s) to be configured. A JTAG instruction causes the EPC4, EPC8, EPC16, and EPC2 device to drive nINIT_CONF low, which in turn pulls nCONFIG low. The EPC4, EPC8, EPC16, and EPC2 device then drives nINIT_CONF high to start configuration. When the JTAG state machine exits this state, nINIT_CONF releases nCONFIG and configuration is initiated. 1 Altera Corporation An EPC4, EPC8, EPC16, and EPC2 device can be programmed with a POF generated for an EPC1 or EPC1441 device, however, an EPC2 device cannot configure FLEX 6000 or FLEX 8000 devices. An EPC1 device can be programmed using a POF generated for an EPC1441 device. 7 Configuration Devices for SRAM-based LUT Devices Data Sheet APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration APEX 20K, Mercury, ACEX 1K, and FLEX devices can be configured with EPC4, EPC8, EPC16, EPC2, EPC1, or EPC1441 devices. FLEX 6000 devices can be configured with EPC1 or EPC1441 devices. APEX II devices can be configured with EPC2, EPC4, EPC8, and EPC16 devices. The EPC4, EPC8, EPC16, EPC2, EPC1, or EPC1441 device stores configuration data in its EPROM array and serially clocks data out with an internal oscillator. The OE, nCS, and DCLK pins supply the control signals for the address counter and the output tri-state buffer. The configuration device sends a serial bitstream of configuration data to its DATA pin, which is routed to the DATA0 or DATA input pin on the LUT-based PLD device. Figure 4 shows an LUT-based PLD configured with a single EPC2, EPC1, or EPC1441 device. 8 Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Figure 4. ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, or Mercury Device Configured with an EPC2, EPC1, or EPC1441 Configuration Device Note (1) APEX II, ACEX 1K, Mercury, APEX 20KC, APEX 20K & FLEX 10K Devices VCC (2) LUT-Based PLD (3) VCC VCC (2) (2) DCLK DATA OE nCS nINIT_CONF (4) DCLK DATA0 nSTATUS CONF_DONE nCONFIG nCEO MSEL0 MSEL1 Configuration Device (5) nCE GND GND VCC APEX 20KE Devices (2) APEX 20KE PLD (7) VCCINT (6) VCC (2) (2) Configuration Device DCLK DATA OE nCS nINIT_CONF (4) DCLK DATA0 nSTATUS CONF_DONE nCONFIG (8) nCEO MSEL0 MSEL1 GND (5) nCE GND Notes to Figure 4: (1) (2) (3) (4) (5) (6) (7) (8) Do not use EPC2 devices to configure FLEX 6000 devices. The pull-up resistor should be connected to the same supply voltage as the configuration device. All pull-up resistors are 1 kΩ. APEX 20KE pull up resistors are 10 kΩ. The OE, nCS, and nINIT_CONF pins on EPC2, EPC4, EPC8, and EPC16 devices have internal, user-configurable 1-kΩ pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The Quartus II software uses the internal pull-up resistors by default. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files. The diagram shows an APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device, which has MSEL0 and MSEL1 tied to ground. For FLEX 6000 devices, MSEL is tied to ground, and the DATA0 pin is named DATA. EPC4, EPC8, EPC16, and EPC2 configuration devices cannot be used with FLEX 6000 devices. All other connections are the same for APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices. The nINIT_CONF pin is only available on EPC2, EPC4, EPC8, and EPC16 devices and has an internal pull up of 1 kΩ that is always active. If nINIT_CONF is not available or not used, nCONFIG must be pulled to VCC either directly or through a 1-kΩ resistor. The nCEO pin is left unconnected. To ensure successful configuration between APEX 20KE and configuration devices in all possible power-up sequences, pull up nCONFIG to VCCINT. This diagram is for APEX 20KE devices only. To isolate the 1.8-V and 3.3-V power supplies when configuration APEX 20KE devices, add a diode between the APEX 20KE device’s nCONFIG pin and the configuration device’s nINIT_CONF pin. Select a diode with a threshold voltage (VT) less than or equal to 0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will only be able to drive low or tri-state. Altera Corporation 9 Configuration Devices for SRAM-based LUT Devices Data Sheet Table 3 describes EPC2, EPC1, and EPC1441 pin functions during APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device configuration. For information on EPC4, EPC8, and EPC16 devices, refer to Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet. Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000 Configuration (Part 1 of 3) Notes (1), (2) Pin Name Pin Number 8-Pin PDIP (3) 20-Pin PLCC 32-Pin TQFP (4) Pin Type Description DATA 1 2 31 Output Serial data output. The DATA pin is tri-stated before configuration when the nCS pin is high, and after the configuration device finishes sending its configuration data. This operation is independent of the device’s position in the cascade chain. DCLK 2 4 2 I/O DCLK is a clock output when configuring with a single configuration device or when the configuration device is the first device in a configuration device chain. DCLK is a clock input for subsequent configuration devices in a configuration device chain. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The counter is incremented only if the OE input is held high, the nCS input is held low, and all configuration data has not been transferred to the target device. When configuring with the first EPC2 or EPC1 device in a configuration device chain or with a single EPC1441 device, the DCLK pin drives low after configuration is complete or when OE is low. OE (5) 3 8 7 OpenDrain I/O Output enable (active high) and reset (active low). A low logic level resets the address counter. A high logic level enables DATA and permits the address counter to count. If this pin is low (reset) during configuration, the internal oscillator becomes inactive and DCLK drives low. See “Error Detection Circuitry” on page 23. nCS (5) 4 9 10 Input Chip select input (active low). A low input allows DCLK to increment the address counter and enables DATA to drive out. If the EPC1 or EPC2 is reset with nCS low, the device initializes as the first device in a configuration chain. If the EPC1 or EPC2 device is reset with nCS high, the device initializes as the subsequent device in the chain. 10 Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000 Configuration (Part 2 of 3) Notes (1), (2) Pin Name Pin Number 8-Pin PDIP (3) nCASC (6) 20-Pin 32-Pin PLCC TQFP (4) Pin Type Description 6 12 15 Output Cascade select output (active low). This output goes low when the address counter has reached its maximum value. In a chain of EPC1 or EPC2 devices, the nCASC pin of one device is connected to the nCS pin of the next device, which permits DCLK to clock data from the next EPC1 or EPC2 device in the chain. nINIT_CONF – (5), (7) 13 16 OpenDrain Output Allows the INIT_CONF JTAG instruction to initiate configuration. This pin is connected to the nCONFIG pin of the LUT device to initiate configuration from the EPC2 via a JTAG instruction. If multiple EPC2 devices are used to configure an ACEX, APEX, FLEX or Mercury device, only the first EPC2 has its nINIT_CONF pin tied to the device’s nCONFIG pin. TDI (7) – 11 13 Input JTAG data input pin. Connect this pin to VCC if the JTAG circuitry is not used. TDO (7) – 1 28 Output JTAG data output pin. Do not connect this pin if the JTAG circuitry is not used. TMS (7) – 19 25 Input JTAG mode select pin. Connect this pin to VCC if the JTAG circuitry is not used. TCK (7) – 3 32 Input JTAG clock pin. Connect this pin to ground if the JTAG circuitry is not used. VCCSEL (7) – 5 3 Input Mode select for VCC supply. VCCSEL must be connected to ground if the device uses a 5.0-V power supply (i.e., VCC = 5.0 V). VCCSEL must be connected to VCC if the device uses a 3.3-V power supply (i.e., VCC = 3.3 V). VPPSEL (7) – 14 17 Input Mode select for VPP. VPPSEL must be connected to ground if VPP uses a 5.0-V power supply (i.e., VPP = 5.0 V). VPPSEL must be connected to VCC if VPP uses a 3.3-V power supply (i.e, VPP = 3.3 V). VPP (7) – 18 23 Power Programming power pin. For the EPC2 device, this pin is normally tied to VCC. If the EPC2 VCC is 3.3 V, VPP can be tied to 5.0 V to improve in-system programming times. For EPC1 and EPC1441 devices, VPP must be tied to VCC. Altera Corporation 11 Configuration Devices for SRAM-based LUT Devices Data Sheet Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000 Configuration (Part 3 of 3) Notes (1), (2) Pin Name Pin Number 8-Pin PDIP (3) 20-Pin PLCC 32-Pin TQFP (4) Pin Type Description VCC 7, 8 20 27 Power GND 5 10 12 Ground Ground pin. A 0.2-µF decoupling capacitor must be placed between the VCC and GND pins. Power pin. Notes to Table 3: (1) (2) (3) (4) (5) (6) (7) Do not use EPC2 devices to configure FLEX 6000 devices. Pin-out information for EPC8 and EPC16 configuration devices, please refer to each respective data sheet. This package is available for EPC1 and EPC1441 devices only. This package is available for EPC2 and EPC1441 devices only. The OE, nCS, and nINIT_CONF pins on EPC2 devices have internal, user-configurable 1-kΩ pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The EPC1441 device does not support data cascading. EPC2 and EPC1 devices support data cascading. This pin applies to the EPC2 device only. APEX II, APEX 20K, Merucry, ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration with Multiple EPC2 or EPC1 Configuration Devices When configuration data for APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices exceeds the capacity of a single EPC2 or EPC1 configuration device, multiple EPC2 or EPC1 devices can be cascaded together. If multiple EPC2 or EPC1 devices are required, the nCASC and nCS pins provide handshaking between the devices. 1 12 EPC8 and EPC16 configuration devices cannot be cascaded together. The EPC1441 device does not support data cascading. Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet When configuring APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX 10K devices with cascaded EPC2 or EPC1 devices, the position of the EPC2 or EPC1 device in the chain determines its operation. Similarly, when configuring FLEX 6000 devices with cascaded EPC1 devices, the position of the EPC1 device in the chain determines its operation. When the first or master device in a configuration device chain is powered-up or reset and the nCS pin is driven low, the master device controls configuration. The master device supplies all clock pulses to one or more LUT-based PLDs and to any subsequent slave devices during configuration. The master EPC2 or EPC1 device also provides the first stream of data to the LUT-based PLD during multi-device configuration. After the master EPC2 or EPC1 device finishes sending configuration data, the master EPC2 or EPC1 device drives its nCASC pin low, which drives the nCS pin of the first slave EPC2 or EPC1 device low. This action causes the slave EPC2 or EPC1 device to send configuration data to the LUT-based PLDs. The master EPC2 or EPC1 device clocks all subsequent slave devices until configuration is complete. Once all configuration data is transferred and the nCS pin on the master EPC2 or EPC1 device is driven high by the LUTbased PLD’s CONF_DONE pin, the master EPC2 or EPC1 device clocks 16 additional cycles to initialize the LUT-based PLD(s). The master EPC2 or EPC1 device then goes into zero-power (idle) state. If nCS on the master EPC2 or EPC1 device is driven high before all configuration data is transferred, or if nCS is not driven high after all configuration data is transferred, the master EPC2 or EPC1 device drives the APEX 20K, Mercury, ACEX 1K, and FLEX device’s nSTATUS pin low, indicating a configuration error. Configuration automatically restarts if the project is compiled with the Auto-Restart Configuration on Frame Error option turned on in the MAX+PLUS II software’s Global Project Device Options dialog box (Assign menu). Figure 5 shows an APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device configured with two EPC2 or EPC1 devices. Additional EPC2 or EPC1 devices can be added by connecting nCASC to nCS of the subsequent slave EPC2 or EPC1 device in the chain and connecting DCLK, DATA, and OE in parallel. 1 Altera Corporation A mixture of APEX 20K, Mercury, ACEX 1K, FLEX 10K, and FLEX 6000 devices can be configured in the same chain. A mixture of FLEX 10K, FLEX 10KA, FLEX 10KE, and 5.0-V and 3.3-V FLEX 6000 devices can be configured in the same chain. See “Configuration Chain with Multiple Voltage Levels” on page 25. 13 Configuration Devices for SRAM-based LUT Devices Data Sheet Figure 5. APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 Device Configured with Two EPC2 or EPC1 Configuration Devices Note (1) VCC VCC (2, 3) (2, 3) LUT-Based PLD (4) DCLK DATA OE nCS nCASC (5) nINIT_CONF (6) DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 GND Configuration Device 1 Configuration Device 2 DCLK DATA nCS OE nCE GND Notes to Figure 5: (1) (2) (3) (4) (5) (6) 14 Do not use EPC2 devices to configure FLEX 6000 devices. The pull-up resistor should be connected to the same supply voltage as the configuration device. All pull-up resistors are 1 kΩ (APEX 20KE pull-resistors are 10 kΩ). The OE and nCS pins on EPC2 devices have internal, user-configurable 1-kΩ pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The diagram shows an APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device, which has MSEL0 and MSEL1 tied to ground. For FLEX 6000 devices, MSEL is tied to ground, and the DATA0 pin is named DATA. EPC8, EPC16, and EPC2 devices cannot be used with FLEX 6000 devices. All other connections are the same for FLEX 6000 devices. The Quartus II software uses the internal pull-up resistors by default. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files. EPC4, EPC8, and EPC16 devices cannot be cascaded. The nINIT_CONF pin is only available on EPC2 devices and has an internal pull up of 1 kΩ that is always active. If nINIT_CONF is not available or not used, nCONFIG must be pulled to VCC either directly or through a 1-kΩ resistor. Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Figure 6 shows two APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices configured with two EPC2 or EPC1 devices. Figure 6. Two ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, or Mercury Devices Configured with Two EPC2 or EPC1 Configuration Devices Note (1) VCC APEX II, ACEX 1K, Mercury, APEX 20KC, APEX 20K, FLEX 10K, & FLEX 6000 Devices LUT-Based PLD (3) MSEL0 MSEL1 VCC VCC (2) (2) (2) Configuration Device 1 DCLK DATA OE nCS nCASC (4) nINIT_CONF (5) LUT-Based PLD (3) DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG Configuration Device 2 DCLK DATA nCS OE GND GND nCEO nCE nCE GND VCC VCC APEX 20KE Devices VCCINT (6) (2) APEX 20KE PLD (7) MSEL0 MSEL1 MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG GND nCE (2) Configuration Device 1 DCLK DATA OE nCS nCASC (4) nINIT_CONF (5) APEX 20KE PLD (7) DCLK DATA0 nSTATUS CONF_DONE nCONFIG GND (2) Configuration Device 2 DCLK DATA nCS OE (8) nCEO nCE GND Altera Corporation 15 Configuration Devices for SRAM-based LUT Devices Data Sheet Notes to Figure 6: (1) (2) (3) (4) (5) (6) (7) (8) Do not use EPC2 devices to configure FLEX 6000 devices. The pull-up resistor should be connected to the same supply voltage as the configuration device. All pull-up resistors are 1 kΩ (APEX 20KE pull-resistors are 10 kΩ). The OE and nCS pins on EPC2 devices have internal, userconfigurable 1-kΩ pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The Quartus II software uses the internal pull-up resistors by default. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files. The diagram shows an APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX 10K device, which has MSEL0 and MSEL1 tied to ground. For FLEX 6000 devices, MSEL is tied to ground, and the DATA0 pin is named DATA. EPC2 cannot be used with FLEX 6000 devices. All other connections are the same for FLEX 6000 devices. EPC4, EPC8, and EPC16 devices cannot be cascaded. The nINIT_CONF pin is only available on EPC2 devices and has an internal pull up of 1 kΩ that is always active. If nINIT_CONF is not available or not used, nCONFIG must be pulled to VCC either directly or through a 1-kΩ resistor. To ensure successful configuration between APEX 20KE and configuration devices in all possible power-up sequences, pull up nCONFIG to VCCINT. This diagram is for APEX 20KE devices only. To isolate the 1.8-V and 3.3-V power supplies when configuration APEX 20KE devices, add a diode between the APEX 20KE device’s nCONFIG pin and the configuration device’s nINIT_CONF pin. Select a diode with a threshold voltage (VT) less than or queal to 0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will only be able to drive low or tri-state. f For more information on APEX 20K, ACEX 1K, FLEX 10K, or FLEX 6000 device configuration, see Application Note 116 (Configuring ACEX 1K, APEX 20K, FLEX 10K & FLEX 6000 Devices). Figure 7 shows the timing waveform for the configuration device scheme. Figure 7. Configuration Device Scheme Timing Waveform nINIT_CONF or VCC/nCONFIG tPOR OE/nSTATUS nCS/CONF_DONE DCLK DATA tDSU tCL D0 D1 tCH tDH tOEZX D2 D3 (1) Dn tCO User I/O Tri-State User Mode Tri-State INIT_DONE (2) Notes to Figure 7: (1) (2) The configuration devivce will drive DATA low after configuration. APEX II and APEX 20K devices (except EP2A70 devices) enter user mode 40 clock cycles after CONF_DONE goes high. EP2A70 devices enter user mode 72 clock cycles after CONF_DONE goes high. FLEX 10K and FLEX 6000 devices enter user mode 10 clock cycles after CONF_DONE goes high. Mercury devices enter user mode 136 clock cycles after CONF_DONE goes high. 16 Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Table 4 defines the APEX 20K, FLEX 10K, and FLEX 6000 timing parameters when using EPC2 devices at 3.3 V. Table 4. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC2 Devices at 3.3 V Note (1) Symbol Parameter Min Max Units ms tPOR POR delay (2) 200 tOEZX OE high to DATA output enabled 80 ns tCH DCLK high time 40 100 ns tCL DCLK low time 40 100 ns tDSU Data setup time before rising edge on DCLK 30 tDH Data hold time after rising edge on DCLK 0 tCO DCLK to DATA out tOEW OE low pulse width to guarantee counter reset fCLK DCLK frequency ns ns 30 100 5 ns ns 12.5 MHz Notes to Table 4: (1) (2) Altera Corporation For more information regarding EPC4, EPC8, or EPC16 configuration device timing parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet. The configuration device imposes a POR delay upon initial power-up to allow the voltage supply to stabilize. Subsequent reconfigurations do not incur this delay. 17 Configuration Devices for SRAM-based LUT Devices Data Sheet Table 5 defines the APEX 20K, FLEX 10K, and FLEX 6000 timing parameters when using EPC1 and EPC1441 devices at 3.3 V. Table 5. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC1 & EPC1441 Devices at 3.3 V Note (1) Symbol Parameter Min Max Units tPOR POR delay (2) 200 ms tOEZX OE high to DATA output enabled 80 ns tCH DCLK high time 50 250 ns tCL DCLK low time 50 250 tDSU Data setup time before rising edge on DCLK 30 tDH Data hold time after rising edge on DCLK 0 tCO DCLK to DATA out tOEW OE low pulse width to guarantee counter reset fCLK DCLK frequency ns 30 100 2 ns ns ns ns 10 MHz Notes to Table 5: (1) (2) 18 For more information regarding EPC4, EPC8, or EPC16 configuration device timing parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet. The configuration device imposes a POR delay upon initial power-up to allow the voltage supply to stabilize. Subsequent reconfigurations do not incur this delay. Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Table 6 defines the APEX 20K, FLEX 10K, and FLEX 6000 timing parameters when using EPC2, EPC1, and EPC1441 devices at 5.0 V. Table 6. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC2, EPC1 & EPC1441 Devices at 5.0 V Notes (1), (2) Symbol Parameter Min Max Units ms tPOR POR delay (3) 200 tOEZX OE high to DATA output enabled 50 ns tCH DCLK high time 30 75 ns tCL DCLK low time 30 75 ns tDSU Data setup time before rising edge on DCLK 30 tDH Data hold time after rising edge on DCLK 0 tCO DCLK to DATA out tOEW OE low pulse width to guarantee counter reset 100 fCLK DCLK frequency 6.7 ns ns 30 ns ns 16.7 MHz Notes to Table 6: (1) (2) (3) Do not use EPC16, EPC8, EPC4, or EPC2 devices to configure FLEX 6000 devices. For more information regarding EPC4, EPC8, or EPC16 configuration device timing parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet. The configuration device imposes a POR delay upon initial power-up to allow the voltage supply to stabilize. Subsequent reconfigurations do not incur this delay. FLEX 8000 Device Configuration FLEX 8000 devices differ from ACEX 1K, APEX 20K, APEX II, FLEX 10K, and FLEX 6000 devices in that they have internal oscillators that can provide a DCLK signal to the configuration device. The configuration device sends configuration data out as a serial bitstream on the DATA output pin. This data is routed into the FLEX 8000 device via the DATA0 input pin. The EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V configuration devices support this type of configuration. Altera Corporation 19 Configuration Devices for SRAM-based LUT Devices Data Sheet EPC1 and EPC1441 devices can replace the EPC1213, EPC1064, and EPC1064V configuration devices. The EPC1 or EPC1441 device automatically emulates the EPC1213, EPC1064, or EPC1064V when it is programmed with the appropriate POF. When the EPC1 or EPC1441 device is programmed with an EPC1213, EPC1064, or EPC1064V POF, the FLEX 8000 device drives the EPC1 or EPC1441 device’s OE pin high and clocks the EPC1 or EPC1441 device. One EPC1 device can store more configuration data than the EPC1064, EPC1064V, EPC1213, or EPC1441 device. Therefore, designers can use one type of configuration device for all FLEX devices. In addition, a single EPC1 or EPC1441 device can configure any FLEX 8000 device. For multi-device configuration of FLEX 8000 devices, the nCASC and nCS pins provide handshaking between multiple configuration devices, allowing several cascaded EPC1 or EPC1213 devices to serially configure multiple FLEX 8000 devices. The EPC1441, EPC1064, and EPC1064V do not support data cascading. Figure 8 shows a FLEX 8000 device configured with a single EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V configuration device. Figure 8. FLEX 8000 Device Configured with an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V Configuration Device VCC (1) VCC (1) (2) FLEX 8000 Device "0" "0" "0" nS/P MSEL1 MSEL0 CONF_DONE nSTATUS DCLK VCC (1) (2) Configuration Device nCS OE DCLK DATA DATA0 nCONFIG Notes to Figure 8: (1) (2) The pull-up resistor should be connected to the same supply voltage as the configuration device. All pull-up resistors are 1 kΩ. Figure 9 shows three FLEX 8000 devices configured with two EPC1 or EPC1213 configuration devices. 20 Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Figure 9. FLEX 8000 Multi-Device Configuration with Two EPC1 or EPC1213 Configuration Devices VCC (1) VCC (1) VCC VCC FLEX 8000 Device 1 "0" "0" "0" nS/P MSEL1 MSEL0 (1) (2) (2) (1) (2) VCC (1) (2) Configuration Device 1 Configuration Device 2 nCASC DATA CONF_DONE nSTATUS DCLK nCS OE DCLK DATA nCS OE DCLK DATA0 nCONFIG VCC (1) (2) FLEX 8000 Device 2 "0" "1" "0" nS/P MSEL1 MSEL0 CONF_DONE nSTATUS DCLK DATA0 nCONFIG VCC (1) (2) FLEX 8000 Device 3 "0" "1" "0" nS/P MSEL1 MSEL0 CONF_DONE nSTATUS DCLK DATA0 nCONFIG Notes to Figure 9: (1) (2) The pull-resistor should be connected to the same supply voltage as the confiuration device. All pull-up resistors are 1 kΩ. Altera Corporation 21 Configuration Devices for SRAM-based LUT Devices Data Sheet Table 7 describes the pin functions of all configuration devices during FLEX 8000 device configuration. Table 7. Configuration Device Pin Functions During FLEX 8000 Device Configuration Pin Name Pin Number 8-Pin PDIP (1) 20-Pin PLCC 32-Pin TQFP (2) Pin Type Description DATA 1 2 31 Output Serial data output. The DATA pin is tri-stated before configuration when the nCS pin is high and after the configuration device finishes sending its configuration data. This operation is independent of the device’s position in the cascade chain. DCLK 2 4 2 Input DCLK is a clock input when using EPC1, EPC1213, EPC1064, and EPC1064V configuration devices. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The counter is incremented only if the OE input is held high, the nCS input is held low, and all configuration data has not been transferred to the target device. OE 3 8 7 OpenDrain I/O Output enable (active high) and reset (active low). A low logic level resets the address counter. A high logic level enables DATA and permits the address counter to count. nCS (3) 4 9 10 Input Chip-select input (active low). A low input allows DCLK to increment the address counter and enables DATA. nCASC 6 12 15 Output Cascade-select output (active low). This output goes low when the address counter has reached its maximum value. The nCASC output is usually connected to the nCS input of the next device in a configuration chain, so the next DCLK clocks data out of the next device. VCC 7, 8 20 27 Power Power pin. GND 5 10 12 Ground Ground pin. A 0.2-µF decoupling capacitor must be placed between the VCC and GND pins. Notes: to Table 7 (1) (2) (3) This package is available for EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V devices only. This package is available for EPC1441, EPC1064, and EPC1064V devices only. The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC1 and EPC1213 devices support data cascading for FLEX 8000 devices. f For more information on FLEX 8000 device configuration, see the following documents: ■ ■ 22 Application Note 33 (Configuring FLEX 8000 Devices) Application Note 38 (Configuring Multiple FLEX 8000 Devices) Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Power & Operation This section describes Power-On Reset (POR) delay, error detection, and 3.3-V and 5.0-V operation of Altera configuration devices. Power-On Reset During initial power-up, a POR delay occurs to permit voltage levels to stabilize. When configuring an APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device with an EPC4, EPC8, EPC16, EPC2, EPC1, or EPC1441 device, the POR delay occurs inside the configuration device, and the POR delay is a maximum of 200 ms. When configuring a FLEX 8000 device with an EPC1213, EPC1064, or EPC1064V device, the POR delay occurs inside the FLEX 8000 device, and the POR delay is typically 100 ms, with a maximum of 200 ms. Error Detection Circuitry The EPC4, EPC8, EPC16, EPC2, EPC1, and EPC1441 configuration devices have built-in error detection circuitry for configuring APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 devices only. Built-in error-detection circuitry uses the nCS pin of the configuration device, which monitors the CONF_DONE pin on the APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device. An error condition occurs if the CONF_DONE pin does not go high after all the configuration data has been sent, or if the CONF_DONE pin goes high before the configuration device has completed sending configuration data. When an error condition occurs, the configuration device drives its OE pin low, which drives the APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device’s nSTATUS pin low, indicating an error. After an error, configuration automatically restarts if the Auto-Restart Configuration on Frame Error option is turned on in the Global Project Device Options dialog box (Assign menu) in the MAX+PLUS II software. For APEX 20K, APEX II, and Mercury devices, the Quartus II software provides a similar option. In addition, if the APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device detects a cyclic redundancy code (CRC) error in the received data, it may also flag the error by driving nSTATUS low. This low signal on nSTATUS resets the configuration device, allowing reconfiguration. CRC checking is performed when configuring all APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 devices. Altera Corporation 23 Configuration Devices for SRAM-based LUT Devices Data Sheet 3.3-V or 5.0-V Operation EPC2, EPC1, and EPC1441 devices can configure 5.0-V, 3.3-V, or 2.5-V devices. For each configuration device, an option must be set for 5.0-V or 3.3-V operation (EPC4, EPC8, and EPC16 devices are 3.3 V). For EPC1 and EPC1441 configuration devices, the Use Low-Voltage Configuration EPROM option in the Global Project Device Options dialog box (Assign menu) in the MAX+PLUS II software sets this parameter. (For APEX 20K, APEX II, and Mercury devices, the Quartus II software provides a similar option.) For EPC2 devices, this option is set externally by the VCCSEL pin. In addition, the EPC2 device has an externally controlled option, set by the VPPSEL pin, to adjust the programming voltage to 5.0 V or 3.3 V. The functions of the VCCSEL and VPPSEL pins are described below. ■ VCCSEL pin—For EPC2 configuration devices, 5.0-V or 3.3-V operation is controlled by the VCCSEL option pin. The device functions in 5.0-V mode when VCCSEL is connected to GND; the device functions in 3.3-V mode when VCCSEL is connected to VCC. ■ VPPSEL pin—The EPC2 VPP programming power pin is normally tied to VCC. For EPC2 devices operating with a 3.3-V supply, it is possible to improve EPC2 in-system programming times by providing VPP with a 5.0-V supply. For all other devices, VPP must be tied to VCC. The EPC2 device’s VPPSEL pin must be set in accordance with the EPC2 VPP pin. If the VPP pin is supplied by a 5.0-V supply, VPPSEL must be connected to GND; if the VPP pin is supplied by a 3.3-V power supply, VPPSEL must be connected to VCC. Table 8 describes the relationship between the VCC and VPP voltage levels and the required logic level for VCCSEL and VPPSEL (i.e., high or low logic level). Table 8. VCCSEL & VPPSEL Pin Functions on the EPC2 VCC Voltage Level VPP Voltage Level VCCSEL Pin Logic VPPSEL Pin Logic (V) (V) Level Level 24 3.3 3.3 High 3.3 5.0 High High Low 5.0 5.0 Low Low Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet For EPC1 and EPC1441 configuration devices, 3.3-V or 5.0-V operation is controlled by a programming bit in the POF. The programming bit value is determined by the core supply voltage of the targeted device during design compilation with the MAX+PLUS II software. For example, EPC1 devices are programmed automatically to operate in 3.3-V mode when configuring FLEX 10KA devices, which have a VCC voltage of 3.3 V. In this example, the EPC1 device’s VCC pin is connected to a 3.3-V power supply. Designers may choose to set the configuration device for low voltage when using the MultiVoltTM feature, which allows an ACEX, APEX, APEX II, FLEX, or Mercury device to bridge between systems operating with different voltages. When compiling for 3.3-V FLEX 6000 devices, set the configuration device for low-voltage operation. To set the EPC1 and EPC1441 configuration devices for low-voltage operation, turn on the Low-Voltage I/O option in the Global Project Device Options dialog box (Assign menu) in the MAX+PLUS II software. Configuration Chain with Multiple Voltage Levels An EPC2 or EPC1 device can configure a device chain with multiple voltage levels. All 3.3-V and 2.5-V ACEX, APEX, APEX II, FLEX, and Mercury devices can be driven by higher-voltage signals. When configuring a mixed-voltage device chain, the APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX devices’ VCCINT and VCCIO pins may be connected to 2.5 V, 3.3 V, or 5.0 V, depending upon the device. The configuration device may be powered at 3.3 V or 5.0 V. If an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V configuration device is powered at 3.3 V, the nSTATUS and CONF_DONE pull-up resistors must be connected to 3.3 V. If these configuration devices are powered at 5.0 V, the nSTATUS and CONF_DONE pull-up resistors must be connected to 3.3 V or 5.0 V. Altera Corporation 25 Configuration Devices for SRAM-based LUT Devices Data Sheet At 3.3-V operation, all EPC2 inputs are 5.0-V tolerant, except DATA, DCLK, and nCASC. The DATA, DCLK, and nCEO pins are used only to interface between the EPC2 configuration device and the APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX 10K device it is configuring. The voltage tolerances of all EPC2 pins at 5.0 V and 3.3 V are listed in Table 9. Table 9. EPC2 Input & Bidirectional Pin Voltage Tolerance Pin f 3.3-V Operation 5.0-V Tolerant 3.3-V Tolerant 5.0-V Tolerant 3.3-V Tolerant DATA v v v DCLK v v v nCASC v v v OE v v v v nCS v v v v VCCSEL v v v v VPPSEL v v v v nINIT_CONF v v v v TDI v v v v TMS v v v v TCK v v v v For more information on APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 devices, see the following documents: ■ ■ ■ ■ ■ ■ ■ ■ 26 5.0-V Operation ACEX 1K Programmable Logic Device Family Data Sheet APEX 20K Programmable Logic Device Family Data Sheet APEX II Programmable Logic Device Family Data Sheet FLEX 10K Embedded Programmable Logic Family Data Sheet FLEX 10KE Embedded Programmable Logic Family Data Sheet FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 6000 Programmable Logic Device Family Data Sheet Mercury Programmable Logic Device Family Data Sheet Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Programming & Configuration File Support The Quartus II and MAX+PLUS II development systems provide programming support for Altera configuration devices. The Quartus II and MAX+PLUS II software automatically generates a POF to program each configuration device in a project. In a multi-device project, the software can combine the programming files for multiple ACEX, APEX, APEX II, FLEX, or Mercury devices into one or more configuration devices. The software allows you to select the appropriate configuration device to most efficiently store the data for each APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX device. Moreover, when compiling for ACEX 1K, FLEX 10KA, FLEX 10KE, or Mercury devices, the MAX+PLUS II software automatically defaults to generate the EPC1 or EPC1441 POF with the programming bit set for 3.3-V operation. All Altera configuration devices are programmable using Altera programming hardware in conjunction with the Quartus II or MAX+PLUS II software. In addition, many manufacturers offer programming hardware that supports other Altera configuration devices. EPC4, EPC8, EPC16, and EPC2 configuration devices can be programmed in-system through its industry-standard 4-pin JTAG interface. ISP capability in the EPC2, EPC4, EPC8, and EPC16 devices provides ease in prototyping and updating APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX device functionality. The EPC8 and EPC16 devices can be programmed in-system via test equipment using SVF Files, Jam STAPL Files (.jam), or Jam STAPL Byte-Code Files (.jbc), embedded processors using the Jam programming and test language, and the MAX+PLUS II or Quartus II software via the MasterBlaster or ByteBlasterMV download cables. When programming multiple EPC2 devices in a JTAG chain, the Quartus II and MAX+PLUS II software and other programming methods employ concurrent programming to simultaneously program multiple devices and reduce programming time. EPC2, EPC4, EPC8, and EPC16 devices can be programmed and erased up to 100 times. After programming an EPC2, EPC4, EPC8, or EPC16 device in-system, APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX device configuration can be initiated by including the EPC2 JTAG configuration instruction. See Table 10 on page 28. f For more information on programming and configuration support, see the following documents: ■ ■ ■ ■ ■ ■ Altera Corporation Altera Programming Hardware Data Sheet Programming Hardware Manufacturers MasterBlaster Serial/USB Communications Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet ByteBlaster Parallel Port Download Cable Data Sheet BitBlaster Serial Download Cable Data Sheet 27 Configuration Devices for SRAM-based LUT Devices Data Sheet IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing f The EPC2 provides JTAG BST circuitry that complies with the IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be performed before or after configuration, but not during configuration. The EPC2 device supports the JTAG instructions shown in Table 10. The ISP circuitry in EPC2, EPC4, EPC8, and EPC16 devices is compatible with tools that support the IEEE Std. 1532. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. For EPC4, EPC8, and EPC16 JTAG instruction, refer to the Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet. Table 10. EPC2 JTAG Instructions JTAG Instruction Description SAMPLE/PRELOAD Allows a snapshot of a signal at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing results at the input pins. BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation. IDCODE Selects the device IDCODE register and places it between TDI and TDO, allowing the device IDCODE to be serially shifted out of TDO. The device IDCODE for the EPC2 configuration device is shown below: 0000 0001000000000010 00001101110 1 USERCODE Selects the USERCODE register and places it between TDI and TDO, allowing the USERCODE to be serially shifted out of TDO. The 32-bit USERCODE is a programmable user-defined pattern. ISP Instructions These instructions are used when programming an EPC2 device via JTAG ports with a MasterBlaster, ByteBlaster MV, ByteBlaster, or BitBlaster download cable, or using a Jam STAPL File (.jam), Jam STAPL Byte-Code File (.jbc), or SVF File via an embedded processor. INIT_CONF This function allows the user to initiate the APEX or FLEX configuration process by tying nINIT_CONF to the APEX or FLEX device(s) nCONFIG pin(s). After this instruction is updated, the nINIT_CONF pin is driven low. When the Initiate Configuration instruction is cleared, nINIT_CONF is released, which starts the APEX or FLEX device configuration. This instruction is used by the MAX+PLUS II software, Jam STAPL Files, and JBC Files. f For more information, see Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices). Figure 10 shows the timing requirements for the JTAG signals. 28 Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Figure 10. EPC2 JTAG Waveforms TMS TDI tJCP tJCH tJCL tJPSU tJPH TCK tJPZX tJPXZ tJPCO TDO tJSH tJSSU Signal to Be Captured tJSZX tJSCO tJSXZ Signal to Be Driven Table 11 shows the timing parameters and values for configuration devices. Table 11. JTAG Timing Parameters & Values Symbol Operating Conditions Altera Corporation Parameter Min Max Unit tJCP TCK clock period 100 tJCH TCK clock high time ns 50 ns tJCL TCK clock low time 50 ns tJPSU JTAG port setup time 20 ns tJPH JTAG port hold time 45 tJPCO JTAG port clock to output 25 ns tJPZX JTAG port high impedance to valid output 25 ns tJPXZ JTAG port valid output to high impedance 25 tJSSU Capture register setup time 20 tJSH Capture register hold time 45 tJSCO Update register clock to output 25 ns tJSZX Update register high-impedance to valid output 25 ns tJSXZ Update register valid output to high impedance 25 ns ns ns ns ns Tables 12 through 19 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for configuration devices. 29 Configuration Devices for SRAM-based LUT Devices Data Sheet f For EPC4, EPC8, and EPC16 device operating conditions, refer to the Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet. Table 12. Absolute Maximum Ratings Symbol Note (1) Parameter Conditions Min Max Unit V VCC Supply voltage With respect to ground (2) –2.0 7.0 VI DC input voltage With respect to ground (2) –2.0 7.0 V IMAX DC VCC or ground current 50 mA IOUT DC output current, per pin PD Power dissipation TSTG Storage temperature No bias TAMB Ambient temperature Under bias TJ Junction temperature Under bias –25 25 mA 250 mW –65 150 °C –65 135 °C 135 °C Max Unit Table 13. Recommended Operating Conditions Symbol VCC Parameter Conditions Supply voltage for 5.0-V operation (3), (4) Supply voltage for 3.3-V operation (3), (4) VI Input voltage With respect to ground VO Output voltage TA Operating temperature tR Input rise time tF Input fall time Min 4.75 (4.50) 5.25 (5.50) For commercial use For industrial use V 3.0 (3.0) 3.6 (3.6) V –0.3 V CC + 0.3 (5) V 0 V CC V 0 70 °C –40 85 °C 20 ns 20 ns Min Max Unit V Table 14. DC Operating Conditions Symbol Parameter Conditions VIH High-level input voltage 2.0 VCC + 0.3 (5) VIL Low-level input voltage –0.3 0.8 VOH 5.0-V mode high-level TTL output voltage IOH = –4 mA DC (6) 2.4 V VCC – 0.2 V 3.3-V mode high-level CMOS output voltage IOH = –0.1 mA DC (6) V VOL Low-level output voltage IOL = 4 mA DC (6) 0.4 V II Input leakage current VI = VCC or ground –10 10 µA IOZ Tri-state output off-state current VO = VCC or ground –10 10 µA 30 Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Table 15. EPC1213, EPC1064 & EPC1064V Device ICC Supply Current Values Symbol Parameter Conditions Min Typ Max Unit ICC0 VCC supply current (standby) 100 200 µA ICC1 VCC supply current (during configuration) 10 50 mA Table 16. EPC2 Device ICC Supply Current Values Typ Max Unit ICC0 Symbol VCC supply current (standby) Parameter VCC = 5.0 V or 3.3 V Conditions Min 50 100 µA ICC1 VCC supply current (during configuration) VCC = 5.0 V or 3.3 V 18 50 mA Unit Table 17. EPC1 Device ICC Supply Current Values Typ Max ICC0 Symbol VCC supply current (standby) Parameter Conditions Min 50 100 µA ICC1 VCC supply current (during configuration) VCC = 5.0 V 30 50 mA VCC = 3.3 V 10 16.5 mA Unit Table 18. EPC1441 Device ICC Supply Current Values Typ Max ICC0 Symbol VCC supply current (standby) Parameter 30 60 µA ICC1 VCC supply current (during configuration) VCC = 5.0 V 15 30 mA ICC1 VCC supply current (during configuration) VCC = 3.3 V 5 10 mA Min Max Unit Table 19. Capacitance Symbol Conditions Min Note (7) Parameter Conditions CIN Input pin capacitance VIN = 0 V, f = 1.0 MHz 10 pF COUT Output pin capacitance VOUT = 0 V, f = 1.0 MHz 10 pF Notes to Tables 12 − 19: (1) (2) (3) (4) (5) (6) (7) See the Operating Requirements for Altera Devices Data Sheet. The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns under no-load conditions. Numbers in parentheses are for industrial-temperature-range devices. Maximum VCC rise time is 100 ms. Certain EPC2 pins may be driven to 5.75 V when operated with a 3.3-V VCC. See Table 9 on page 26. The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL or CMOS output current. Capacitance is sample-tested only. Altera Corporation 31 Configuration Devices for SRAM-based LUT Devices Data Sheet Tables 20 through 24 show the device configuration parameters for APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX devices. Table 20. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC2 Devices at 5.0-V Max Unit tCE Symbol OE high to first clock delay Parameter Conditions Min Typ 200 ns tOEZX OE high to data output enabled 50 ns tCO DCLK to data out delay 20 ns tMCH DCLK high time for the first device in the configuration chain 30 50 75 ns tMCL DCLK low time for the first device in the configuration chain 30 50 75 ns 10 16.7 MHz fCK Clock frequency 6.7 tSCH DCLK high time for subsequent devices 30 tSCL DCLK low time for subsequent devices 30 tCASC CLK rising edge to nCASC 20 tCCA nCS to nCASC cascade delay 10 ns fCDOE CLK to data enable/disable 20 ns tOEC OE low to CLK disable delay 20 ns tNRCAS OE low (reset) to nCASC delay 25 ns tNRR OE low time (reset) minimum ns ns 100 ns ns Table 21. ACEX 1K, APEX 20K, APEX II, FLEX 10K & Mercury Device Configuration Parameters Using EPC2 Devices at 3.3-V Symbol Parameter Conditions Min Typ Max Unit ns tCE OE high to first clock delay 300 tOEZX OE high to data output enabled 80 ns tCO DCLK to data out delay 30 ns tMCH DCLK high time for the first device in the configuration chain 40 65 100 ns tMCL DCLK low time for the first device in the configuration chain 40 65 100 ns fCK Clock frequency 5 7.7 12.5 MHz tSCH DCLK high time for subsequent devices 40 tSCL DCLK low time for subsequent devices 40 tCASC CLK rising edge to nCASC tCCA nCS to nCASC cascade delay 15 ns fCDOE CLK to data enable/disable 30 ns tOEC OE low to CLK disable delay 30 ns tNRCAS OE low (reset) to nCASC delay 30 tNRR OE low time (reset) minimum 32 ns ns 25 100 ns ns ns Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Table 22. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 & EPC1441 Devices at 5.0-V Max Unit tCE Symbol OE high to first clock delay Parameter Conditions Min Typ 200 ns tOEZX OE high to data output enabled 50 ns tCO DCLK to data out delay 20 ns tMCH DCLK high time for the first device in the configuration chain 30 50 75 ns tMCL DCLK low time for the first device in the configuration chain 30 50 75 ns fCK Clock frequency 6.7 10 16.7 MHz tSCH DCLK high time for subsequent devices 30 ns tSCL DCLK low time for subsequent devices 30 ns tCASC CLK rising edge to nCASC 20 ns tCCA nCS to nCASC cascade delay 10 ns fCDOE CLK to data enable/disable 20 ns tOEC OE low to CLK disable delay 20 ns tNRCAS OE low (reset) to nCASC delay 25 ns tNRR OE low time (reset) minimum 100 ns Table 23. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 & EPC1441 Devices at 3.3-V Max Unit tCE Symbol OE high to first clock delay Parameter 300 ns tOEZX OE high to data output enabled 80 ns tCO DCLK to data out delay 30 ns tMCH DCLK high time for the first device in the configuration chain 50 125 250 ns tMCL DCLK low time for the first device in the configuration chain 50 125 250 ns fCK Clock frequency 2 4 10 MHz tSCH DCLK high time for subsequent devices 50 ns tSCL DCLK low time for subsequent devices 50 ns tCASC CLK rising edge to nCASC 25 ns tCCA nCS to nCASC cascade delay 15 ns fCDOE CLK to data enable/disable 30 ns tOEC OE low to CLK disable delay 30 ns tNRCAS OE low (reset) to nCASC delay 30 ns tNRR OE low time (reset) minimum Altera Corporation Conditions Min 100 Typ ns 33 Configuration Devices for SRAM-based LUT Devices Data Sheet Table 24. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1441, EPC1213, EPC1064 & EPC1064V Devices Symbol Parameter Conditions EPC1064V EPC1064 EPC1213 EPC1 Unit EPC1441 Min Max Min Max Min Max tOEZX OE high to DATA output enabled 75 50 50 ns tCSZX nCS low to DATA output enabled 75 50 50 ns tCSXZ nCS high to DATA output disabled 75 50 50 ns tCSS nCS low setup time to first DCLK rising edge 150 100 50 ns tCSH nCS low hold time after DCLK rising edge 0 0 0 ns tDSU Data setup time before rising edge on DCLK 75 50 50 ns tDH Data hold time after rising edge on DCLK 0 tCO DCLK to DATA out delay tCK Clock period fCK Clock frequency tCL DCLK low time 120 tCH DCLK high time 120 tXZ OE low or nCS high to DATA output disabled tOEW OE pulse width to guarantee counter reset tCASC Last DCLK + 1 to nCASC low delay 90 60 50 ns tCKXZ Last DCLK + 1 to DATA tri-state delay 75 50 50 ns tCEOUT nCS high to nCASC high delay 150 100 100 ns Revision History 240 0 75 160 4 80 8 MHz ns 50 80 150 ns 100 6 75 ns 75 ns 50 50 ns 50 100 100 ns ns The information contained in the Configuration Devices for SRAM-Based LUT Devices Data Sheet version 12.1 supersedes information published in pervious versions. The following changes were made to the Configuration Devices for SRAM-Based LUT Devices Data Sheet version 12.1: ■ ■ ■ 34 0 100 Updated Table 2. Updated notes to Figures 4, 5, and 6. Added APEX 20KE device diagrams to Figures 4 and 6. Altera Corporation Configuration Devices for SRAM-Based LUT Devices Data Sheet Notes: Altera Corporation 35 Configuration Devices for SRAM-Based LUT Devices Data Sheet ® 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: [email protected] 36 Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. 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