TI 74FCT163H501CPVCT

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163501
CY74FCT163H501
18-Bit Registered Transceivers
SCCS047 - January 1998 - Revised March 2000
Features
• Eliminates the need for external pull-up or pull-down
resistors
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.6 ns
• Latch-up performance exceeds JEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical Volp (ground bounce) performance exceeds Mil
Std 883D
• VCC = 2.7V to 3.6V
CY74FCT163501 Features:
• Balanced output drivers: 24 mA
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 3.3V,
TA= 25˚C
CY74FCT163H501 Features:
• Bus hold retains the last active state
• Devices with bus hold are not recommended for translating rail-to-rail CMOS signals to 3.3V logic levels
Functional Description
These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For
A-to-B data flow, the device operates in transparent mode
when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a HIGH or LOW logic level. If LEAB
is LOW, the A bus data is stored in the latch/flip-flop on the
LOW-to-HIGH transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and
CLKBA. The output buffers are designed with a power-off
disable feature to allow live insertion of boards.
THE CY74FCT163501 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors, as well as provides for
minimal undershoot and reduced ground bounce. The
CY74FCT163501 is ideal for driving transmission lines.
The CY74FCT163H501 is a 24-mA balanced output part, that
has “bus hold” on the data inputs. The device retains the
input’s last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and
prevents floating inputs.
Pin Configuration
Functional Block Diagram; CY74FCT163501, CY74FCT163H501
SSOP/TSSOP
Top View
OEAB
LEAB
A1
GND
A2
OEAB
A3
CLKBA
VCC
A4
A5
A6
LEBA
OEBA
CLKAB
LEAB
A1
C
C
D
D
B1
C
C
D
D
TO 17 OTHER CHANNELS
GND
A7
A8
A9
A 10
A 11
A 12
GND
A 13
A 14
A 15
VCC
FCT163501-1
A 16
A 17
GND
A 18
OEBA
LEBA
1
2
56
55
3
4
54
53
5
6
7
52
51
50
8
9
49
48
10
11
12
13
14
15
16
17
18
19
20
21
22
23
47
46
45
44
43
42
41
40
39
38
37
36
35
34
24
25
26
27
28
33
32
31
30
29
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
FCT163501-2
Copyright
© 2000, Texas Instruments Incorporated
CY74FCT163501
CY74FCT163H501
Maximum Ratings[6, 7]
Pin Description
Name
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Description
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
Ambient Temperature with
Power Applied .................................................. −55°C to +125°C
LEBA
B-to-A Latch Enable Input
DC Input Voltage .................................................−0.5V to +7.0V
CLKAB
A-to-B Clock Input
DC Output Voltage ..............................................−0.5V to +7.0V
CLKBA
B-to-A Clock Input
A
A-to-B Data Inputs or B-to-A Three-State
Outputs[1]
DC Output Current
(Maximum Sink Current/Pin) ...........................−60 to +120 mA
B
B-to-A Data Inputs or A-to-B Three-State
Outputs[1]
Storage Temperature ..................................... −55°C to +125°C
Power Dissipation .......................................................... 1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Operating Range
Function Table[2, 3]
Inputs
1.
2.
3.
4.
5.
6.
7.
Range
Outputs
OEAB
LEAB
CLKAB
A
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
L
X
B[4]
H
L
H
X
B[5]
Industrial
Ambient
Temperature
VCC
−40°C to +85°C
2.7V to 3.6V
On the 74FCT163H501 these pins have bus hold.
A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-impedance
= LOW-to-HIGH Transition
Output level before the indicated steady-state input conditions were established.
Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
2
CY74FCT163501
CY74FCT163H501
Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC = 2.7V to 3.6V
Parameter
Description
Test Conditions
VIH
Input HIGH Voltage
All Inputs
VIL
Input LOW Voltage
VH
Input Hysteresis[9]
VIK
Input Clamp Diode Voltage
VCC=Min., IIN=–18 mA
IIH
Input HIGH Current
IIL
Min.
Typ.[8]
2.0
Max.
Unit
5.5
V
0.8
100
–0.7
V
mV
–1.2
V
VCC=Max., VI=5.5
±1
µA
Input LOW Current
VCC=Max., VI=GND
±1
µA
IOZH
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=5.5V
±1
µA
IOZL
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=GND
±1
µA
IOS
Short Circuit Current[10]
VCC=Max., VOUT=GND
–240
mA
IOFF
Power-Off Disable
VCC=0V, VOUT≤4.5V
±100
µA
ICC
Quiescent Power Supply Current
VIN≤0.2V,
VIN>VCC–0.2V
VCC=Max.
0.1
10
µA
∆ICC
Quiescent Power Supply Current
(TTL inputs HIGH)
VIN=VCC–0.6V[11] VCC=Max.
2.0
30
µA
–60
–135
Notes:
8. Typical values are at VCC=3.3V, TA = +25˚C ambient.
9. This parameter is specified but not tested.
10. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
11. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
3
CY74FCT163501
CY74FCT163H501
Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
Test Conditions
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Input Hysteresis[9]
VIK
Input Clamp Diode Voltage
VCC=Min., IIN=–18 mA
IIH
Input HIGH Current
IIL
Input LOW Current
IBBH
IBBL
Min.
All Inputs
Typ.[8]
2.0
Max.
Unit
VCC
V
0.8
100
[12]
Bus Hold Sustain Current on Bus Hold Input
V
mV
–1.2
V
VCC=Max., VI=VCC
±100
µA
VCC=Max., VI=GND
±100
µA
VCC=Min.
–0.7
VI=2.0V
–50
µA
VI=0.8V
+50
µA
±500
µA
VCC=Max., VOUT=VCC
±1
µA
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=GND
±1
µA
IOS
Short Circuit Current[10]
VCC=Max., VOUT=GND
–240
mA
IOFF
Power-Off Disable
VCC=0V, VOUT≤4.5V
±100
µA
ICC
Quiescent Power Supply Current
VIN≤0.2V,
VIN>VCC–0.2V
VCC=Max.
+40
µA
∆ICC
Quiescent Power supply Current
(TTL inputs HIGH)
VIN=VCC–0.6V[11] VCC=Max.
+350
µA
[12]
IBHHO
IBHLO
Bus Hold Overdrive Current on Bus Hold Input
VCC=Max., VI=1.5V
IOZH
High Impedance Output Current
(Three-State Output pins)
IOZL
–60
–135
Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
Test Conditions
IODL
Output LOW Dynamic
Current[10]
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
IODH
Output HIGH Dynamic Current[10]
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
VOH
Output HIGH Voltage
VCC=Min., IOH= –0.1 mA
VOL
Output LOW Voltage
Min.
Typ.[8]
Max.
Unit
45
180
mA
–45
–180
mA
VCC–0.2
V
VCC=3.0V, IOH= –8 mA
2.4[13]
3.0
V
VCC=3.0V, IOH= –24 mA
2.0
3.0
V
VCC=Min., IOL= 0.1mA
0.2
VCC=Min., IOL= 24 mA
0.3
V
0.55
Capacitance[9](TA = +25˚C, f = 1.0 MHz)
Parameter
Description
Test Conditions
Typ.[8]
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6.0
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8.0
pF
Notes:
12. Pins with bus hold are described in Pin Description.
13. VOH=VCC – 0.6V at rated current.
4
CY74FCT163501
CY74FCT163H501
Power Supply Characteristics
Sym.
Parameter
Test Conditions[14]
Min.
Typ.[8]
Max.
Unit
ICCD
Dynamic Power Supply
Current[15]
VCC=Max., Outputs Open
OEAB=OEBA=VCC or GND
One Input Toggling,
50% Duty Cycle
VIN=VCC or
VIN=GND
—
75
120
µA/
MHz
IC
Total Power Supply
Current[16]
VCC=Max., Outputs Open
f0 =10MHz (CLKAB)
50% Duty Cycle
OEAB=OEBA=VCC
LEAB = GND, One Bit Toggling
f1 = 5MHz, 50% Duty Cycle
VIN=VCC or
VIN=GND
—
0.8
1.7
mA
VIN=3.4V or
VIN=GND
—
1.3
3.2
VIN=VCC or
VIN=GND
—
3.8
6.5[17]
VIN=3.4V or
VIN=GND
—
8.5
20.8[17]
VCC=Max., Outputs Open
f0 = 10MHz (CLKAB)
50% Duty Cycle
OEAB=OEBA=VCC
LEAB=GND
Eighteen Bits Toggling
f1=2.5MHz, 50% Duty Cycle
Notes:
14. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
15. This parameter is not directly testable, but is derived for use in Total Power Supply Current.
16. IC= IQUIESCENT + IINPUTS + IDYNAMIC
IC
= ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
= Duty Cycle for TTL inputs HIGH
DH
= Number of TTL inputs at DH
NT
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f0
= Input signal frequency
f1
= Number of inputs changing at f1
N1
All currents are in milliamps and all frequencies are in megahertz.
17. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
5
CY74FCT163501
CY74FCT163H501
Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[18]
CY74FCT163501C
CY74FCT163H501C
Parameter
Description
Min.
Max.
Unit
Fig.No.[19]
fMAX
CLKAB or CLKBA frequency[9]
—
150
MHz
—
tPLH
tPHL
Propagation Delay
A to B or B to A
1.5
4.6
ns
1,3
tPLH
tPHL
Propagation Delay
LEBA to A, LEAB to B
1.5
5.3
ns
1,5
tPLH
tPHL
Propagation Delay
CLKBA to A,
CLKAB to B
1.5
5.3
ns
1,5
tPZH
tPZL
Output Enable Time
OEBA to A, OEAB to B
1.5
5.6
ns
1,7,8
tPHZ
tPLZ
Output Disable Time
OEBA to A, OEAB to B
1.5
5.2
ns
1,7,8
tSU
Set-Up Time,
HIGH or LOW
A to CLKAB,
B to CLKBA
3.0
—
ns
4
tH
Hold Time
HIGH or LOW
A to CLKAB,
B to CLKBA
0
—
ns
4
tSU
Set-Up Time, HIGH or LOW
A to LEAB,
B to LEBA
Clock LOW
3.0
—
ns
4
Clock HIGH
1.5
—
ns
4
1.5
—
ns
4
3.0
—
ns
5
3.0
—
ns
5
—
0.5
ns
—
tH
Hold Time, HIGH or LOW, A to LEAB,
B to LEBA
tW
LEAB or LEBA Pulse Width HIGH[9]
tW
CLKAB or CLKBA Pulse Width HIGH or
tSK(O)
Output Skew[20]
LOW[9]
Notes:
18. Minimum limits are specified, but not tested, on propagation delays.
19. See “Parameter Measurement Information” in the General Information section.
20. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.
6
CY74FCT163501
CY74FCT163H501
Ordering Information CY74FCT163501T
Speed
(ns)
4.6
Package
Name
Ordering Code
Package Type
CY74FCT163501CPACT
Z56
56-Lead (240-Mil) TSSOP
CY74FCT163501CPVC/PVCT
O56
56-Lead (300-Mil) SSOP
Operating
Range
Industrial
Ordering Information CY74FCT163H501T
Speed
(ns)
4.6
Ordering Code
Package
Name
Package Type
74FCT163H501CPACT
Z56
56-Lead (240-Mil) TSSOP
CY74FCT163H501CPVC
O56
56-Lead (300-Mil) SSOP
74FCT163H501CPVCT
O56
56-Lead (300-Mil) SSOP
Package Diagrams
56-Lead Shrunk Small Outline Package O56
7
Operating
Range
Industrial
CY74FCT163501
CY74FCT163H501
Package Diagrams (continued)
56-Lead Thin Shrunk Small Outline Package Z56
8
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Copyright  2000, Texas Instruments Incorporated