TM497FBK32, TM497FBK32S 4194304 BY 32-BIT TM893GBK32, TM893GBK32S 8388608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 D D D D D D D D D D Organization – TM497FBK32/S: 4 194 304 x 32 – TM893GBK32/S: 8 388 608 x 32 Single 5-V Power Supply (±10% Tolerance) 72-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets TM497FBK32/S – Uses Eight 16M-Bit Dynamic Random-Access Memories (DRAMs) in Plastic Small-Outline J-Lead (SOJ) Packages TM893GBK32/S – Uses Sixteen 16M-Bit DRAMs in Plastic SOJ Packages Long Refresh Period 32 ms (2 048 Cycles) All Inputs, Outputs, Clocks Fully TTL-Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks Extended Data Out (EDO) Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh D D Presence Detect Performance Ranges: ACCESS ACCESS ACCESS TIME TIME TIME tRAC tAA tCAC (MAX) (MAX) (MAX) ’497FBK32/S-60 60 ns 30 ns 15 ns ’497FBK32/S-70 70 ns 35 ns 18 ns ’497FBK32/S-80 80 ns 40 ns 20 ns D D D D ’893GBK32/S-60 60 ns ’893GBK32/S-70 70 ns ’893GBK32/S-80 80 ns 30 ns 35 ns 40 ns 15 ns 18 ns 20 ns EDO CYCLE tHPC (MIN) 25 ns 30 ns 35 ns 25 ns 30 ns 35 ns Low Power Dissipation Operating Free-Air Temperature Range 0°C to 70°C Gold-Tabbed Version Available:† TM497FBK32, TM893GBK32 Tin-Lead (Solder-) Tabbed Version Available: TM497FBK32S, TM893GBK32S description The TM497FBK32 is a 16M-byte dynamic random-access memory (DRAM) organized as four times 4 194 304 × 8 bits in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is composed of eight TMS417409DJ, 4 194 304 × 4-bit DRAMs, each in 24/26-lead plastic small-outline J-lead (SOJ) packages mounted on a substrate with decoupling capacitors. The TMS417409DJ is described in the TMS416409, TMS417409 data sheet (literature number SMKS884). The TM497FBK32 SIMM is available in the single-sided BK leadless module for use with sockets. The TM497FBK32 features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation from 0°C to 70°C. The TM893GBK32/S is a 32M-byte DRAM organized as four times 8 388 608 × 8 bits in a 72-pin leadless SIMM. The SIMM is composed of sixteen TMS417409DJ 4 194 304 × 4-bit DRAMs. The TM893GBK32/S SIMM is available in the double-sided BK leadless module for use with sockets. The TM893GBK32/S features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation from 0°C to 70°C. operation The TM497FBK32/S operates as eight TMS417409DJs connected as shown in Figure 1 and in Table 1. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. The TM893GBK32/S operates as sixteen TMS417409DJs connected as shown in Figure 2 and in Table 2. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TM497FBK32, TM497FBK32S 4194304 BY 32-BIT TM893GBK32, TM893GBK32S 8388608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 refresh The refresh period is extended to 32 ms and, during this period, each of the 2 048 rows must be strobed with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. power up To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh (RAS-only or CBR ) cycle. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM497FBK32, TM497FBK32S 4194304 BY 32-BIT TM893GBK32, TM893GBK32S 8388608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 BK SINGLE-IN-LINE PACKAGE ( TOP VIEW ) VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 NC RAS2 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 NC NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 TM497FBK32/S ( SIDE VIEW ) TM893GBK32/S ( SIDE VIEW ) PIN NOMENCLATURE A0 – A10 CAS0 – CAS3 DQ0 – DQ31 NC PD1 – PD4 RAS0 – RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In / Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable PRESENCE DETECT SIGNAL (PIN) 80 ns TM497FBK32/S 70 ns 60 ns TM893GBK32/S POST OFFICE BOX 1443 PD1 (67) PD2 (68) PD3 (69) PD4 (70) VSS VSS NC NC NC VSS NC VSS NC 80 ns VSS NC 70 ns NC VSS VSS 60 ns NC VSS • HOUSTON, TEXAS 77251–1443 NC NC VSS NC NC VSS NC NC 3 TM497FBK32, TM497FBK32S 4194304 BY 32-BIT TM893GBK32, TM893GBK32S 8388608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 Table 1. TM497FBK32/S Connection Table DATA BLOCK RASx CASx DQ0 – DQ7 RAS0 CAS0 DQ8 – DQ15 RAS0 CAS1 DQ16 – DQ23 RAS2 CAS2 DQ24 – DQ31 RAS2 CAS3 Table 2. TM893GBK32/S Connection Table DATA BLOCK RASx CASx Side 1 Side 2 DQ0 – DQ7 RAS0 RAS1 CAS0 DQ8 – DQ15 RAS0 RAS1 CAS1 DQ16 – DQ23 RAS2 RAS3 CAS2 DQ24 – DQ31 RAS2 RAS3 CAS3 single-in-line memory module and components PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM497FBK32 and TM893GBK32: Nickel plate and gold plate over copper Contact area for TM497FBK32S and TM893GBK32S: Nickel plate and tin-lead over copper 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 A0 – A10 RAS0 W CAS0 11 RAS2 CAS1 11 11 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 11 DQ0 – DQ3 11 DQ4 – DQ7 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 11 DQ8 – DQ11 11 DQ12 – DQ15 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 Figure 1. Functional Block Diagram of TM497FBK32 11 DQ16 – DQ19 11 DQ20 – DQ23 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 DQ24 – DQ27 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 DQ28 – DQ31 SMMS668 – NOVEMBER 1996 5 TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 CAS3 CAS2 11 RAS2 CAS1 11 11 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 CAS3 CAS2 11 DQ0 – DQ3 11 DQ4 – DQ7 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 DQ8 – DQ11 11 4 M × 4 A0 – A10 RAS W CAS OE DQ1– DQ4 11 DQ12 – DQ15 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 11 DQ16 – DQ19 11 DQ20 – DQ23 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 DQ24 – DQ27 DQ28 – DQ31 side 2 A0 – A10 RAS1 W CAS0 11 RAS3 CAS1 11 11 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 11 DQ0 – DQ3 11 DQ4 – DQ7 CAS3 CAS2 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 DQ8 – DQ11 11 4 M × 4 A0 – A10 RAS W CAS OE DQ1– DQ4 11 DQ12 – DQ15 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 Figure 2. Functional Block Diagram of TM893GBK32/S 11 DQ16 – DQ19 11 DQ20 – DQ23 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 4M×4 A0 – A10 RAS W CAS OE DQ1– DQ4 DQ24 – DQ27 DQ28 – DQ31 Template Release Date: 7–11–94 A0 – A10 RAS0 W CAS0 TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 6 side 1 TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 5 UNIT VCC VIH Supply voltage 4.5 5.5 V High-level input voltage 2.4 6.5 V VIL TA Low-level input voltage (see Note 2) –1 0.8 V 0 70 °C Operating free-air temperature NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH VOL High-level output voltage II Input current (leakage) IO ICC1 ICC2 Low-level output voltage TEST CONDITIONS‡ IOH = – 5 mA IOL = 4.2 mA ’497FBK32-60 MIN MAX 2.4 ’497FBK32-70 MIN MAX 2.4 ’497FBK32-80 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA Output current (leakage) VCC = 5.5 V, CAS high VO = 0 V to VCC, ± 10 ± 10 ± 10 µA Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 880 800 720 mA 16 16 16 mA 8 8 8 mA Standby current VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 880 800 720 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, RAS low, 560 480 400 mA tPC = MIN, CAS cycling ‡ For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS† PARAMETER VOH VOL High-level output voltage Low-level output voltage IOH = – 5 mA IOL = 4.2 mA ’893GBK32-60 MIN MAX 2.4 ’893GBK32-70 MIN MAX 2.4 ’893GBK32-80 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V ± 20 ± 20 ± 20 µA II Input current (leakage) VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC IO Output current (leakage) VCC = 5.5 V, CASx high VO = 0 V to VCC, ± 20 ± 20 ± 20 µA ICC1 Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 896 816 736 mA VIH = 2.4 V (TTL), After one memory cycle, RASx and CASx high 32 32 32 mA VIH = VCC – 0.2 V (CMOS), After one memory cycle, RASx and CASx high 16 16 16 mA 1760 1600 1440 mA 576 496 416 mA ICC2 Standby current ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, RASx cycling, (RASx only); Minimum cycle CASx low (CBR) CASx high RASx low after ICC4 Average page current (see Note 4) VCC = 5.5 V, RASx low, tPC = MIN, CASx cycling † For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) TM497FBK32 PARAMETER MIN MAX TM893GBK32 MIN MAX UNIT Ci(A) Input capacitance, address inputs 50 80 pF Ci(R) Input capacitance, RAS inputs 33 28 pF Ci(C) Input capacitance, CAS inputs 17 28 pF Ci(W) Input capacitance, write-enable input 66 112 pF Co(DQ) Output capacitance on DQ pins 9 14 pF NOTE 5: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature ’497FBK32-60 ’893GBK32-60 PARAMETER MIN MAX ’497FBK32-70 ’893GBK32-70 MIN MAX ’497FBK32-80 ’893GBK32-80 MIN UNIT MAX tAA tCAC Access time from column address 30 35 40 ns Access time from CAS low 15 18 20 ns tCPA tRAC Access time from column precharge 35 40 45 ns Access time from RAS low 60 70 80 ns tCLZ tOH CAS to output in low-impedance state 0 0 0 Output disable time from start of CAS high 3 3 3 tOFF Output disable time after CAS high (see Note 6) NOTE 6: tOFF is specified when the output is no longer driven. 0 15 0 18 0 ns ns 20 ns EDO timing requirements over recommended ranges of supply voltage and operating free-air temperature ’497FBK32-60 ’893GBK32-60 MIN MAX ’497FBK32-70 ’893GBK32-70 MIN MAX ’497FBK32-80 ’893GBK32-80 MIN UNIT MAX tHPC tPRWC Cycle time, EDO page mode read or write 25 30 35 ns Cycle time, EDO read-write 80 90 100 ns tCSH tDOH Hold time, CAS after RAS 50 55 60 ns 3 3 3 ns tCAS tWPE Pulse duration, CAS Pulse duration, W (output disable only) 5 5 5 ns tCP Precharge time, CAS 5 5 5 ns Hold time, output after RAS 10 POST OFFICE BOX 1443 10 000 • HOUSTON, TEXAS 77251–1443 12 10 000 15 10 000 ns 9 TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature ’497FBK32-60 ’893GBK32-60 MIN MAX ’497FBK32-70 ’893GBK32-70 MIN MAX ’497FBK32-80 ’893GBK32-80 MIN UNIT MAX tRC tPC Cycle time, random read or write (see Note 7) 110 130 150 ns Cycle time, page-mode read or write (see Notes 7 and 8) 40 45 50 ns tRASP tRAS Pulse duration, page-mode, RAS low 60 100 000 70 100 000 80 100 000 ns Pulse duration, non-page-mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS tCP Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns Pulse duration, CAS high 10 10 10 ns tRP tWP Pulse duration, RAS high (precharge) 40 50 60 ns Pulse duration, W low 10 10 10 ns tASC tASR Setup time, column address before CAS low 0 0 0 ns Setup time, row address before RAS low 0 0 0 ns tDS tRCS Setup time, data before CAS low 0 0 0 ns Setup time, W high before CAS low 0 0 0 ns tCWL tRWL Setup time, W-low before CAS high 10 12 15 ns Setup time, W-low before RAS high 10 12 15 ns tWCS tWRP Setup time, W-low before CAS low 0 0 0 ns Setup time, W-high before RAS low (CBR refresh only) 10 10 10 ns tCAH tRHCP Hold time, column address after CAS low 10 12 15 ns Hold time, RAS high after CAS precharge 35 40 45 ns tDH tRAH Hold time, data after CAS low 10 12 15 ns Hold time, row address after RAS low 10 10 10 ns tRCH tRRH Hold time, W high after CAS high (see Note 9) 0 0 0 ns Hold time, W high after RAS high (see Note 9) 0 0 0 ns tWCH tWRH Hold time, W low after CAS low 10 12 15 ns Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns tCHR tCRP Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns Delay time, CAS high to RAS low 5 5 5 ns tCSH tCSR Delay time, RAS low to CAS high 50 55 60 ns tRAD tRAL Delay time, RAS low to column address (see Note 10) 15 Delay time, column address to RAS high 30 35 40 tCAL tRCD Delay time, column address to CAS high 30 35 40 Delay time, RAS low to CAS low (see Note 10) 20 tRPC tRSH Delay time, RAS high to CAS low (CBR only) tREF tT Refresh time interval Delay time, CAS low to RAS low (CBR refresh only) Delay time, CAS low to RAS high 5 30 45 15 20 52 15 20 0 0 0 12 15 3 30 All cycles assume tT = 5 ns. To assure tPC min, tASC should be greater than or equal to tCP. Either tRRH or tRCH must be satisfied for a read cycle. The maximum value is specified only to assure access time. POST OFFICE BOX 1443 5 35 10 32 Transition time NOTES: 7. 8. 9. 10. 10 5 • HOUSTON, TEXAS 77251–1443 32 3 30 3 ns 40 ns ns ns 60 ns ns ns 32 ms 30 ns TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 MECHANICAL DATA BK (R-PSIM-N72) SINGLE-IN-LINE MEMORY MODULE 0.054 (1,37) 0.047 (1,19) 4.255 (108,08) 4.245 (107,82) 0.125 (3,18) TYP 1.005 (25,53) 0.995 (25,27) 0.128 (3,25) 0.120 (3,05) 0.050 (1,27) 0.010 (0,25) MAX 0.400 (10,16) TYP 0.040 (1,02) TYP 0.208 (5,28) MAX 0.360 (9,14) MAX (For Double-Sided SIMM) 4040197 / B 02/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. device symbolization TM497FBK32 -SS YY MM T -SS YYMMT = Year Code = Month Code = Assembly Site Code = Speed Code NOTE: The location of the part number may vary. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated