ETC NM9715

Nm9715
PCI Dual 1284 Printer Ports
Features
Applications
• Single 5V operation
• Low power
• Pin-to-pin compatible to Nm9705
• PCI compatible dual 1284 printer port
• Multi-mode compatible controller (SPP, PS2, EPP,
ECP)
• Fast data rates up to 1.5 Mbytes/s (parallel port)
• Re-map function for legacy ports
• 16-byte FIFO (parallel)
• Microsoft Windows compatible registers
• Software programmable mode selects
• 128-pin QFP package
• Printer server
• Portable backup units
• Printer interface
• Add-on I/O cards
General Description
Ordering Information
The Nm9715 is a dual 1284 parallel port controller with
PCI bus interface. Nm9715 fully supports the existing
Centronics printer interface as well as PS/2, EPP, and
ECP modes.
Application Notes
• AN-9715
Commercial Grade
Nm9715CV
128-QFP
0° C to +70° C
The Nm9715 is ideally suited for PC applications, such
as high speed parallel ports. The Nm9715 is available
in a 128-pin QFP package. It is fabricated using an advanced submicron CMOS process to achieve low drain
power and high speed requirements.
MosChip Semiconductor ♦ 3335 Kifer Rd, Santa Clara, CA 95051 ♦ Tel (408) 737-7141 ♦ Fax (408) 737-7708
Nm9715
PCI Dual 1284 Printer Ports
Nm9715 Block Diagram
PDA0 - PDA7
1284
Parallel Port-A
CLK
P
C
I
P
C
I
nRESET
AD0 - AD31
FAULT-A, SLCT-A, PE-A
nACK-A, nBUSY-A
nSTROBE-A, nAUTOFDX-A
INIT-A, nSLCTIN-A
PDB0 - PDB7
nFRAME, nIRDY
nLOCK, IDSEL,
B
R
I
D
G
E
I
N
T
E
R
F
A
C
E
nTRDY, nSTOP,
nDEVSEL,
nPARR,nSERR
nC/BE0, nC/BE1,
nC/BE3, nC/BE4
1284
Parallel Port-B
FAULT-B, SLCT-B, PE-B
nACK-B, nBUSY-B
nSTROBE-B, nAUTOFDX-B
INIT-B, nSLCTIN-B
nINTA
PCI Clk
Page 2
EE-EN
EE-DI
EE-CS
EE-DO
EE-CLK
EEprom
Interface
Rev. 1.2
Nm9715
PCI Dual 1284 Printer Ports
128-Pin QFP Package
AD29
AD30
AD31
GND
N.C.
EE-EN
CLK
nRESET
nINTA
GND
EE-DI
EE-DO
EE-CLK
EE-CS
VCC
PB0
PB1
PB2
PB3
PB4
GND
PB5
PB6
PB7
VCC
N.C.
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
N.C.
2
101
N.C.
AD27
3
100
N.C.
AD26
4
99
GND
AD25
5
98
PA7
AD24
6
97
PA6
GND
7
96
PA5
nC/BE3
8
95
PA4
IDSEL
9
94
GND
VCC
10
93
PA3
AD23
11
92
PA2
AD22
12
91
PA1
AD21
13
90
PA0
AD20
14
89
VCC
AD19
15
88
GND
AD18
16
87
PEA
AD17
17
86
nACKA
AD16
18
85
nBUSYA
VCC
19
84
SLCTA
GND
20
83
nFAULTA
GND
21
82
VCC
nC/BE2
22
81
nSTROBEA
nFRAME
23
80
nAUTOFDA
nIRDY
24
79
nINITA
nTRDY
25
78
nSLCTINA
nDEVSEL
26
77
GND
nSTOP
27
76
nSTROBEB
nLOCK
28
75
nAUTOFDB
nPERR
29
74
nINITB
nSERR
30
73
nSLCTINB
PAR
31
72
nFAULTB
nC/BE1
32
71
nACKB
GND
33
70
nBUSYB
AD15
34
69
PEB
AD14
35
68
SLCTB
AD13
36
67
N.C.
AD12
37
66
VCC
AD11
38
65
N.C.
Nm9715CV
1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VCC
AD10
AD9
AD8
nC/BE0
GND
GND
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VCC
N.C.
N.C.
N.C.
N.C.
N.C.
GND
N.C.
N.C.
N.C.
N.C.
Rev. 1.2
VCC
AD28
Page 3
Nm9715
PCI Dual 1284 Printer Ports
Pin Name
128
Type
nRESET
121
I
PCI system reset (active low). Resets all internal register, sequencers, and
signals to a consistent state. During reset condition, AD31-0 and nSER are
three-stated.
AD31-29 126-128
I/O
Multiplexed PCI address/data bus. A bus transaction consists of an address
phase followed by one or more data phases. During the address phase AD310 contain a physical address. Write data is stable and valid when nIRDY and
nTRDY are asserted (active).
AD28-24
2-6
I/O
See AD31-29 description.
AD23-16
11-18
I/O
See AD31-29 description.
AD15-11
34-38
I/O
See AD31-29 description.
AD10-8
40-42
I/O
See AD31-29 description.
AD7-0
46-53
I/O
See AD31-29 description.
nFRAME
23
I
Frame is driven by the current master to indicate the beginning and duration
of an access. nFRAME is asserted to indicate a bus transaction is beginning.
While nFRAME is active, data transfer continues.
nIRDY
24
I
Initiator Ready. During a write, nIRDY asserted indicates that the initiator is
driving valid data onto the data bus. During a read, nIRDY asserted indicates
that the initiator is ready to accept data from the Nm9715.
nTRDY
25
O
Target Ready (three-state). It is asserted when Nm9715 is ready to complete
the current data phase.
nSTOP
27
O
Nm9715 asserts nSTOP to indicate that it wishes the initiator to stop the
transaction in process on the current data phase.
nLOCK
28
I
Lock indicates an atomic operation that may require multiple transactions to
complete.
IDSEL
9
I
Initialization Device Select. It is used as a chip select during configuration
read and write transactions.
nDEVSEL
26
O
Device Select (three-state). Nm9715 asserts nDEVSEL when the Nm9715
has decoded its address.
nPERR
29
O
Parity Error (three-state). Is used to report parity errors during all PCI transactions except a special cycle. The minimum duration of nPERR is one clock
cycle.
Page 4
Description
Rev. 1.2
Nm9715
PCI Dual 1284 Printer Ports
Pin Name
128
Type
nSERR
30
O
System Error (open drain). This pin goes low when address parity errors are
detected.
PAR
31
I/O
Even Parity. Parity is even parity across AD31-0 and nC/BE3-0. PAR is stable
and valid one clock after the address phase. For data phase, PAR is stable
and valid one clock after either nIRDY is asserted on a write transaction, or
nTRDY is asserted on a read transaction.
nC/BE3
8
I
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used
as byte enables. nC/BE3 applies to byte “3”.
nC/BE2
22
I
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used
as byte enables. nC/BE2 applies to byte “2”.
nC/BE1
32
I
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used
as byte enables. nC/BE1 applies to byte “1”.
nC/BE0
43
I
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used
as byte enables. nC/BE0 applies to byte “0”.
nINTA
120
O
PCI active low interrupt output (open-drain). This signal goes low (active)
when an interrupt condition occurs.
EE-CS
115
O
External EEprom chip select (active high). After power on reset, Nm9715
reads the EEprom and loads the read-only configuration registers sequentially from the first 64 bytes in the EEprom.
EE-CLK
116
O
External EEprom clock.
EE-DI
118
I
External EEprom data input.
EE-DO
117
O
External EEprom data output.
EE-EN
123
I
Enable/Disable external EEprom (active high, internal pull-up). External
EEprom can be disabled when this pin is tied to GND or pulled low. When
external EEprom is disabled, the default values for Nm9715 will be loaded
into PCI configuration register.
SLCTB
SLCTA
68
84
I
Peripheral/printer selected (internal pull-up). This pin is set to high by peripheral/printer when it is selected.
Rev. 1.2
Description
Page 5
Nm9715
PCI Dual 1284 Printer Ports
Pin Name
128
Type
PEB
PEA
69
87
I
Paper empty (internal pull-up). This pin is set to high by peripheral/printer
when printer paper is empty.
nBUSYB
nBUSYA
70
85
I
Peripheral/printer busy (internal pull-up). This pin is set to high by peripheral/
printer when printer or peripheral is not ready to accept data.
nACKB
nACKA
71
86
I
Peripheral/printer data acknowledge (internal pull-up). This pin is set to low
by peripheral/printer to indicate a successful data transfer has taken place.
During SPP mode when interrupt is enabled, nINTA pin follows the nACKA/
nACKB input pins state.
nFAULTB
nFAULTA
72
83
I
Peripheral/printer data error (internal pull-up). This pin is set to low by peripheral/printer during error condition.
nSTROBEB 76
nSTROBEA 81
O
Peripheral/printer data strobe (open drain, active low). On the rising edge of
the nSTROBEA/nSTROBEB, data is latched into printer port.
nAUTOFDB 75
nAUTOFDA 80
O
Peripheral/printer auto feed (open-drain, active low). Continuous autofed paper is selected when this pin is set to low.
nINITB
nINITA
74
79
O
Initialize the peripheral/printer (open drain, active low). When set to low, peripheral/printer starts it’s initialization routine.
nSLCTINB
nSLCTINA
73
78
O
Peripheral/printer select (open-drain, active low). Selects the peripheral/printer
when it is set to low.
PB7-PB5 105-107
PA7-PA4 98-95
I/O
Peripheral/printer data ports.
PB4-PB0 109-113
PA3-PA0 93-90
I/O
Peripheral/printer data ports.
Page 6
Description
Rev. 1.2
Nm9715
PCI Dual 1284 Printer Ports
Pin Name
128
Type
Description
GND
7,20,21,
33,44,45,
60,77,88,
94,99,108
119,125
Pwr
Power and signal ground.
VCC
1,10,19,
39,54,66,
82,89,104,
114
Pwr
5V supply.
Conventions
The following is a list of the documentation conventions to help familiarize you with Nm9715 document:
nACK is used in the document to replace nACKA and nACKB.
nBUSY is used in the document to replace nBUSYA and nBUSYB.
SLCT is used in the document to replace SLCTA and SLCTB.
nFAULT is used in the document to replace nFAULTA and nFAULTB.
PD7-PD0 are used in the document to replace PA7-PA0 and PB7-PB0.
nSTROBE is used in the document to replace nSTROBEA and nSTROBEB.
nAUTOFDX is used in the document to replace nAUTOFDA and nAUTOFDB.
nINIT is used in the document to replace nINITA and nINITB.
nSLCTIN is used in the document to replace nSLCTINA and nSLCTINB.
Rev. 1.2
Page 7
Nm9715
PCI Dual 1284 Printer Ports
PCI bus operation:
The execution of PCI bus transaction takes place in
broadly five stages: address phase; transaction claiming; data phase(s); final data transfer; and transaction
completion.
Address phase:
Every PCI transaction starts off with an address phase,
one PCI clock period in duration. During address phase
the initiator (also known as current bus master) identifies the target device (via the address) and type of transaction (via the command). The initiator drives the 32-bit
address onto 32-bit address/data bus and 4-bit command onto 4-bit command/byte enable bus. The initiator also asserts the nFRAME signal during the same
clock cycle to indicate the presence of valid address
and transaction type on those buses. The initiator supplies start address and command type for one PCI clock
cycle. The target, Nm9715, generates the subsequent
sequential addresses for burst transfers. The address/
data bus becomes data bus and command/byte enable
bus becomes byte enable bus for the remainder of the
clock cycles of that transaction. The target (Nm9715)
latches the address and command type on the next rising edge of PCI clock, as do all the devices on that PCI
bus. The target (Nm9715) decodes the address and
determines whether it is being addressed, and decodes
the command to determine the type of transaction.
Claiming the transaction:
When Nm9715 determines that it is the target of a transaction, it claims the transaction by asserting nDEVSEL.
Data phase(s):
The data phase of a transaction is the period during
which a data object is transferred between the initiator
and the target (Nm9715). The number of data bytes to
be transferred during a data phase is determined by
the number of command/byte enable signals that are
asserted by the initiator during the data phase. Each
data phase is at least one PCI clock period in duration.
Both initiator and target must indicate that they are ready
to complete a data phase. If not, the data phase is extended by a wait state of one clock period in duration.
The initiator and the target indicate this by asserting
nIRDY and nTRDY respectively and the data transfer is
completed at the rising edge of the next PCI clock.
Page 8
Transaction duration:
The initiator, as stated earlier, gives only start address
during address phase but does not tell the number of
data transfers in a burst transfer transaction. However,
the initiator indicates the completion of data transfer of
a transaction by asserting nIRDY and de-asserting
nFRAME during the last data transfer phase. The transaction, however, does not complete until the target has
also asserted the nTRDY signal and the last data transfer takes place. At this point the nTRDY and nDEVSEL
are de-asserted by the target.
Transaction completion:
When all of nIRDY, nTRDY, nDEVSEL, and nFRAME
are in inactive state (high state), the bus is in idle state.
The bus is ready to be claimed by another bus master.
Internal address select configuration
I/O Address Function
X00-XX07
YX00
YX01
YX02
Standard Printer Port A
Printer Configuration Register A
Printer Configuration Register B
Printer ECR Register
ZX00-XX07
WX00
WX01
WX02
Standard Printer Port B
Printer Configuration Register A
Printer Configuration Register B
Printer ECR Register
X, Y, Z, and W are PCI assigned addresses
Rev. 1.2
Nm9715
PCI Dual 1284 Printer Ports
Nm9715 configuration space register map
AD 31-23
AD 22-16
AD 15-8
AD 7-0
Device ID (9715)
Vendor ID (9710)
00H
Status
Command
04H
Class Code (070102)
BIST
Header Type
Latency Timer
Max Latency (00)
Revision ID (01)
08H
Cache Size (08)
0CH
I/O (X)Base Address
10H
I/O (Y)Base Address
14H
I/O (Z) Base Address
18H
I/O (W)Base Address
1CH
Reserved
20H
Reserved
24H
Reserved
28H
Subsystem ID
Rev. 1.2
Addr
Subsystem Vendor ID
2CH
Reserved
30H
Reserved
34H
Reserved
38H
Min Grant (00)
Interrupt Pin (01)
Interrupt Line
3CH
Page 9
Nm9715
PCI Dual 1284 Printer Ports
Printer Register Table
Ex A2 A1 A0
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
E3 0
0
0
DPR
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
E3 0
0
1
DSR
nBUSY
nACK
PE
SLCT
FAULT
INT
state
“0”
EPP
TIMEOUT
E3 0
1
0
DCR
“0”
“0”
DIR
INTA
nSLCTIN
INIT
E3 0
1
1
EPP
Address
ADD-7
ADD-6
ADD-5
ADD-4
ADD-3
ADD-2
ADD-1
ADD-0
E3 1
0
0
EPP
data
DAT-7
DAT-6
DAT-5
DAT-4
DAT-3
DAT-2
DAT-1
DAT-0
E3 1
0
1
EPP
data
DAT-15
DAT-14
DAT-13
DAT-12
DAT-11
DAT-10
DAT-9
DAT-8
E3 1
1
0
EPP
data
DAT-23
DAT-22
DAT-21
DAT-20
DAT-19
DAT-18
DAT-17
DAT-16
E3 1
1
1
EPP
data
DAT-31
DAT-30
DAT-29
DAT-28
DAT-27
DAT-26
DAT-25
DAT-24
E4 0
0
0
C-FIFO
CDAT-7
CDAT-6
CDAT-5
CDAT-4
CDAT-3
CDAT-2
CDAT-1
CDAT-0
E4 0
0
0
CONF-A
“1”
“0”
“0”
“1”
“0”
“1”
“0”
“0”
E4 0
0
1
CONF-B
“0”
INT
Pin
“0”
“0”
“0”
“0”
“0”
“0”
E4 0
1
0
ECR
ErrIntrEn
enable
“0”
Service
Int
FIFO
full
FIFO
empty
MODE
select
nAUTOFD nSTROBE
E3: Internal standard printer chip select (X, Z)
E4: Internal printer configuration register chip select (Y, W)
Page 10
Rev. 1.2
Nm9715
PCI Dual 1284 Printer Ports
Data Register
Data register is cleared at initialization by RESET. During a write operation, the data register latches the contents of the data bus with the rising edge of the nIOW
input. The contents of this register are buffered and
output onto the PD7-PD0 ports. During a read operation PD7-PD0 ports are buffered and output to the host
CPU on the falling edge of the nIOR input.
Device Status Register
The contents of this register are latched for the duration of the nIOR cycle. The bits of the status port are
defined as follows.
DSR Bit-0:
0 = Normal.
1 = 10µs timeout (EPP mode only). Cleared by writing 1
into DSR register or consecutive reads (after the first
read) always returns to “0”.
DSR Bit-1:
Not used, set to “0”.
DSR Bit-2:
0 = nACK input pin is at low state (INT follows the nACK
pin) when SPP mode is selected. Normal (no interrupt)
when PS/2 mode is selected.
1 = Normal (no interrupt). In standard mode operation,
INT is active (interrupt is generated on the rising edge
of the nACK). It is cleared when DSR is read.
DSR Bit-3:
0 = Printer reports error condition.
1 = Normal operation.
DSR Bit-4:
0 = Printer is off line.
1 = Printer is on line.
DSR Bit-5:
0 = Normal operation
1 = Paper end/empty is detected
DSR Bit-6:
0 = State of the nACK pin (ACK = low).
1 = State of the nACK pin (ACK = high).
Rev. 1.2
DSR Bit-7:
0 = nBUSY pin is high, printer is not ready to take data.
1 = nBUSY pin is low, printer is read to take data.
Device Control Register
DCR Bit-0:
0 = Sets the nSTROBE pin to high.
1 = Sets the nSTROBE pin to low. PD7-PD0 data are
latched into printer
DCR Bit-1:
0 = Sets the nAUTOFD pin to high. Printer generates
auto line feed after each line is printed.
1 = Sets the nAUTOFD pin to low. No auto feed function.
DCR Bit-2:
0 = Sets the INIT pin to high.
1 = Sets the INIT pin to low. Peripheral/printer starts its
initialization routine.
DCR Bit-3:
0 = Sets the nSLCTIN pin to high. Selects the printer.
1 = Sets the nSLCTIN pin to low. Printer is not selected.
DCR Bit-4:
0 = Disables Printer interrupt function. nACK pin has
no effect on the INT pin.
1 = Enables Printer interrupt function. The INT follows
the nACK input pin during standard mode, latches high
on the rising edge of the nACK when PS/2 mode is selected.
DCR Bit-5:
0 = PD7-PD0 pins are out put mode.
1 = PD7-PD0 pins are input mode.
DCR Bits 7-6:
Not used, set to “0”.
Config-A Register
Configuration A register (read only). Reading this register returns 10010100. Writing to this register has no
effect and the data is ignored.
Page 11
Nm9715
PCI Dual 1284 Printer Ports
Config-B Register
Configuration B register. This register allows software
to control the selecting of interrupts. A read-write implementation implies a “software-configurable” device.
Reading this register returns the configured interrupt
and interrupt pin state. If a value is not set to 000 (the
jumper-default) then it is assumed that the value in the
register is correct and software will use the default interrupt.
Config-B Bit-7:
Not used, set to “0”.
Config-B Bit-6:
0 = Configured printer interrupt pin is low.
1 = Configured printer interrupt pin is high.
Mode “000”
SPP/Centronics/Compatible Mode
Forward direction only. The direction bit is forced to “0”
and PD7-PD0 are set to output direction. The Nm9715
is under software control. This mode defines the protocol used by most PCs to transfer data to a printer. It is
commonly called the Centronics mode and is the method
utilized with the standard parallel port. Data is placed
on the PD7-PD0 ports, the printer status is checked via
DSR register. If no error condition is flagged and printer
is not busy, software toggles the nSTROBE pin to latch
the PD7-PD0 data into printer. This operating cycle continues when printer/peripheral issues data acknowledge
signal (pulses the nACK and nBUSY pin).
Nibble Mode
Extended Control Register (ECR)
The nibble mode is the most common way to get reverse channel data from a printer or peripheral. This
mode is usually combined with the Centronics mode or
a proprietary forward channel mode to create a bi-directional channel. In this mode printer status bits are
used as nibble bits.
This register controls the mode selection operation.
Bits order for nibble mode
Config-B Bit 7-0:
Interrupt pin select register.
Bit-7
Bit-6
Bit-5
Operating Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SPP
PS/2
PPF (FIFO mode)
ECP
EPP
Not used
FIFO test
Config A/B enable
Mode changes
After hardware reset, PS/2 mode is selected as default
mode. It is required to select mode 000 or 001 between
any other mode configuration.
PINS
nBUSY
PE
SLCT
nFAULT
nBUSY
PE
SLCT
nFAULT
DATA Bits
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Mode “001”
PS/2, Byte Mode
The byte mode protocol is used to transfer bi-directional
data via PD7-PD0 ports without FIFO utilization. The
direction of the port is controlled with DIR bit in DCR
register. PS/2-byte use SPP protocol for data transfer.
DCR Bit-5:
0 = PD7-PD0 pins are out put mode.
1 = PD7-PD0 pins are input mode.
Page 12
Rev. 1.2
Nm9715
PCI Dual 1284 Printer Ports
Mode “010”
FIFO Output Mode
In this mode, bytes written to the FIFO are transmitted
automatically using the SPP/Centronics standard protocol.
Mode “011”
Extended Capability Port “ECP” Mode
The ECP provides an advanced mode for communication with printer or peripherals. Like EPP protocol, ECP
provides 16-byte FIFO for a high performance bi-directional communication path between the host adapter
and the peripheral. The ECP protocol provides the following cycle types in both the forward and reverse directions.
• Data cycle
• Command cycles
• Run-Length counts (RLE)
• Channel address
The RLE feature enables real time data compression
that can achieve compression ratios up to 64:1. This is
particularly useful for printers and peripherals that are
transferring large raster images that have large strings
of identical data. In order for the RLE mode to be enabled, both the host and peripheral must support it.
Channel addressing is intended to address multiple logical devices within a single physical device, like modem/
FAX/printer in one physical package.
Mode “100”
Enhanced Parallel Port “EPP” Mode
In EPP mode, nSLCTIN (address strobe) and nAUTOFD
(data strobe) are automatically generated while
nSTROBE indicates a write or read cycle. Additional I/
O addresses are defined for data and address access
and when these locations are used, handshaking is
performed automatically by Nm9715.
ECR Bit-4:
Error Interrupt Enable.
0 = Enable nFAULT interrupt. nFAULT pin is used as
source of interrupt.
1 = Disable nFAULT interrupt (nACK is used as source
of interrupt).
ECR Bit-3:
0 = normal operating mode.
ECR Bit-2:
1 = Disables service interrupt.
0 = Enables one of the following 3 cases of interrupts.
One of the 3 service interrupts has occurred. Service
interrupt bit will be set to a “1” by hardware. Writing this
bit to a “1” will not cause an interrupt.
Port Direction (DCR Bit-5 = 0). This bit will be set to “1”
whenever there are write interrupt thresholds (4 characters) or more bytes free in the FIFO. The Nm9715
generates interrupt when this condition is occurred and
service interrupt is cleared to “0”.
Port Direction (DCR Bit-5 = 1). This bit will be set to “1”
whenever there are read iInterrupt thresholds (12 characters) or more bytes to be read from the FIFO. The
Nm9715 generates interrupt when this condition is occurred and service interrupt is cleared to “0”.
ECR Bit-1:
0 = One or more empty locations in FIFO is available.
1 = FIFO full.
ECR Bit-0:
0 = One or more data in FIFO.
1 = FIFO empty.
Mode “110”
FIFO Test Mode
In this mode, the FIFO can be written and read in any
direction, but no data will be transmitted on the PD7PD0 ports. Whatever data is in the FIFO may be displayed on the PD7-PD0 ports.
Rev. 1.2
Page 13
Nm9715
PCI Dual 1284 Printer Ports
Master rest conditions
Register
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
DPR
DSR
DCR
EPP
C-FIFO
CONF-A
CONF-B
ECR
X
0
0
0
0
1
0
0
X
1
0
0
0
0
X
0
X
1
0
0
0
0
0
0
X
1
0
0
0
1
0
0
X
1
0
0
0
0
0
0
X
0
0
0
0
1
0
0
X
0
0
0
0
0
0
0
X
0
0
0
0
0
0
1
Page 14
Rev. 1.2
Nm9715
PCI Dual 1284 Printer Ports
Absolute Maximum Ratings
Supply Range
Voltage at any pin
Operating Temperature
Storage Temperature
Package Dissipation
ESD
Latch up
7 Volts
GND – 0.3 to VCC +0.3
-45° C to 90° C
-65° C to 150° C
500 mW
±2000 Volts
220 mA
DC Electrical Specification
T = 0° C to 70° C (-40° C to +85° C for industrial “E” grade parts), VCC = 5V ± 10% unless otherwise specified.
Symbol
Parameter
5V
Unit
Min
Max
-0.3
2.0
0.8
Vil
Vih
Input Low voltage
Input High voltage
Vt-
Schmitt trigger negative
going threshold voltage
1.10
V
Vt+
Schmitt trigger positive
going threshold voltage
1.87
V
Vol
Voh
Output low voltage
Output high voltage
Iil
Iih
Condition
V
V
0.4
V
C
Input low current
Input high current
±1
±1
µA
µA
Ioz
Three state leakage current
±10
µA
Cin
Cout
Input capacitance
Output capacitance
5
5
pF
pF
Icc
Operating current
60
mA
Revision
Notes
Date
Pin description changes.
Ordering information changed.
7/00
7/02
1.1
1.2
Rev. 1.2
3.5
3
3
Iol=4 mA
Ioh=4 mA
No load
Page 15
Nm9715
PCI Dual 1284 Printer Ports
128-Pin QFP (14X20) Package
HE
E
128
103
102
1
65
38
39
64
D
HD
e
b
A2
A1
c
L
SYMBOL
Page 16
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
A1
A2
0.10
2.73
0.30
2.97
0.004
0.107
0.012
0.117
b
c
e
L
0.17
0.09
0.27
0.20
0.007
0.004
0.011
0.008
0.70
1.03
0.029
0.041
HD
D
23.00
19.90
23.40
20.10
0.906
0.783
0.921
0.791
HE
E
17.00
13.90
17.40
14.10
0.669
0.547
0.685
0.555
0.50 TYP
0.020 TYP
Rev. 1.2
Nm9715
PCI Dual 1284 Printer Ports
IMPORTANT NOTICE
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Printed July 31, 2002
Rev. 1.2
Page 17