N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM P01N02LMB SOT-23 (M3) D PRODUCT SUMMARY V(BR)DSS RDS(ON) ID 25V 180mΩ 1.2A 1. GATE 2. DRAIN 3. SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Gate-Source Voltage TC = 25 °C Continuous Drain Current LIMITS UNITS VGS ±15 V 1.2 ID TC = 100 °C Pulsed Drain Current SYMBOL 1 1.0 IDM TC = 25 °C Power Dissipation 12 0.6 PD TC = 100 °C Operating Junction & Storage Temperature Range 1 Lead Temperature ( /16” from case for 10 sec.) A W 0.5 Tj, Tstg -55 to 150 TL 275 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM Junction-to-Case RθJC 65 Junction-to-Ambient RθJA 230 UNITS °C / W 1 Pulse width limited by maximum junction temperature. ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC V(BR)DSS VGS = 0V, ID = 250 µA 25 VGS(th) VDS = VGS, ID = 250 µA 0.7 Gate-Body Leakage IGSS VDS = 0V, VGS = ±15V ±250 Zero Gate Voltage Drain Current IDSS VDS = 20V, VGS = 0V 25 VDS = 20V, VGS = 0V, TJ = 125 °C 250 Drain-Source Breakdown Voltage Gate Threshold Voltage 1 On-State Drain Current ID(ON) 1 Drain-Source On-State Resistance 1 Forward Transconductance VDS = 10V, VGS = 10V RDS(ON) gfs 1 V 1.0 2.5 1.2 nA µA A VGS = 7V, ID = 1.2A 220 250 VGS = 10V, ID = 1.2A 180 220 VDS = 20V, ID = 1.2A 16 mΩ S AUG-18-2001 N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM P01N02LMB SOT-23 (M3) DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 85 Qg 11 Total Gate Charge 2 2 Gate-Source Charge 2 Gate-Drain Charge 2 Turn-On Delay Time 2 Rise Time 2 Turn-Off Delay Time 2 Fall Time 120 VGS = 0V, VDS = 15V, f = 1MHz pF 100 Qgs VDS = 0.5V(BR)DSS, VGS = 10V, 3.0 Qgd ID = 1A 5.8 td(on) nC 7 tr VDS = 15V, RL = 1Ω 20 td(off) ID ≅ 1A, VGS = 10V, RGS = 50Ω 13 tf nS 19 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current Pulsed Current 3 1 Forward Voltage IS 1.2 ISM 12 VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr IF = IS, VGS = 0V IF = IS, dlF/dt = 100A / µS A 1.3 V 70 nS 0.22 µC Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 1 2 REMARK: THE PRODUCT MARKED WITH “102B” 2 AUG-18-2001 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor P01N02LMB SOT-23 (M3) SOT-23 (M3) MECHANICAL DATA mm mm Dimension Dimension Min. A Typ. Max. 0.95 Min. Typ. Max. H 0.10 0.15 0.25 0.37 B 2.60 2.80 3.00 I C 1.40 1.60 1.80 J D 2.70 2.90 3.10 K E 1.00 1.10 1.30 L F 0.00 0.10 M G 0.35 0.50 N 0.40 3 AUG-18-2001