P1402CDG N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM TO-252 (DPAK) Lead-Free D PRODUCT SUMMARY V(BR)DSS RDS(ON) ID 20 14mΩ 45A 1. GATE 2. DRAIN 3. SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Gate-Source Voltage TC = 25 °C Continuous Drain Current LIMITS UNITS VGS ±12 V 45 ID TC = 100 °C Pulsed Drain Current SYMBOL 1 30 IDM TC = 25 °C Power Dissipation 48 PD TC = 100 °C Operating Junction & Storage Temperature Range 1 Lead Temperature ( /16” from case for 10 sec.) A 140 W 20 Tj, Tstg -55 to 150 TL 275 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM Junction-to-Case RθJC 2.6 Junction-to-Ambient RθJA 110 UNITS °C / W 1 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1％ 2 ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = 250µA VGS(th) VDS = VGS, ID = 250µA Gate-Body Leakage IGSS VDS = 0V, VGS = ±12V ±100 Zero Gate Voltage Drain Current IDSS VDS = 16V, VGS = 0V 1 VDS = 13.2V, VGS = 0V, TJ = 125 °C 10 On-State Drain Current1 ID(ON) Drain-Source On-State Resistance1 RDS(ON) Gate Threshold Voltage Forward Transconductance1 gfs VDS = 5V, VGS = 4.5V 20 V 0.45 0.75 1.25 45 µA A VGS = 2.5V, ID = 9A 18 26 VGS = 5V, ID = 18A 11 14 VDS = 10V, ID = 18A 26 1 nA mΩ S NOV-05-2004 P1402CDG N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM TO-252 (DPAK) Lead-Free DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 125 Qg 17 Total Gate Charge 2 Gate-Source Charge Gate-Drain Charge 2 2 Turn-On Delay Time 2 Rise Time2 Turn-Off Delay Time 2 Fall Time2 500 VGS = 0V, VDS = 15V, f = 1MHz pF 310 Qgs VDS = 0.5V(BR)DSS, VGS = 5V, 1.5 Qgd ID = 18A 10.5 td(on) nC 7.5 tr VDS = 10V, 83 td(off) ID ≅ 18A, VGS = 5V, RGS = 3.3Ω 18 tf nS 23 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS 45 Pulsed Current ISM 140 Forward Voltage1 VSD 3 Reverse Recovery Time Peak Reverse Recovery Current Reverse Recovery Charge IF = IS, VGS = 0V 1.3 trr IRM(REC) V 37 nS 200 A 0.043 µC IF = IS, dlF/dt = 100A / µS Qrr A Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 1 2 REMARK: THE PRODUCT MARKED WITH “P1402CDG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. 2 NOV-05-2004 N-Channel Logic Level Enhancement Mode Field Effect Transistor P1402CDG TO-252 (DPAK) Lead-Free Body Diode Forward Voltage Variation with Source Current and Temperature 60 VGS= 0V 10 Is - Reverse Drain Current(A) NIKO-SEM T = 125° C 1 25° C 0.1 -55° C 0.01 0.001 0.0001 0 3 0.2 0.4 0.6 0.8 1.0 VSD - Body Diode Forward Voltage(V) 1.2 1.4 NOV-05-2004 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor 4 P1402CDG TO-252 (DPAK) Lead-Free NOV-05-2004 P1402CDG N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM TO-252 (DPAK) Lead-Free TO-252 (DPAK) MECHANICAL DATA mm mm Dimension Dimension Min. Typ. Max. Min. Typ. Max. A 9.35 10.4 H 0.89 2.03 B 2.2 2.4 I 6.35 6.80 C 0.45 0.6 J 5.2 5.5 D 0.89 1.5 K 0.6 1 E 0.45 0.69 L 0.5 0.9 F 0.03 0.23 M 3.96 G 5.2 6.2 N 4.57 5.18 G M 2 1 J I 3 L H D C E F B A K 5 NOV-05-2004